AT91SAM9RL-EK Evaluation Board .................................................................................................................... User Guide 6325C–ATARM–22-Jul-10 AT91SAM9RL-EK Evaluation Board User Guide 6325C–ATARM–22-Jul-10 Table of Contents Section 1 Overview .................................................................................................................... 1-1 1.1 Scope................................................................................................................................. 1-1 1.2 Deliverables ....................................................................................................................... 1-1 1.3 AT91SAM9RL-EK Evaluation Board.................................................................................. 1-1 Section 2 Setting Up the AT91SAM9RL-EK Board .................................................................... 2-1 2.1 Electrostatic Warning ......................................................................................................... 2-1 2.2 Requirements..................................................................................................................... 2-1 2.3 Layout ................................................................................................................................ 2-2 2.4 Powering Up the Board...................................................................................................... 2-4 2.5 Backup Power Supply........................................................................................................ 2-4 2.6 Getting Started................................................................................................................... 2-4 2.7 AT91SAM9RL-EK Block Diagram...................................................................................... 2-5 Section 3 Board Description....................................................................................................... 3-1 3.1 AT91SAM9RL64 Microcontroller ....................................................................................... 3-1 3.2 AT91SAM9RL Block Diagram............................................................................................ 3-4 3.3 Microcontroller ................................................................................................................... 3-4 3.4 Memory .............................................................................................................................. 3-4 3.5 Clock Circuitry.................................................................................................................... 3-4 3.6 Reset Circuitry ................................................................................................................... 3-5 3.7 Shutdown Controller .......................................................................................................... 3-5 3.8 Power Supply Circuitry....................................................................................................... 3-5 3.9 Remote Communication .................................................................................................... 3-5 3.10 Audio Stereo Interface ....................................................................................................... 3-5 3.11 User Interface .................................................................................................................... 3-5 3.12 Debug Interface ................................................................................................................. 3-5 3.13 Expansion Slot ................................................................................................................... 3-6 3.14 PIO Usage ......................................................................................................................... 3-7 Section 4 Jumpers...................................................................................................................... 4-1 4.1 Jumpers ............................................................................................................................. 4-1 4.2 JTAG/ICE........................................................................................................................... 4-1 AT91SAM9RL-EK Evaluation Board User Guide i 6325C–ATARM–22-Jul-10 Table of Contents (Continued) 4.3 Microcontroller Clock ......................................................................................................... 4-2 4.4 Memory .............................................................................................................................. 4-2 4.5 Miscellaneous .................................................................................................................... 4-2 Section 5 Schematics................................................................................................................. 5-1 5.1 Board Schematics.............................................................................................................. 5-1 Section 6 Revision History ......................................................................................................... 6-1 6.1 ii 6325C–ATARM–22-Jul-10 Revision History ................................................................................................................. 6-1 AT91SAM9RL-EK Evaluation Board User Guide Section 1 Overview 1.1 Scope The AT91SAM9RL-EK evaluation kit enables the evaluation of and code development for applications running on an AT91SAM9RL device. It significantly reduces design cycle time, increasing confidence in a right-first-time system solution. This guide focuses on the AT91SAM9RL-EK board as an evaluation platform. The board supports the AT91SAM9RL in an LFBGA217 package. 1.2 Deliverables The AT91SAM9RL-EK package contains the following items: 1.3 an AT91SAM9RL-EK board universal input AC/DC power supply with US, UK and Europe plug adapter one 3V battery backup (CR1225 or equivalent) one A/B-type USB cable one serial RS232 cable one CD-ROM that allows the user to begin evaluating the AT91 ARM® Thumb® 32-bit microcontroller quickly. AT91SAM9RL-EK Evaluation Board The board is equipped with an AT91SAM9RL64 (217-ball LFBGA package) together with the following: 64 Mbytes of SDRAM memory 256 Mbytes of NAND Flash memory one Atmel serial DataFlash® one Atmel TWI serial EEPROM (footprint only) one USB High Speed device port interface one DBGU serial communication port one additional serial communication port with RTS/CTS handshake control JTAG/ICE debug interface one AC97 Audio Codec one 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight one Power LED and two general-purpose LED AT91SAM9RL-EK Evaluation Board User Guide 1-1 6325C–ATARM–22-Jul-10 Overview two user input push buttons one Wakeup input push button one reset push button one MCI SD/MMC card slot four expansion connectors (PIOA, PIOB, PIOC, PIOD) one BGA-like EBI expansion footprint connector one Lithium Coin Cell Battery Retainer for 12 mm cell size 1-2 6325C–ATARM–22-Jul-10 AT91SAM9RL-EK Evaluation Board User Guide Section 2 Setting Up the AT91SAM9RL-EK Board 2.1 Electrostatic Warning Upon delivery, the AT91SAM9RL-EK evaluation board is wrapped in a protective anti-static bag. The board must not be exposed to electrostatic discharges. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other on-board metallic element. 2.2 Requirements In order to set up the AT91SAM9RL-EK evaluation board, the following items are needed: The AT91SAM9RL-EK evaluation board itself AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm AT91SAM9RL-EK Evaluation Board User Guide 2-1 6325C–ATARM–22-Jul-10 Setting Up the AT91SAM9RL-EK Board 2.3 Layout Figure 2-1. AT91SAM9RL-EK Layout - Top View 2-2 6325C–ATARM–22-Jul-10 AT91SAM9RL-EK Evaluation Board User Guide Setting Up the AT91SAM9RL-EK Board Figure 2-2. AT91SAM9RL-EK Layout - Bottom View AT91SAM9RL-EK Evaluation Board User Guide 2-3 6325C–ATARM–22-Jul-10 Setting Up the AT91SAM9RL-EK Board 2.4 Powering Up the Board The AT91SAM9RL-EK requires 5V DC (±5%). DC power is supplied to the board via the 2.1 mm by 5.5 mm socket J1. Coaxial plug center positive standard. 2.5 Backup Power Supply The user has the possibility to plug a battery (3V Lithium Battery CR1225 or equivalent) in order to permanently power the backup part of the device. Refer to Section 4. 2.6 Getting Started The AT91SAM9RL-EK evaluation board is delivered with a CD-ROM containing all necessary information and step-by-step procedures for working with the most common development toolchains. Please refer to this CD-ROM, or to the AT91 web site, http://www.atmel.com/products/AT91/, for the most up-todate information on getting started with the AT91SAM9RL-EK. 2-4 6325C–ATARM–22-Jul-10 AT91SAM9RL-EK Evaluation Board User Guide AT91SAM9RL-EK Evaluation Board User Guide 12VDC 06 - AUDIO USER'S INTERFACE OUT IN 08 - LCD COM0 VCTRL PCI HSYNC DCLK DTMG R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 G0 7 AD0_XR AD1_XL AD2_YT AD3_YB LCDCC LCDPW R LCDHSYNC LCDDOTCK LCDDEN LCDD18 LCDD23 LCDD22 LCDD21 LCDD20 LCDD19 LCDD15 LCDD14 LCDD13 LCDD12 LCDD11 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 TXD0 RXD0 RTS0 CTS0 DTXD DRXD PA8 PCK1 AC97FS AC97CK AC97TX AC97RX PB0 PB1 PW M2 PW M1 PW M0 COMMENT ITALIC FONTS 7 FREE I/O SIGNAL PERIPH PERIPHERAL ASSIGNED I/O SIGNAL Pxx (NAME) SOFTWARE ASSIGNED I/O SIGNAL Pxx Pxx SIGNAL NAMING CONVENTIONS X_RIGHT TOUCH SCREEN X_LEFT Y_UP Y_LOW 3.5" QVGA TXD RXD RTS CTS B5 B4 B3 B2 B1 DTXD DRXD USBCNX DM DP DBGU DEVICE RST# EXT_CLK SYNC BITCLK SDATA_OUT SDATA_IN AUDIO RIGHTCLIC LEFTCLIC USERLED2 USERLED1 SHDN POWERLED 07 - COMMUNICATION MIC USB RS232 LCD INTERFACE 6 PA[0..31] PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 AD0_XR AD1_XL AD2_YT AD3_YB DRXD DTXD TW D0 TW CK0 MISO MOSI SPCK NPCS0 (MCI_CD) MC_DA0 MC_CDA MC_CK MC_DA1 MC_DA2 MC_DA3 TXD0 RXD0 (USBCNX) RTS0 CTS0 5 SDCK SDCKE PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 NRST 5 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 (RIGHT CLIC) (LEFT CLIC) A21_NANDALE A22_NANDCLE NANDOE NANDW E NCS3_NANDCS NANDOE NANDWE D[16..31] RAS CAS SDA10 SDWE SDCS_NCS1 PC[0..31] D[0..31] 4 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 PD[0..21] NCS0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 CFOE_NRD PW M0 PW M1 PW M2 (RDYBSY) PCK1 AC97FS AC97CK AC97TX AC97RX CFW E_NW E_NW R0 CFIOR_NBS1_NW R1 CFIOR_NBS3_NW R3 SDCK SDCKE RAS CAS SDA10 SDW E SDCS_NCS1 2 2 TW CK0 TW D0 NRST MOSI MISO SPCK NPCS0 MC_CK MC_DA0 MC_DA1 MC_DA2 MC_DA3 MC_CDA PA15 A22_NANDCLE A21_NANDALE NANDOE NANDW E NCS3_NANDCS PD17 D[0..7] NCS0 A[0..14] A16 A17 3 3 CFW E_NW E_NW R0 CFOE_NRD CFIOR_NBS1_NW R1 CFIOR_NBS3_NW R3 SDCK SDCKE RAS CAS SDA10 SDW E SDCS_NCS1 A[0..17] D[0..15] LCDHSYNC LCDDOTCK LCDDEN LCDCC LCDPW R NCS0 CFOE_NRD CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 SDCK SDCKE A[0..17] PC[0..31] PD[0..21] PB[0..31] NCS0 CFWE_NWE_NWR0 CFOE_NRD CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 D[0..31] D[0..15] A[0..17] D[0..15] RAS CAS SDA10 SDWE SDCS_NCS1 4 PA[0..31] 09 - EXPANSION CONNECTORS PD[0..21] PC[0..31] PB[0..31] PA[0..31] DM DP NRST SHDN 03 - MICROCONTROLLER PB[0..31] PD[0..21] PC[0..31] PB[0..31] PA[0..31] NRST NANDOE NANDW E PIO USAGE 6 SCL SDA NRST SI SO SCK CS CK DA0 DA1 DA2 DA3 CDA MCI_CD I2C SPI CARD READER 05 - MCI & TWI CLE ALE NANDOE NANDWE NANDCS RDYBSY D[0..7] BA0 BA1 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 SDCK SDCKE RAS CAS SDA10 SDWE SDCS_NCS1 A[0..14] D[0..31] 04 - EBI MEMORY SDRAM NANFLASH 1 1 A B C D Figure 2-3. MMC SD/SDIO 2.7 SERIAL SERIAL EEPROM DATAFLASH 02 - POWER SUPPLY Setting Up the AT91SAM9RL-EK Board AT91SAM9RL-EK Block Diagram AT91SAM9RL-EK Block Diagram 6325C–ATARM–22-Jul-10 2-5 Section 3 Board Description 3.1 AT91SAM9RL64 Microcontroller Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer – 210 MIPS at 190 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support – Mid-level implementation Embedded Trace Macrocell™ Multi-layer AHB Bus Matrix for Large Bandwidth Transfers – Six 32-bit-layer Matrix – Boot Mode Select Option, Remap Command One 32-KByte internal ROM, Single-cycle Access at Maximum Speed One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed – 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB Bus Matrix Single-cycle Accessible on AHB Bus at Bus Speed Single-cycle Accessible on TCM Interface at Processor Speed 2-channel DMA – Memory to Memory Transfer – 16 Bytes FIFO – LInked List External Bus Interface (EBI) – EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® LCD Controller – Supports Passive or Active Displays – Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Virtual Screen Support High Speed (480 Mbit/s) USB 2.0 Device Controller – On-Chip High Speed Transceiver, UTMI+ Physical Interface – Integrated FIFOs and Dedicated DMA – 4 Kbyte Configurable Integrated DPRAM Fully-featured System Controller, including – Reset Controller, Shutdown Controller AT91SAM9RL-EK Evaluation Board User Guide 3-1 6325C–ATARM–22-Jul-10 Board Description – Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock Reset Controller (RSTC) – Based on Two Power-on Reset Cells – Reset Source Identification and Reset Output Control Shutdown Controller (SHDC) – Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) – Selectable 32768 Hz Low-power oscillator or Internal Low-power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 12 MHz On-chip Oscillator for Main System Clock and USB Clock – One PLL up to 240 MHz – One PLL 480 MHz Optimized for USB HS Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – One External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and support for Debug Communication Channel Periodic Interval Timer (PIT) – 20-bit interval timer plus 12-bit interval counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Real-time Clock (RTC) – Time, Date and Alarm 32-bit Parallel Load – Low Power Consumption – Programmable Periodic Interrupt One 6-channel 10-Bit Analog-to-Digital Converter – Touch Screen Interface Compatible with Industry Standard 4-wire Sensitive Touch Panels Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD) – 118 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os for 217-ball BGA package – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up resistor and Synchronous Output 24-channel Peripheral DMA Controller (PDC) One Multimedia Card Interface (MCI) – SDCard/SDIO 1.0 and MultiMedia Card 3.1 Compliant 3-2 6325C–ATARM–22-Jul-10 AT91SAM9RL-EK Evaluation Board User Guide Board Description – Automatic Protocol Control and Fast Automatic Data Transfers with PDC Two Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One AC97 Controller (AC97C) – 6-channel Single AC97 Analog Front End Interface, Slot Assigner Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation, Manchester Encoding/Decoding – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support One Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects – High-speed Synchronous Communications One Three-channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) Two Two-wire Interfaces (TWI) – Compatible with Standard Two-wire Serial Memories – One, Two or Three Bytes for Slave Address – Sequential Read/Write Operations – Master, Multi-master and Slave Mode Operation – Bit Rate: Up to 400 Kbits – General Call Supported in Slave mode – Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only (TWI0 only) SAM-BA Boot Assistant – Default Boot Program – Interface with SAM-BA Graphic User Interface IEEE 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: – 1.08 to 1.32V for VDDCORE, VDDPLLB and VDDBU – 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMI and VDDIOP – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package AT91SAM9RL-EK Evaluation Board User Guide 3-3 6325C–ATARM–22-Jul-10 Board Description AT91SAM9RL Block Diagram TST SLAVE System Controller FIQ JTAG Selection and Boundary Scan In-Circuit Emulator IRQ DBGU ARM926EJ-S Processor PDC TCM ICache Interface 4 Kbytes ITCM DTCM PCK0-PCK1 PLLRCA XIN XOUT PLLA OSC 12M S HS UTMI Transceiver EBI AIC DRXD DTXD BM MASTER LC D LC D0 D LC VS LCD D Y D LC HS NC 23 LD DD YNC O LC DE TC LC DC N K DP C LC W DM R O D AT91SAM9RL Block Diagram TD TDI O TM S TC RTK CK NT RS JT T AG SE L Figure 3-1. G N VD DU D TM VB UT I M D G I FS D D FS P D D H M D SD H P SD M 3.2 PMC I DCache 4 Kbytes USB Device HS LCDC DMA DMA CompactFlash NAND Flash & ECC D SDRAM Controller UPLL 6-layer AHB Bus Matrix WDT PIT D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NWAIT A23-A24 A18-A20 RC XIN32 XOUT32 OSC 32K 4 GPBREG SRAM 64K Bytes RTT SHDN WKUP SHDC VDDBU POR VDDCORE POR Peripheral Bridge ROM 32K Bytes Peripheral DMA Controller A21/NANDALE 2-channel DMA A22/NANDCLE Static Memory Controller APB RTC A25/CFRNW D16-D31 NCS4/CFCS0 PDC RSTC MCI PDC TWI0 TWI1 NRST PDC USART0 USART1 USART2 USART3 PDC SPI PDC PWM TC0 TC1 TC2 AC97 PDC SSC0 SSC1 PDC Touch Screen Controller 6-channel 10-bit ADC NCS5/CFCS1 NCS3/NANDCS NCS2 CFCE1-CFCE2 NANDOE, NANDWE PIOB PIOD DA 0 -D C A3 DA C TW K TW D C 0 K T 0 T W C WC D1 TS K RT 0- 1 C SC S0 TS R K0 -RT 3 D -S S X0 C 3 TX - K D RD 3 0- X TX 3 D D 3 C D 0 R D I0 N SR PC S0 D 0 -N TR PC 0 S SP 3 C M K O PW M SI TC M0 ISO -P LK W TI 0M O T 3 TI A0 CL O -T K B0 IO 2 -T A IO 2 AC B2 AC97C AC 97FK S AC97R X TK 97T 0- X TF T TD 0-TK1 R 0- F1 D T R 0-RD1 F R 0-RD1 K0 F TS -R 1 AD K1 T AD RG 0 AD XP 1 AD XM 2 AD YP 3Y G M P G AD TS PA 4 AD D5 V VD R D EF G AN N A DA N PIOA PIOC 3.3 Microcontroller 3.4 3.5 One AT91SAM9RL64 217-ball LFBGA fitted on board Memory 32 Kbytes of Internal ROM 64 Kbyte of Internal SRAM Atmel serial DataFlash 64 Mbytes of SDRAM memory (32-bit bus width) 256 Mbytes of NAND Flash memory (8-bit bus width) TWI serial EEPROM (footprint only) Clock Circuitry 3-4 6325C–ATARM–22-Jul-10 12 MHz standard crystal for the embedded oscillator AT91SAM9RL-EK Evaluation Board User Guide Board Description 3.6 3.7 3.8 3.9 3.10 3.11 3.12 Software selectable, 32768Hz Low-power external standard crystal Oscillator or Internal Low Power RC Oscillator Reset Circuitry Internal reset controller with bi-directional reset pin External reset pushbutton Shutdown Controller Programmable shutdown and Wake-Up Wake-up push button Power Supply Circuitry On-board 1.2V High Efficiency step-down charge pump regulator with shutdown control On-board 3.3V linear regulator with shutdown control Remote Communication One serial interface (DBGU COM Port) via RS-232 DB9 male socket One additional serial interface (COM Port 1) with RTS/CTS handshake control via RS-232 DB9 male socket One High Speed USB 2.0 port 480 Mbits per second (UDP) Audio Stereo Interface One AC97 audio CODEC with: One 32 Ohm Stereo Headset output (J16) with master volume and mute controls One line-in One Mono/Stereo Microphone input. User Interface Two user input pushbuttons Two user green LED One yellow power LED (can be also software controlled) Debug Interface 20-pin JTAG/ICE interface connector DBGU COM port AT91SAM9RL-EK Evaluation Board User Guide 3-5 6325C–ATARM–22-Jul-10 Board Description 3.13 Expansion Slot One DataFlash, SD/MMC card slot All I/Os of the AT91SAM9RL are routed to peripheral extension connectors (J23, J24, J25, J26). All EBI Signals of the AT91SAM9RL are routed to extension footprint connectors (J27). Refer to the Atmel application note Connecting EBI Memory Daughter Boards to AT91SAM Evaluation Boards, lit. no. 6309. This allows the developer to check the integrity of the components and to extend the features of the board by adding external hardware components or boards. 3-6 6325C–ATARM–22-Jul-10 AT91SAM9RL-EK Evaluation Board User Guide Board Description 3.14 PIO Usage Table 3-1. PIO Controller A I/O Line Peripheral A Peripheral B Application Usage PA0 MC_DA0 SD/MMC CARD READER MC_DA0 VDDIOP PA1 MC_CDA SD/MMC CARD READER MC_CDA VDDIOP PA2 MC_CK SD/MMC CARD READER MC_CK VDDIOP PA3 MC_DA1 TCLK0 SD/MMC CARD READER MC_DA1 VDDIOP PA4 MC_DA2 TIOA0 SD/MMC CARD READER MC_DA2 VDDIOP PA5 MC_DA3 TIOB0 SD/MMC CARD READER MC_DA3 VDDIOP PA6 TXD0 RS232 COM PORT TXD0 VDDIOP PA7 RXD0 RS232 COM PORT RXD0 VDDIOP PA8 SCK0 RF1 USB DEVICE PA8 as USB_CNX VDDIOP PA9 RTS0 RK1 RS232 COM PORT RTS0 VDDIOP PA10 CTS0 RK0 RS232 COM PORT CTS0 VDDIOP PA11 TXD1 VDDIOP PA12 RXD1 VDDIOP PA13 TXD2 TD1 VDDIOP PA14 RXD2 RD1 VDDIOP PA15 TD0 PA16 RD0 PA17 AD0 PA18 AD1 PA19 SD/MMC CARD READER Powered by PA15 as MCI_CD VDDIOP VDDIOP TOUCH SCREEN PANEL AD0_XR VDDIOP RTS1 TOUCH SCREEN PANEL AD1_XL VDDIOP AD2 CTS1 TOUCH SCREEN PANEL AD2_YT VDDIOP PA20 AD3 SCK3 TOUCH SCREEN PANEL AD3_YB VDDIOP PA21 DRXD SERIAL DEBUG PORT DRXD VDDIOP PA22 DTXD SERIAL DEBUG PORT DTXD VDDIOP PA23 TWD0 I2C MEMORY TWD0 VDDIOP PA24 TWCK0 I2C MEMORY TWCK0 VDDIOP PA25 MISO DATAFLASH DEVICE MISO VDDIOP PA26 MOSI DATAFLASH DEVICE MOSI VDDIOP PA27 SPCK DATAFLASH DEVICE SPCK VDDIOP PA28 NPCS0 DATAFLASH DEVICE NPCS0 VDDIOP PA29 RTS2 TF1 VDDIOP PA30 CTS2 TK1 VDDIOP PA31 NWAIT IRQ VDDIOP RF0 AT91SAM9RL-EK Evaluation Board User Guide 3-7 6325C–ATARM–22-Jul-10 Board Description Table 3-2. PIO Controller B I/O Line Peripheral A PB0 TXD3 USER’S PUSH BUTTON 1 PB0 as LEFT CLICK VDDIOP PB1 RXD3 USER’S PUSH BUTTON 2 PB1 as RIGHT CLICK VDDIOP PB2 A21/NANDALE NAND FLASH MEMORY NANDALE VDDIOM PB3 A22/NANDCLE NAND FLASH MEMORY NANDCLE VDDIOM PB4 NANDOE NAND FLASH MEMORY NANDOE VDDIOM PB5 NANDWE NAND FLASH MEMORY NANDWE VDDIOM PB6 NCS3/NANDCS NAND FLASH MEMORY NCS3/NANDCS VDDIOM PB7 NCS4/CFCS0 NPCS1 VDDIOM PB8 CFCE1 PWM0 VDDIOM PB9 CFCE2 PWM1 VDDIOM PB10 A25/CFRNW FIQ VDDIOM PB11 A18 VDDIOM PB12 A19 VDDIOM PB13 A20 VDDIOM PB14 A23 PCK0 VDDIOM PB15 A24 ADTRG VDDIOM PB16 D16 SDRAM MEMORY D16 VDDIOM PB17 D17 SDRAM MEMORY D17 VDDIOM PB18 D18 SDRAM MEMORY D18 VDDIOM PB19 D19 SDRAM MEMORY D19 VDDIOM PB20 D20 SDRAM MEMORY D20 VDDIOM PB21 D21 SDRAM MEMORY D21 VDDIOM PB22 D22 SDRAM MEMORY D22 VDDIOM PB23 D23 SDRAM MEMORY D23 VDDIOM PB24 D24 SDRAM MEMORY D24 VDDIOM PB25 D25 SDRAM MEMORY D25 VDDIOM PB26 D26 SDRAM MEMORY D26 VDDIOM PB27 D27 SDRAM MEMORY D27 VDDIOM PB28 D28 SDRAM MEMORY D28 VDDIOM PB29 D29 SDRAM MEMORY D29 VDDIOM PB30 D30 SDRAM MEMORY D30 VDDIOM PB31 D31 SDRAM MEMORY D31 VDDIOM 3-8 6325C–ATARM–22-Jul-10 Peripheral B Application Usage Powered by AT91SAM9RL-EK Evaluation Board User Guide Board Description Table 3-3. PIO Controller C I/O Line Peripheral A Peripheral B Application Usage Powered by PC0 TF0 PC1 TK0 LCDPWR PC2 LCDMOD PWM0 PC3 LCDCC PWM1 PC4 LCDVSYNC PC5 LCDHSYNC LCD PANEL LCDHSYNC VDDIOP PC6 LCDDOTCK LCD PANEL LCDDOTCK VDDIOP PC7 LCDDEN LCD PANEL LCDDEN VDDIOP PC8 LCDD0 LCDD2 LCD PANEL LCDD2 VDDIOP PC9 LCDD1 LCDD3 LCD PANEL LCDD3 VDDIOP PC10 LCDD2 LCDD4 LCD PANEL LCDD4 VDDIOP PC11 LCDD3 LCDD5 LCD PANEL LCDD5 VDDIOP PC12 LCDD4 LCDD6 LCD PANEL LCDD6 VDDIOP PC13 LCDD5 LCDD7 LCD PANEL LCDD7 VDDIOP PC14 LCDD6 LCDD10 LCD PANEL LCDD10 VDDIOP PC15 LCDD7 LCDD11 LCD PANEL LCDD11 VDDIOP PC16 LCDD8 LCDD12 LCD PANEL LCDD12 VDDIOP PC17 LCDD9 LCDD13 LCD PANEL LCDD13 VDDIOP PC18 LCDD10 LCDD14 LCD PANEL LCDD14 VDDIOP PC19 LCDD11 LCDD15 LCD PANEL LCDD15 VDDIOP PC20 LCDD12 LCDD18 LCD PANEL LCDD18 VDDIOP PC21 LCDD13 LCDD19 LCD PANEL LCDD19 VDDIOP PC22 LCDD14 LCDD20 LCD PANEL LCDD20 VDDIOP PC23 LCDD15 LCDD21 LCD PANEL LCDD21 VDDIOP PC24 LCDD16 LCDD22 LCD PANEL LCDD22 VDDIOP PC25 LCDD17 LCDD23 LCD PANEL LCDD23 VDDIOP PC26 LCDD18 VDDIOP PC27 LCDD19 VDDIOP PC28 LCDD20 VDDIOP PC29 LCDD21 TIOA1 VDDIOP PC30 LCDD22 TIOB1 VDDIOP PC31 LCDD23 TCLK1 VDDIOP VDDIOP LCD PANEL LCDPWR VDDIOP VDDIOP LCD PANEL LCDCC VDDIOP VDDIOP AT91SAM9RL-EK Evaluation Board User Guide 3-9 6325C–ATARM–22-Jul-10 Board Description Table 3-4. PIO Controller D I/O Line Peripheral A PD0 NCS2 PD1 AC97_FS PD2 AC97_CK PD3 Peripheral B Application Usage Powered by VDDIOP AC97 CODEC AC97_FS VDDIOP SCK1 AC97 CODEC AC97_CK VDDIOP AC97_TX CTS3 AC97 CODEC AC97_TX VDDIOP PD4 AC97_RX RTS3 AC97 CODEC AC97_RX VDDIOP PD5 DTXD PWM2 PD6 AD4 VDDIOP PD7 AD5 VDDIOP PD8 NPCS2 PWM3 VDDIOP PD9 SCK2 NPCS3 VDDIOP PD10 TWD1 TIOA2 VDDIOP PD11 TWCK1 TIOB2 VDDIOP PD12 PWM2 PCK1 VDDIOP PD13 NCS5/CFCS1 NPCS3 VDDIOP PD14 DSR0 PWM0 POWER LED PD14 or PWM0 VDDIOP PD15 DTR0 PWM1 USER LED 1 PD15 or PWM1 VDDIOP PD16 DCD0 PWM2 USER LED 2 PD16 or PWM2 VDDIOP PD17 RI0 NAND FLASH MEMORY PD17 as RDYBSY VDDIOP PD18 PWM3 VDDIOP PD19 PCK0 VDDIOP PD20 PCK1 VDDIOP PD21 TCLK2 VDDIOP 3-10 6325C–ATARM–22-Jul-10 VDDIOP AT91SAM9RL-EK Evaluation Board User Guide Section 4 Jumpers 4.1 Jumpers Table 4-1. Jumpers Configuration Designation Default Setting J2 Closed 3.3V Jumper(1) J3 Closed Forces power on. To use the software shutdown control, J3 must be opened. 3V battery backup must be present. J5 Closed VDDPLLB Jumper(1) J6 Closed VDDPLLA Jumper(1) J8 Closed VDDBU Jumper(1) J10 Closed VDDCORE Jumper(1) J11 1-2 J12 Closed Enables the use of the embedded NAND FLASH device (MN7) J13 Closed Enables the use of the embedded SERIAL DATAFLASH device (MN8) Note: 4.2 Feature BMS (Boot Mode Select) 1-2: Internal ROM 2-3: NCS0 1. These jumpers are provided for power consumption measurement use. By default, they are closed. To use this feature, the user has to open the strap and insert an ammeter. JTAG/ICE Table 4-2. JTAG/ICE Configuration Designation Default Setting S1 Opened Selects ICE mode or JTAG mode R11 Soldered Enables the ICE NTRST input R13 Soldered Enables the ICE NRST input AT91SAM9RL-EK Evaluation Board User Guide Feature 4-1 6325C–ATARM–22-Jul-10 Jumpers 4.3 Microcontroller Clock Table 4-3. Microcontroller Clock Configuration 4.4 Designation Default Setting S2 Opened Feature To use an external source clock, the user has to close S2 and populate J7. In this case, C16, C17 and J7 have to be unsoldered. Memory Table 4-4. Memory Configuration Designation Default Setting Feature SDRAM (MN5 & MN6) R29 R30 Soldered Soldered Enables MN5 Chip select access Enables MN6 Chip select access Closed Soldered Opened Enables the use of the NANDFLASH device Enables the use of the Ready/Busy signal Disables the write protect NANDFLASH (MN7) J12 R32 S3 SERIAL DATAFLASH (MN8) J13 S4 Closed Opened Enables the use of the DATAFLASH device Disables the write protect. TWI SERIAL EEPROM NOT POPULATED (MN9) 4.5 Miscellaneous Refer to the TOP level schematic for the PIO usage. Table 4-5. Miscellaneous Designation Default Setting Feature USB HIGH SPEED DEVICE INTERFACE R75 Soldered USB DEVICE: Enables the use of the USBCNX signal Soldered Soldered Enables the use of DTXD output signal Enables the use of DRXD input DBGU COM PORT R64 R66 RS232 COM PORT: Enable the use of Input/output signals 4-2 6325C–ATARM–22-Jul-10 AT91SAM9RL-EK Evaluation Board User Guide Jumpers Table 4-5. Miscellaneous Designation Default Setting R70 R71 R72 R73 Soldered Soldered Soldered Soldered TP1 N.A GND Test point TP2 N.A GND Test point TP3 N.A GND Test point AT91SAM9RL-EK Evaluation Board User Guide Feature TXD RTS RXD CTS 4-3 6325C–ATARM–22-Jul-10 Section 5 Schematics 5.1 Board Schematics This section contains the following schematics: Board Diagram - Schematic Top Level Power supply AT91SAM9RL Microcontroller EBI Memory Serial Memory Audio AC97 Serial Interface TFT LCD display Expansion connectors AT91SAM9RL-EK Evaluation Board User Guide 5-1 6325C–ATARM–22-Jul-10 Section 6 Errata 6.1 Pull-up Resistor on the Wrong Pin The RTCK pin (connector J4, pin 11), which is an input, has a pull-up resistor whereas the TCK pin (connector J4, pin 9), which is an output, has not. Problem Fix/Workaround The user may observe a possible increase in the power consumption on VDDIO (a few micro-amps) but it does not prevent the JTAG-ICE interface to work correctly on this board. Correct schematics would have a pull-up on the TCK pin to tie the CMOS input to a known level, in order to avoid a possible pad oscillation and a possible increase in power consumption. 6.2 VDDCORE Power Consumption Measurement Impossible If the AT91SAM9RL64 device is an engineering sample (ES), VDDCORE power consumption measurement is impossible on J10 Jumper. Problem Fix/Workaround None. AT91SAM9RL-EK Evaluation Board User Guide 6-1 6325C–ATARM–22-Jul-10 Section 7 Revision History 7.1 Revision History Table 7-1. Revision History Document Ref. Comments Change Request Ref. 6325C Section 6.2 ”VDDCORE Power Consumption Measurement Impossible” errata added 7188 CFE1 and CFE2 changed into CFCE1 and CFCE2 in Table 3-2 on page 3-8 5864 Section 6.1 ”Pull-up Resistor on the Wrong Pin” errata added 5983 6325B 6325A First issue. AT91SAM9RL-EK Evaluation Board User Guide 7-1 6325C–ATARM–22-Jul-10 Revision History 7-2 6325C–ATARM–22-Jul-10 AT91SAM9RL-EK Evaluation Board User Guide Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, DataFlash ® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM ®, the ARMPowered ® logo, Thumb® and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. 6325C–ATARM–22-Jul-10