Application Notes

AN11171
BGU7063 evaluation board application note
Rev. 1 — 7 January 2013
Application note
Document information
Info
Content
Keywords
BGU7063, LNA-VGA, IP3i, NF, PCB, Pi(1dB), dynamic range.
Abstract
This application note describes the evaluation board (EVB) design and
typical performance of the BGU7063. The BGU7063 is a fully integrated
analog-controlled variable gain amplifier module. This EVB is supplied
with all necessary connectors in order to enable ease of evaluation.
Ordering info
Board number: OM7937, BGU7063
12NC: 9340 668 53598
Contact information
For more information, please visit: http://www.nxp.com
AN11171
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BGU7063 evaluation board application note
Revision history
Rev
Date
Description
v.1
First publication
20130107
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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1. Introduction
This application note gives a description of the BGU7063 evaluation board.
This enables ease of evaluation; it provides the EVB circuit schematic, the bill of
materials (BOM), PCB material information and artwork. It also provides a list of
equipment for a typical evaluation set up, as well as typical test results of the BGU7063.
This fully supplied EVB can be ordered from the NXP website www.nxp.com
2. Product description
NXP semiconductors’ BGU7063 is a fully integrated analog-controlled variable gain
amplifier module. Its low noise and high linearity performance makes it ideal for sensitive
receivers in cellular base station applications. The BGU7063 is operating in the 1920MHz
to 1980MHz frequency range and has a gain control range of 35 dB. At maximum gain
the noise figure is 0.9 dB. The gain is analog-controlled having maximum gain at 0 V and
minimum gain at 3.3 V. The LNA can be bypassed extending the dynamic range. The
BGU7063 is internally matched to 50 Ohm, meaning no external matching is required,
enabling ease of use. It is housed in a 16 pins 8x8x1.3mm leadless HLQFN16R package
SOT1301. The BGU7063 can operate from 4.75V to 5.25 single supply and consumes
about 230mA in high gain mode (LNA active) and about 190mA in the low gain mode
(LNA bypassed)
BGU7063 is one of a series of LNA-VGA products for the different frequency bands
intended for cellular base stations and its related applications.
Fig 1.
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Pin description.
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3. BGU7063 Evaluation board
The BGU7063 evaluation board, (see Fig 2) is fabricated on a 1mm thick 3 layer PCB
that uses 0.5mm R4003C for the RF performance and 0.5mm Fr4 for the mechanical
strength of the PCB. The board is fully assembled with the BGU7063, including the
external components. The board is supplied with two SMA connectors for input and
output connection to the RF test equipment.
Fig 2.
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Evaluation Board
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3.1 Application circuit
The circuit diagram of the evaluation board is shown in Fig 3
Fig 3.
Circuit diagram of the evaluation board.
Since the BGU7063 is fully integrated the evaluation board only needs two AC coupling
capacitors on the RF input and RF output, as well as bias decoupling circuits on Vcc1
and Vcc2, GS1, GS2, VCTRL(GP).
3.2 Decoupling structure.
Applying the BGU7063 in e.g. wireless base station BST, ask for careful Vcc decoupling
in order to get the optimal and stable performance of the product especially on NF.
If the LNA_VGA module is supplied via supply rail that supplies more components, lack
of decoupling can degrade the performance.
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3.3 PCB Layout information
C17
C11
L1
L2
C16
C10
C15
C14
C13
C12
C9
C8
C7
C6
C1
C2
U1
C3
C5
C4
3
1950
Fig 4.
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BGU7063 evaluation board component placement
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Table 1.
BOM of the BGU7063 evaluation board
Table description (optional)
Designator
Description
Footprint
Value
Supplier Name/type
U1
HLQFN16R
BGU7063
8x8x1.3mm
16 pins
PCB
20x30mm
BGU706x EVB v2.1
June 2012
C1,C2
Capacitor
0402
1nF
Murata GRM1555
AC coupling
C3-C5
Capacitor
0402
100pF
Murata GRM1555
Decoupling
C6,C12
Capacitor
0402
100pF
Murata GRM1555
Decoupling
C11,C17
Capacitor
0402
100nF
Murata GRM1555
Decoupling
C7-C10,
-
-
-
-
Not assembled
L1,L2
Inductor
0402
10nH
Murata LQG15
Decoupling
X1,X2
SMA RF
-
-
Johnson, End launch
SMA 142-0701-841
-
-
Molex, PCB header,
right angle, 1 row 6
way 90121-0766
C13-C16
connector
X3
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DC header
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Fig 5.
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BGU706x Evaluation board Top layer PCB layout
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Fig 6.
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Application note
BGU706x Evaluation board inner layer PCB layout
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Fig 7.
BGU706x Evaluation board bottom layer PCB layout
Fig 8.
BGU706x Evaluation board stack up
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3.4 Recommended footprint
A good PCB layout is an essential part of an RF circuit design. The BGU7063 evaluation
board can serve as a guideline for laying out a board using the BGU7063. Both RF input
and RF output lines are controlled impedance lines. Vcc1 and Vcc2 are decoupled by a
Π filter decoupling. The recommended footprint for reflow soldering can be found in Fig 9
as well as via this link sot1301-1_fr.pdf.
Fig 9.
Recommended footprint specification for the HLQFV16R
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4. Test Setup
4.1 S_Parameter,1dB compression, IIP3, measurement setup
The BGU7063 EVB is fully assembled and tested.
Fig 10 Shows the measurements setup that is used to evaluate the BGU7063 EVB for
S_parameters Gain, IRL ORL Reverse Isolation), 1dB gain compression as well as IIP3.
It is intended as a guide only, substitutions are possible. The 10dB attenuator in the
output path is recommended in order to avoid overdriving the analyzers receiver port
when measuring 1 dB gain compression. Especially in the high gain mode of the
BGU7063, this is needed.
Fig 10. S_parameter, 1dB compression and IP3 measurement setup.
4.2 Noise figure measurement setup
In Fig 11 the noise figure measurement set-up is shown, this is also intended as a guide
only, substitutions can be made. For the High gain mode of the BGU7063 it is
recommended to use a 5dB ENR noise source, for the Low gain a 15 dB ENR noise
source recommended. To achieve to lowest possible setup noise figure an external pre
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amplifier might be necessary, but since this will make the total gain in the highest gain
setting of the BGU7063 to high a 6dB attenuator is needed to avoid overdriving the input
of the spectrum analyzer.
Fig 11. Noise figure test setup
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5. Typical operating performance.
A detailed overview of the performance of the BGU7063 can be found in de Datasheet.
In Table 2 and Table 3 the typical performance at 1950MHz in High- and Low-gain is
given.
Table 2.
Typical performance high gain mode
GS1=LOW; GS2=HIGH; Vcc1=5V; Vcc2=5V; f=1950MHz; Tamb=25°C; input and output 50Ω; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
mA
ICC(tot)
total supply current
200
230
265
Gp(min)
minimum power gain
Vctrl(Gp) = 3.3 V
12.5
dB
Gp(max)
maximum power gain
Vctrl(Gp) = 0 V
37.5
dB
Gp(flat)
power gain flatness
1920 MHz≤ f ≤1980 MHz
0.2
dB
Vctrl(Gp) = 0 V(maximum power gain)
0.9
dB
Gp = 35 dB
1.05
dB
Gp = 18 dB
6.40
dB
Gp = 35 dB
0.9
dBm
Gp = 30 dB
3.4
dBm
Gp = 29 dB
3.8
dBm
Gp = 18 dB
5.4
dBm
input power at 1 dB gain compression Gp = 35 dB
0.9
dBm
Gp = 30 dB
3.4
dBm
Gp = 29 dB
3.8
dBm
Gp = 18 dB
5.4
dBm
Vctrl(Gp) = 0 V(maximum power gain)
35
dB
Gp = 35 dB
31
dB
15
dB
18 dB≤ Gp≤ 35 dB
NF
IP3I
Pi(1dB)
RLin
noise figure
input third-order intercept point
input return loss
2-tone; tone-spacing = 1.0 MHz
RLout
output return loss
Vctrl(Gp) = 0 V (maximum power gain)
K
Rollett stability factor
0 GHz≤ f ≤ 12.75 GHz
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Table 3.
Typical performance low gain mode
GS1=HIGH; GS2=LOW; Vcc1=5V; Vcc2=5V; f=1950MHz; Tamb=25°C; input and output 50Ω; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
mA
ICC(tot)
total supply current
165
190
215
Gp(min)
minimum power gain
Vctrl(Gp) = 3.3 V
-6.6
dB
Gp(max)
maximum power gain
Vctrl(Gp) = 0 V
18.6
dB
Gp(flat)
power gain flatness
1920 MHz≤ f ≤1980 MHz
0.2
dB
3 dB≤ Gp≤ 17 dB
NF
IP3I
Pi(1dB)
RLin
noise figure
Vctrl(Gp) = 0 V(maximum power gain)
input third-order intercept point
dB
Gp = 17 dB
11.3
dB
Gp = 3 dB
22.0
dB
Gp = 17 dB
20
dBm
Gp = 12 dB
24
dBm
Gp = 11 dB
25
dBm
Gp = 3 dB
28
dBm
6.0
dBm
Gp = 12 dB
10.0
dBm
Gp = 11 dB
10.5
dBm
Gp = 3 dB
10.5
dBm
Vctrl(Gp) = 0 V(maximum power gain)
30
dB
Gp = 17 dB
25
dB
18
dB
2-tone; tone-spacing = 1.0 MHz
input power at 1 dB gain compression Gp = 17 dB
input return loss
RLout
output return loss
Vctrl(Gp) = 0 V (maximum power gain)
K
Rollett stability factor
0 GHz≤ f ≤ 12.75 GHz
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6. Legal information
6.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
6.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s
own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express,
implied or statutory, including but not limited to the implied warranties of noninfringement, merchantability and fitness for a particular purpose. The entire
risk as to the quality, or arising out of the use or performance, of this product
remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be
liable to customer for any special, indirect, consequential, punitive or
incidental damages (including without limitation damages for loss of
business, business interruption, loss of use, loss of data or information, and
the like) arising out the use of or inability to use the product, whether or not
based on tort (including negligence), strict liability, breach of contract, breach
of warranty or any other theory, even if advised of the possibility of such
damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by
customer for the product or five dollars (US$5.00). The foregoing limitations,
exclusions and disclaimers shall apply to the maximum extent permitted by
applicable law, even if any remedy fails of its essential purpose.
6.3 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are property of their respective owners.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP
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7. List of figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Pin description. ................................................. 3
Evaluation Board............................................... 4
Circuit diagram of the evaluation board. ........... 5
BGU7063 evaluation board component
placement ......................................................... 6
BGU706x Evaluation board Top layer PCB
layout ................................................................ 8
BGU706x Evaluation board inner layer PCB
layout ................................................................ 9
BGU706x Evaluation board bottom layer PCB
layout .............................................................. 10
BGU706x Evaluation board stack up .............. 10
Recommended footprint specification for the
HLQFV16R ..................................................... 11
S_parameter, 1dB compression and IP3
measurement setup. ....................................... 12
Noise figure test setup .................................... 13
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8. List of tables
Table 1.
Table 2.
Table 3.
BOM of the BGU7063 evaluation board ............ 7
Typical performance high gain mode .............. 14
Typical performance low gain mode ............... 15
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9. Contents
1.
2.
3.
3.1
3.2
3.3
3.4
4.
4.1
4.2
5.
6.
6.1
6.2
6.3
7.
8.
9.
Introduction ......................................................... 3
Product description ............................................ 3
BGU7063 Evaluation board ................................ 4
Application circuit ............................................... 5
Decoupling structure. ......................................... 5
PCB Layout information ..................................... 6
Recommended footprint ................................... 11
Test Setup .......................................................... 12
S_Parameter,1dB compression, IIP3,
measurement setup ......................................... 12
Noise figure measurement setup ..................... 12
Typical operating performance. ....................... 14
Legal information .............................................. 16
Definitions ........................................................ 16
Disclaimers....................................................... 16
Trademarks ...................................................... 16
List of figures..................................................... 17
List of tables ...................................................... 18
Contents ............................................................. 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2013.
All rights reserved.
For more information, visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 January 2013
Document identifier: AN11171