LatticeECP2M™ SERDES Evaluation Board
User’s Guide
May 2010
Revision: EB25_01.7
LatticeECP2M SERDES
Evaluation Board User’s Guide
Lattice Semiconductor
Introduction
This user’s guide describes the LatticeECP2M™ SERDES Evaluation Board featuring the LatticeECP2M FPGA.
This stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces. The board also includes a PCI Express x1 edge for future expansion. Please note the PCI Express x1 edge is only connected if the board is populated with the LatticeECP2M-50
or larger FPGA.
The evaluation board includes provisioning to connect four high-speed SERDES channels via SMA connectors to
test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias.
The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.
The board has several debugging and analyzing features for complete customer evaluations of the LatticeECP2M
FPGA. The intended use of this guide is to be referenced in conjunction with evaluation design tutorials to demonstrate the LatticeECP2M FPGA.
Figure 1. LatticeECP2M SERDES Evaluation Board
Board Features
• LatticeECP2M FPGA in 672-ffBGA package. Default device is LFE2M35E-6FF672C.
• Four SERDES high-speed channels interfaced to SMA test points and clock connections SERDES interface to
x1 PCI Express edge fingers (PCI Express x1 edge available with LatticeECP2M-50 or larger FPGA only)
• DDR2 memory device
• SFP Transceiver cage and associated interface (available with LatticeECP2M-50 or larger FPGA only)
• SATA-like connections to SERDES channels (available with LatticeECP2M-50 or larger FPGA only)
• Power connections and power sources
• ispVM® programming support
• On-board and external reference clock sources
– Interchangeable clock oscillators
– On-board reference clock management using Lattice ispClock™ devices
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• ORCAstra Demonstration Software interface via standard ispVM JTAG connection
• Various high-speed layout structures
• User-defined input and output points
• SMA connectors included (10) for high-speed clock or data interfacing
• Performance monitoring via test headers, LEDs and switches
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board. Figure 2 shows the functional partitioning of the board.
Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development.
However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end
application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout
in the user's application may significantly affect circuit performance and reliability.
Figure 2. LatticeECP2M SERDES Evaluation Board Block Diagram
16 SMAs/
4 SERDES
Channels
(SRIO x1, x4),
XAUI
LatticeECP2M-50 Only
1 SERDES
Channel
SFP Cage
2 SERDES
Channels
SATA Interface
ispVM/JTAG
PCI Express x1
Edge Fingers
(LatticeECP2M-50 Only)
Clock Management
ispClock
LatticeECP2M
672 fpBGA
8 LVDS Paired SMAs
for Demo of LVDS
I/O Performance
FPGA Loader
SMA Clock
Inputs/Oscillator
SPI Flash Devices
General Purpose
I/O: Switches
& LEDs
DDR2 Memory
Component
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Figure 3. LatticeECP2M SERDES Evaluation Board, Top View
LatticeECP2M Device
This board features a LatticeECP2M FPGA with a 1.2V core supply. It can accommodate all pin compatible
LatticeECP2M devices in the 672-ball fpBGA (1mm pitch) package. A complete description of this device can be
found in the LatticeECP2/M Family Data Sheet.
Note: The connections referenced in this document refer to the LFE2M35E-FF672 device. Available I/Os and associated sysIO™ banks may differ for other densities within this device family. However, only the LFE2M50E-FF672
device allows full use of the PCI Express x1 edge, SFP and SATA interfaces.
Applying Power to the Board
The LatticeECP2M SERDES Evaluation Board is ready to power on. The board can be supplied with power from
an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a bench-top supply
via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host
board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord
to J1 and plug the wall transformer into an AC wall outlet.
Power Supplies
(see Appendix A, Figure 2)
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to
accept a main supply via the TB1 connection. This connection is provided to use with a bench-top supply adjusted
to provide a nominal 12V DC.
All input power sources and on-board power supplies use surface mounted fuses and have green LEDs to indicate
power GOOD status of the intermediate supplies
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Table 1. Board Power Supply Fuses (see Appendix A, Figure 4)
F1
1.2V Core Fuse
F2
1.5V Fuse
F3
3.3V Fuse
F4
1.2V Fuse
F5
2.5V Fuse
F6
1.8V Fuse
Table 2. Board Power Supply Indicators (see Appendix A, Figure 4)
D1
2.5V Source Good Indicator
D2
3.3V Source Good Indicator
D3
12V Input Good Indicator
D4
1.2V VCC Core Source Good Indicator
D5
1.5V Source Good Indicator
D6
1.8V Source Good Indicator
D7
1.2V Source Good Indicator
External power can be supplied via the screw-terminals (TB1) as an alternative.
Table 3. Board Supply Disconnects (see Appendix A, Figure 3)
TB1
Screw terminal for 12 VDC
Pin1(square PCB pad) -> +12V DC
Pin2 -> Ground
PCI Express Power Interface
Power can be sourced to the board via the PCB edge-finger (CN1). This interface allows the user to provide power
from a PCI Express Host board.
Programming/FPGA Configuration
(see Appendix A, Figure 4)
A programming header is provided on the evaluation board, providing access to the LatticeECP2M JTAG port.
Note: An ispDOWNLOAD® Cable is included with each ispLEVER design tool shipment. Cables may also be purchased separately from Lattice.
ispVM Download Interface
J8 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control
the device.
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Table 4. ispVM JTAG Connector (see Appendix A, Figure 2)
Pin 1
VCC
Pin 2
TDO
Pin 3
TDI
Pin 4
PROGRAMN
Pin 5
NC
Pin 6
TMS
Pin 7
GND
Pin 8
TCK
Pin 9
DONE
Pin 10
INITN
Programming Daisy Chain
This board includes two Lattice Semiconductor programmable devices that can be programmed in a daisy chain. A
jumper setting of J105 controls the chain. Both devices are in the programming chain from the JTAG header J8 with
jumpers on J105 across pins {1-2}, pins{3-4} and pins{5-6}. Also a jumper on J10 across pins{1-2} and pins{3-4}
are also required for both devices to be in the chain.
If the user desires only to program U1, J105 requires jumpers across pins{1-2} and pins{3-5}. J10 requires only a
jumper across pins{1-2}.
Download Procedures
Requirements
• PC with ispVM System v.16.0 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable).
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (HW-DLN-3C, HW-USBN-2A, etc.)
JTAG Download
The LatticeECP2M device can be configured easily via its JTAG port. The device is SRAM-based; it must remain
powered on to retain its configuration when programmed in this fashion.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the LatticeECP2M FPGA device and render the
board inoperable.
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1. Press the SCAN button located in the toolbar. The LatticeECP2M device will automatically be detected.
2. Double-click the device to open the device information dialog. In the device information dialog, click the
Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes.
3. Click the green GO button. This will begin the download process into the device. Upon successful download,
the device will be operational.
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Configuration Status Indicators
(see Appendix A, Figure 4)
These LEDs indicate the status of configuration to the FPGA.
• D8 (red) illuminated – Indicates that programming was aborted or reinitialized, driving the INITN output low.
• D11 (green) illuminated – Indicates the successful completion of configuration by releasing the open collector
DONE output pin.
• D12 (green) flashing – Indicates TDI activity.
• D10 (red) illuminated – Indicates that PROGRAMN is low.
• D9 (red) illuminated – Indicates that GSRN is low.
PROGRAMN and GSRN
(see Appendix A, Figure 4)
These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW2).
Depressing the button drives a logic level “0” to the device.
CFG [2:0]
(see Appendix A, Figure 4)
The FPGA CFG pins are set on the board for a particular programming mode via the SW1 DIP switch. JTAG programming is independent of the MODE pins and is always available to the user.
On-Board Flash Memory
(see Appendix A, Figure 4)
Two memory devices (U10 and U12) are on-board for non-volatile configuration memory storage.
These two devices occupy the same Flash slot on the board. U10 can be populated with an 8M or smaller 8-pin
SOIC device. U12 can be used in place of U10 with a 16-pin TSSOP 64M Flash device.
U15 is supplied as an 8M Flash device.
J11 is used to control the selection of the Flash memory to be accessed.
FPGA Clock Management
(see Appendix A, Figure 8)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are generated from input provided via SMAs (see Table 5) or from crystal oscillators (Y1 and Y2). Y1 is socketed for interchangeability and Y2 is a 100MHz surface-mounted oscillator which is fanned-out around U1 for reference clocks
with a fan-out buffer IC.
A 4-pin DIP type oscillator such as the Connor-Winfield XO-400 series can be used in socket Y1.
Both of these input clock sources are routed through the Lattice ispClock5620A programmable clock manager
devices (U2). These clock management devices allow for clock synthesis and buffering.
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Table 5. SMA Clock Input
SMA
Signal
J35
U2 Reference + Input
J36
U2 Reference - Input
U2 is an ispClock5620A clock generator that allows designers to implement clock distribution networks supporting
multiple, synchronized output frequencies using a single device. By integrating a Phase-Locked Loop (PLL) along
with multiple output dividers, the ispClock5620A can derive up to five separate output frequencies from a single
input reference frequency. PAC-Designer® software (available for download from the Lattice web site at www.latticesemi.com/pac-designer) is used to program the ispClock features.
ispClock supports reference clocks in the range of 10 to 320 MHz. The duty cycle of the clock source does not
need to be 50%; the only requirement is that both the HIGH and LOW times of this signal must be 1.25ns or longer.
The following standards are supported with either minimal or no external components: LVTTL, LVCMOS, SSTL2,
SSTL3, HSTL, LVDS and LVPECL.
When the ispClock5620A is in a LOCKED state, the LOCK output pin goes LOW. The LOCKN pins are connected
to amber LED D13 and will illuminate when the LOCKN pin goes low. The lock detector has two operating modes;
phase-lock mode and frequency lock mode. In phase-lock mode, the LOCK signal is asserted if the phases of the
reference and feedback signals match. In frequency-lock mode the LOCK signal is asserted when the frequencies
of the feedback and reference signals match.
U2 is controlled by SW4 or from a predefined connection to U1 (LatticeECP2M). The DIP switch controls the ispClock device. The reference clock selection and device reset is controlled using the switches. The switches that
control the ispClock outputs can be synchronously controlled by the SGATE output on a bank-by-bank basis or tristated on an output-by-output basis using the OEXb and OEYb inputs. All outputs may be tri-stated by bringing the
GOEb input high.
The VCCO voltage is board-connected to 2.5V or 3.3V based on the on-board connection of FB21 or FB22.
The output clocks of U2 are routed to devices to provide system level clocking. These pre-defined board clocks are
routed to input LatticeECP2M input clock pins for SERDES reference clocks, primary clocks, PLL inputs and DLL
inputs as well as connection to a SMA (J34). This SMA is 50-ohm terminated for off-board interconnection to test
equipment.
A clock input to the ispClock device can be provided from the PCI Express edge-fingers. This is accomplished by
configuring the on-board resistor jumpers R79 and R80 (see Appendix A, Figure 5).
The board has various component stuffing options to provision specific clock source variations. Table 6 outlines the
need to open or short connections on the board as well as required terminations for proper signal quality.
Table 6. Clock Source Connection Variations
Clock Source
Default
R67
R68
R69
R70
R100
R101
R215
short
short
50-ohm
50-ohm
short
short
100-ohm
open
Y1 or Y2 Clock Source
open
open
open
open
short
short
J14/J15 CML or LVDS source
short
short
50-ohm
50-ohm
open
open
open
Core Ref Clock
open
open
don’t care
don’t care
don’t care
don’t care
don’t care
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SERDES
(see Appendix A, Figure 5)
SERDES Reference Clock
The 50-ohm terminated SMA connectors provide supply reference clocks directly to the LatticeECP2M device from
the ispClock management device. This device drives clocks to both SERDES quads via 100-ohm LVDS signaling.
The on-board clock oscillators mentioned in previous sections of this document can be chosen to drive the same
SERDES reference clocks. In addition, the board can be provisioned to source the clock from the PCI Express
edge-fingers directly to the SERDES REFCLK pins.
SERDES Channels
Surface Mounted SMA Connections
(see Appendix A, Figure 5)
DC coupled top-mounted SMA connectors connect to the four SERDES Tx and Rx channels. These pins are
directly coupled to the designated SMA connector, creating a path for both input and output differential data.
Table 7. SERDES Connectors (see Appendix A, Figure 5)
SMA
Channel Name
SMA
Channel Name
J18
U_HDINP0
J19
U_HDOUTP0
J21
U_HDINN0
J22
U_HDOUTN0
J24
U_HDINP1
J25
U_HDOUTP1
J26
U_HDINN1
J27
U_HDOUTN1
J29
U_HDINN2
J30
U_HDOUTP2
J32
U_HDINP2
J33
U_HDOUTN2
J20
U_HDINP3
J28
U_HDOUTP3
J23
U_HDINN3
J31
U_HDOUTN3
SERDES SFP Transceiver Interface
(see Appendix A, Figure 5)
A small form-factor pluggable (SFP) transceiver cage is included for evaluation of SFP specific protocols. The PCB
includes the appropriate power and high-speed circuitry needed for the SFP standard transceiver. Note: this interface is only available on boards featuring a LatticeECP2M-50 or larger FPGA.
Table 8. SFP Connections to SERDES Pins (see Appendix A, Figure 5)
SFP Rx
Channel Name
SFP Tx
Channel Name
RD+
L_HDINP3
TD+
L_HDOUTP3
RD-
L_HDINN3
TD-
L_HDOUTN3
Table 9. SFP Control and Status Connections to FPGA
SFP Pin
FPGA BGA
SFP Pin
FPGA BGA
TxFault
M3
ModeDef0
N1
TxDis
L8
ModeDef1
M1
LOS
N2
ModeDef3
M6
RateSel
N3
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SERDES SATA Channels
(see Appendix A, Figure 5)
Connections are included to attach SATA type cables to SERDES channels for board-to-board or loopback purposes. The connectors are configured using the 7-pin SATA specifications. Note: this interface is only available on
boards featuring a LatticeECP2M-50 or larger FPGA.
Table 10. SERDES to SATA Connector
CN1 Pin
FPGA BGA
CN2 Pin
FPGA BGA
TxFault
M3
ModeDef0
N1
TxDis
L8
ModeDef1
M1
LOS
N2
ModeDef3
M6
RateSel
N3
SERDES PCI Express Channels
(see Appendix A, Figure 5)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edgefingers (CN1) to fit directly into an x1 host receptacle. Power can be supplied directly from the PCI Express host via
the edge-finger connections. Note: this interface is only available on boards featuring a LatticeECP2M-50 or larger
FPGA.
FPGA Test Pins
(see Appendix A, Figure 10)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS
designated according to the following table.
Table 11. FPGA Test Pins (see Appendix A, Figure 7)
Switch
BGA
Netname
LED
BGA
NetName
SW6D
T3
Switch1
D16
U3
RED1
SW6C
T4
Switch2
D17
U4
YELLOW1
SW6B
P8
Switch3
D19
U5
GREEN1
SW6A
R6
Switch4
D21
U6
BLUE1
SW5D
T1
Switch5
D15
U2
RED2
SW5C
U1
Switch6
D18
V1
YELLOW2
SW5B
R7
Switch7
D20
W2
GREEN2
SW5A
T5
Switch8
D22
V2
BLUE2
Note: LEDs will illuminate if connected to an un-programmed FPGA pin. It is recommended that a pull-down be
programmed on FPGA output pins.
17-Segment LED Display
(see Appendix A, Figure 10)
General-purpose FPGA pins are connected to a 17-segment display according to the following table. These pins
can be driven low to illuminate the display segments.
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Figure 4. 17-Segment LED Display
Segment
BGA
A
H2
B
J3
C
G1
D
H3
E
J7
F
H5
G
G5
H
G6
K
F3
M
J8
N
E1
P
J9
R
E3
S
F5
T
D3
U
F6
DP
C2
A
H
B
K M N
U
G
P
T S
F
C
R
E
D
DP
Test SMA Connections
General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit
evaluations of several types of FPGA I/O buffers. The use of several termination schemes permits easy interfaces
for the type of buffer.
Table 12. FPGA I/O Test SMA Connectors (see Appendix A, Figure 9)
SMA
Designation
Name
LFE2M35E
Signal
672-BGA
J37
LVDS_INP0
PR37A
N23
LVDS_INN0
PR37B
M21
LVDS_INP1
PR41A
P24
LVDS_INN1
PR41B
P23
J45
LVDS_INP2
PR51A
T24
J47
LVDS_INN2
PR51B
U24
J49*
LVDS_INP3
PR57A
V24
J51*
LVDS_INN3
PR57B
W24
J38
LVDS_OUTP0
PR50A
T23
J40
LVDS_OUTN0
PR50B
T22
J42
LVDS_OUTP1
PR53A
V26
J44
LVDS_OUTN1
PR53B
V25
J46
LVDS_OUTP2
PR55A
W26
J48
LVDS_OUTN2
PR55B
W25
J50
LVDS_OUTP3
PR59A
Y26
J52
LVDS_OUTN3
PR59A
AA26
J39
12
Termination
Description
Termination
Resistor(s)
100-ohm Differential
R130
100-ohm Differential
R132
100-ohm Differential
R134
100-ohm Differential
R136
100-ohm Differential
R131
100-ohm Differential
R133
100-ohm Differential
R135
100-ohm Differential
R137
LatticeECP2M SERDES
Evaluation Board User’s Guide
Lattice Semiconductor
Test Pad Array
A 5 x 12 array of test pads are provided for the user to utilize for test points. This array provides 48 general I/O contacts and 12 ground points.
Table 13. Test Pad Array BGA Reference
Test Points Array on Component Side
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AA20
V17
W20
AC25
AC23
AD26
AB21
AC22
AD12
AF12
W14
AB13
AA13
AE9
AF9
AB6
E23
E24
P26
P25
U21
U19
V21
J2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K7
J6
K5
L5
P5
N6
P4
R3
W5
Y4
U8
W6
G7
G8
E6
D5
G12
C8
E13
H17
E14
G17
D17
E17
High Speed Test Point
DP1
(see Appendix A, Figure 9)
General-purpose FPGA pins are available to a differential test pad. These connections allow a high-impedance
probe to measure the performance of a coupled- differential output buffer pair.
DDR2 Memory
U18
(see Appendix A, Figure 10)
The LatticeECP2M SERDES Evaluation Board is equipped with an 84-ball BGA DDR2 SDRAM memory device
such as the Micron MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The
evaluation board includes termination of address and command signals. It includes all power and external components needed to demonstrate the memory controller of the LatticeECP2M device.
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Ordering Information
Description
Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
LatticeECP2M35 SERDES Evaluation Board
(Non-RoHS, Obsolete)
LFE2M35E-S-EV
10
LatticeECP2M50 SERDES Evaluation Board
(Non-RoHS, Obsolete)
LFE2M50E-S-EV
10
LatticeECP2M50 SERDES Evaluation Board
(RoHS Compliant)
LFE2M50E-S-EVN
Known Issues
The current silkscreen markings by J28 and J31 are incorrectly labeled. They should be labeled 3G OUT CH3.
SATA Host interface (CN1) – Receive data must be polarity-inverted in FPGA design for correct connection.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
December 2006
01.0
Initial release.
Change Summary
December 2006
01.1
Includes new SERDES schematic in Appendix A.
March 2007
01.2
Added Ordering Information section.
April 2007
01.3
Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
May 2007
01.4
Updated SW6D switch information in FPGA Test Pins table.
February 2008
01.5
Updated FPGA Clock Management text section and added Clock
Source Connection Variations table.
Updated SERDES Connectors table.
Added Known Issues section.
Updated SERDES schematic in Appendix A.
January 2009
01.6
Updated ordering information.
May 2010
01.7
Updated Known Issues section.
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
14
15
A
B
C
D
5
4
4
SFP Transceiver Cage
LVDS Test SMAs
ECP2M-672fpBGA
Option 2
PCI Express Platform
Evaluation Board
5
ispCLK
5620AV
2
3
2
Board will meet PCI Express Electromechanical
Specification Rev 1.0
Add-in card form factor for standard height and full length
4.376" Height x 9.5" Length
X1 PCIE Fingers
ECP2M
672BGA
SMA Test Connections
4 SERDES Channels
3
Title
D a te :
S iz e
C
1
S he e t
ECP2M PCI EXPRESS Card
P roje c t
Cover Page
1
of
16-Segment Display
1
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Appendix A. Schematic
Figure 5. Cover Page
A
B
C
D
TESTPOINT
1
1
1
1
1
1
R14
0R-0805SMT
TP11
TP9
TP7
R30
0R-0805SMT
C16
10UF-16V_TANTBSMT
3_3VIN
TP3
TP5
C3
10UF-16V_TANTBSMT
3_3VIN
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
5
1
TP12
1
TP10
1
TP8
1
TP6
1
TP4
1
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
C17
2
4
5
100NF-0603SMT
TP2
100NF-0603SMT
R17
R33
1
3
124R-0603SMT
C18
22UF-16V_TANTBSMT
BOURNS-3224W-5K
R39
AMS1503CT
OUTPUT
VCONTROL
SENSE
ADJUST_GND
1_8V
1.5V
C19
4
C11
4
R9
1
10K-0603SMT
Q3
2N2222/SOT23
R31
OPEN-0805SMT
1
2
1
2
U5
U6
12_0V
12_0V
GND
VIN
GND
VIN
R10
1
10K-0603SMT
LED-SMT1206_GREEN
D6
1_8V
1. 8V
R4
470R-1206SMT
12_0V
PTH12060W
SENSE
PTH12060W
BOURNS-3224W-10K
R34
R15
0R-0603SMT
R25
5
6
0R-0603SMT
R28
R26
100K-0603SMT
1_8K-0603SMT
R35
15_4K-0603SMT
C14
10UF-16V_TANTBSMT
SENSE
VOUT
BOURNS-3224W-10K
R21
6
5
R12
100K-0603SMT
R11
1
10K-0603SMT
3
1_2V
LED-SMT1206_GREEN
D7
C4
10UF-16V_TANTBSMT
VOUT
Q4
2N2222/SOT23
1.2V
R5
470R-1206SMT
12_0V
3
1.2V
330UF-FKSMT
C5
+
3_3V
330UF-FKSMT
3.3V
C6
10UF-16V_TANTBSMT
R32
OPEN-0805SMT
R7
150R-0603SMT
3.3V
D2
LED-SMT1206_GREEN
3_3V
F3
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
F4
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
C15
+
1_2V
G
3_3VIN
R6
100R-0603SMT
2. 5V
D1
LED-SMT1206_GREEN
2_5V
G
POWER RAIL GOOD INDICATORS
R18
OPEN-0805SMT
LED-SMT1206_GREEN
D5
1_5V
1.5V
R3
470R-1206SMT
12_0V
Q2
2N2222/SOT23
1.8V
1_5V
VCC_CORE
C10
22UF-16V_TANTBSMT
5A Fast-Blo SMT Socketed Fuse
VPOWER
U8
3
1
124R-0603SMT
BOURNS-3224W-2K
R24
AMS1503CT
OUTPUT
VCONTROL
SENSE
ADJUST_GND
VPOWER
U4
R8
1
10K-0603SMT
LED-SMT1206_GREEN
D4
V C C _C O R E
F2
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
F6
F1228CT-ND
C9
2
4
5
Q1
2N2222/SOT23
470R-1206SMT
R2
G
3
2
TP1
27R-0603SMT
G
3
2
G
3
GND Pads
Distributed around the board
R36
INHIBIT#
R20
56R-0603SMT
INHIBIT#
2
G
3
2
12_0V
100NF-0603SMT
8
3
1
2
U7
12_0V
C1
2
GND
VIN
OPEN-0805SMT
R19
3_3VIN
LED-SMT1206_GREEN
D3
R1
12_0V
PTH12060W
1
2
U3
C2
2
1
GND
+12VDC
12_0V
PTH03010W
VOUT
BOURNS-3224W-10K
R22
VOUT
R29
0R-0603SMT
R38
2_2K-0603SMT
4.32K Typical
C12
10UF-16V_TANTBSMT
5
6
R27
100K-0603SMT
5
6
0R-0603SMT
R16
R13
100K-0603SMT
Title
D a te :
S iz e
C
2.5V
1
R23
15K-0603SMT
12_0V
1
S he e t
ECP2M PCI EXPRESS Card
P roje c t
J1
1
330UF-FKSMT
C7
+
DC/DC Conversion
330UF-FKSMT
C13
+
2_5V
C8
10UF-16V_TANTBSMT
SENSE
VCC_CORE
F1
F1251CT-ND
10A Fast-Blo SMT Socketed Fuse
FPGA
VCC_CORE
100UF-FKSMT
+
Male Power Jack 2.1mm
22HP037
3
POWER INPUT
Terminal Block/ED1202DS
TB1
F5
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
GND
VIN
SENSE
BOURNS-3224W-10K
R37
12_0V
470UF-FKSMT
+
12_0V
470R-1206SMT
12VIN GOOD
2
2
5
100NF-0603SMT
10
MUP
9
MDWN
3
10
MUP
9
MDWN
ADJUST
INHIBIT#
3
TRACK
ADJUST
3_3_TRIM
4
8
TRACK
GND
4
10
MUP
INHIBIT#
ADJUST
4
G
3
GND
7
9
MDWN
10
MUP
9
MDWN
8
TRACK
GND
7
CORE_TRIM
7
1_2_TRIM
8
TRACK
ADJUST
4
2_5_TRIM
GND
16
7
2
of
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 6. DC/DC Conversion
A
B
C
D
C35
C36
C37
C46
5.6nF
0402
C121
T8
1
1
LLM0_PLLCAP
JUMPER1
C122
JUMPER1
J101
C71
C72
C73
C74
VCC_PLL
G19
J17
H7
K6
R8
P7
V18
P20
J99
HEADER 3
VCC Core
U1I
1_5V
J98
HEADER 3
C123
C124
ecp2m-672fpbga
2
2
1_5V
1_2V
C125
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
1_2V
L12
L13
L14
L15
M11
M12
M15
M16
N11
N16
P11
P16
R11
R12
R15
R16
T12
T13
T14
T15
C126
PP6
VCC_CORE
+ C419
+ C417
22UF-16V_TANTBSMT
C127
C420
VDDOB
C418
VDDIB
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C70
ecp2m-672fpbga
PLL
RLM0_PLLCAP
J100
V19
RUM0_VCCPLL
RUM1_VCCPLL
LUM0_VCCPLL
LUM1_VCCPLL
LLM0_VCCPLL
LLM2_VCCPLL
RLM0_VCCPLL
RLM2_VCCPLL
+ C38
C128
C20
1UF-16V-0805SMT
C129
PP1
C83
C133
C134
C135
C136
C137
C138
C139
C140
C141
5
4
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C132
VCC_CORE
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C120
VCC_CORE
C47
5.6nF
0402
U1G
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C28
VCC_PLL
1
2
100NF-0603SMT
100NF-0603SMT
C114
VDDRX
100NF-0603SMT
C106
VDDTX
100NF-0603SMT
C98
VDDP
C439
C21
C22
C23
C40
C24
C25
C26
C27
C31
C42
C32
C43
C33
C44
C34
C45
C49
C50
C51
C52
C53
C54
C55
C56
C60
C64
C65
C66
C67
C68
C61
C69
10NF-0603SMT
C115
10NF-0603SMT
C107
10NF-0603SMT
C99
+ C87
100NF-0603SMT
C116
100NF-0603SMT
C108
100NF-0603SMT
C100
C88
C101
10NF-0603SMT
C117
10NF-0603SMT
C109
10NF-0603SMT
C94
AE25
AD23
AD15
AE13
B25
C23
C15
B13
A22
C20
C18
A16
AF16
AD20
AD18
AF22
AE19
B19
C92
C96
ecp2m-672fpbga
C102
3
100NF-0603SMT
C118
100NF-0603SMT
C110
100NF-0603SMT
C103
10NF-0603SMT
C119
10NF-0603SMT
C111
10NF-0603SMT
1_2V
SERDES Supplies
L_VCCIB0
L_VCCIB1
L_VCCIB2
L_VCCIB3
U_VCCIB0
U_VCCIB1
U_VCCIB2
U_VCCIB3
U_VCCOB0
U_VCCOB1
U_VCCOB2
U_VCCOB3
L_VCCOB3
L_VCCOB1
L_VCCOB2
L_VCCOB0
L_VCCAUX33
U_VCCAUX33
U1H
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C90
VDDIB
VDDOB
VDDIB
VDDIB
FB1
BLM41PG600SN1
FB3
BLM41PG600SN1
FB2
BLM41PG600SN1
+ C130
VDDRX
+ C112
VDDTX
+ C104
VDDP
VDDP
VDDTX
VDDRX
C113
C131
C105
10NF-0603SMT
C95
AD25
AD24
AD13
AD14
C25
C24
C14
C13
AD16
AD17
AD21
AD22
C22
C21
C17
C16
C19
AD19
100NF-0603SMT
C91
VDDOB
L_VCCRX0
L_VCCRX1
L_VCCRX3
L_VCCRX2
U_VCCRX0
U_VCCRX1
U_VCCRX2
U_VCCRX3
L_VCCTX3
L_VCCTX2
L_VCCTX1
L_VCCTX0
U_VCCTX0
U_VCCTX1
U_VCCTX2
U_VCCTX3
U_VCCP
L_VCCP
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C63
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C48
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C41
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C39
3_3V
1_8V
2_5V
3
2
100NF-0603SMT
C93
+ C57
1_8V
+ C29
2_5V
2
22UF-16V_TANTBSMT
1UF-16V-0805SMT
PP8
PP7
PP5
PP2
PP3
C76
U1J
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
C78
ecp2m-672fpbga
C77
B7
B12
F11
J13
K12
D18
F16
J14
K15
G25
L21
M17
M25
N18
P18
R17
R25
T21
Y25
AC18
AA16
U15
V14
AA11
AE7
U12
V13
AE12
P9
R10
R2
T6
Y2
G2
L6
M10
M2
N9
D a te :
S iz e
C
Title
VCCIO8
VCCIO8
VCCJ
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
3_3V
C62
3_3V
1
1UF-16V-0805SMT
10NF-0603SMT
C81
22UF-16V_TANTBSMT
S he e t
ECP2M PCI EXPRESS Card
P roje c t
+ C59
1
10NF-0603SMT
C80
U17
AC24
AA7
J11
J12
J15
J16
L18
L9
M18
M9
R18
R9
T18
T9
V11
V12
V15
V16
Power Supplies
10NF-0603SMT
C79
Power
Supplies
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C75
10NF-0603SMT
C97
C58
C30
1
2
FB8
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
1
2
3
1
2
3
1UF-16V-0805SMT
1UF-16V-0805SMT
BLM41PG600SN1
22UF-16V_TANTBSMT
1_2V
100NF-0603SMT
1
1UF-16V-0805SMT
2
4
1UF-16V-0805SMT
C89
PP4
1
3
of
10NF-0603SMT
C82
2
5
1
2
1UF-16V-0805SMT
1UF-16V-0805SMT
1UF-16V-0805SMT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
1
2
1
2
1
17
2
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 7. Power Supplies
100NF-0603SMT
A
B
C143
3_3V
C144
3_3V
Y
X
1(OFF)
X
LED-SMT1206_RED
D9
5
FPGA_CSSPI0N
SFLASH_Q_1
1
2
3
4
1
2
3
4
5
6
7
8
3_3V
CK
D
DU8
DU7
DU6
DU5
VSS
W#
1
3
3_3V
HEADER 2X2
2
4
8
7
6
5
16
15
14
13
12
11
10
9
8
7
6
5
J11
M25P80-FLASH
VCC
S#
Q HOLD#
W#
CLK
GND
DI
U15
FLASH1
M25P64-FLASH
HOLD#
VCC
DU1
DU2
DU3
DU4
S#
Q
U12
M25P80-FLASH
VCC
S#
Q HOLD#
W#
CLK
GND
DI
U10
SPI0_Q
FPGA_CCLK
FPGA_SISPI
FPGA_CCLK
FPGA_CCLK
3_3V
LED-SMT1206_RED
D10
680R-0603SMT
R53
ispJTAG
Slave Parallel
FLASH0
SFLASH_Q_0
SFLASH_Q_1
FLASH_DIS
FPGA_CSSPI0N
SFLASH_Q_0
3_3V
1
2
3
4
1(OFF)
1(OFF)
680R-0603SMT
R51
Master Parallel
0(ON)
0(ON)
Master Serial
1(OFF)
0(ON)
SPIX Flash
Slave Serial
1(OFF)
0(ON)
0(ON)
FPGA_CSSPI0N
SFLASH_Q_0
GSRN
X
1(OFF)
1(OFF)
[10] GSRN
R56
10K-0603SMT
C
10NF-0603SMT
1(OFF)
Q5
2N2222/SOT23
D11
CFG1
CFG0
R47
10K-0603SMT
R48
10K-0603SMT
1
R
D8
INITN
R55
10K-0603SMT
DONE
JUMPER1
J13
JUMPER1
J12
4
2
2
PROGRAMN
GSRN
0R-0603SMT
R64
PROGRAMN
FPGA RESETN/GSRN
1
3
3
6
3
2Y
1Y
2
4
Momentary Switch
B3F-1150
1
SW3
2
4
Momentary Switch
B3F-1150
1
SW2
SW1
SW DIP-3 CTS 194-3MST
DONE indicator will light when
configuration is successfully
completed
LED-SMT1206_RED
[5] PCIE_PERSTN
1
6
5
4
1
2
3
INITN indicator will light
if an error occurs during
configuration programming
CFG2
ON
R45
10K-0603SMT
R52
680R-0603SMT
3_3V
3_3V
R54
1(OFF)
LED-SMT1206_GREEN
0(ON)
R60
10K-0603SMT
Y
PROGRAMN
220R-0603SMT
G
3
2
R61
10K-0603SMT
SPI3 Flash
R62
5
4
2
3
1
SN74LVC125A/SO14
2A
2OE_N
1A
1
3_3V
1OE_N
U14A
1
2
HEADER 2
J2
C145
Configuration Mode
4_7K-0603SMT
0(ON)
100NF-0603SMT
CFG0
OUT2
OUT1
MAX6817
IN2
IN1
U11
4
6
SPIFASTN
R44
5
VCC
0(ON)
R65
3
11
8
4Y
3Y
FPGA_D0
FPGA_D7
10
12
13
9
SN74LVC125A/SO14
4A
4OE_N
3A
U14B
3OE_N
3_3V
3_3V
J10
1
1
JUMPER1
J9
JUMPER1
J7
HEADER 2X2
2
4
1
3
2
2
[8]
TDI_EC
TDO_EC
LOCAL_TDO
R222
10K-0603SMT
2
FPGA_D[0..7]
JUMPER1
1
3
5
ecp2m-672fpbga
TCK
2
PR62A/BUSY
PR62B/DOUT/CSON
PR63A/DI
PR63B/D7
PR64A/D6
PR64B/D5
PR65A/D4
PR65B/D3
PR66A/D2
PR66B/D1
PR67A/D0
PR67B/CSN
PR68A/CS1N
PR68B/WRITEN
FPGA_CSSPI0N
Y24
W23
V20
W21
AA24
Y23
W18
W22
Y20
W19
Y22
AB26
Y21
Y19
FPGA_CSSPI1N
J103
HEADER 3X2
2
4
6
J105
2
R221
10K-0603SMT
JUMPER1
2
1
1
2
3
HEADER 3
J5
J104
JUMPER1
J102
1
2
3
HEADER 3
TMS_EC
TMS_ISPCLK
1
1
FPGA_D7
FPGA_D0
J60
FPGA_SISPI
FPGA_CSSPI1N
FPGA_CSSPI0N
FPGA_D7
FPGA_D6
FPGA_D5
FPGA_D4
FPGA_D3
FPGA_D2
FPGA_D1
FPGA_D0
CSN
CS1N
WRITEN
TDI_BUF
TDI_ISPCLK
TDO_ISPCLK
[8] TMS_ISPCLK
[8] TDI_ISPCLK
[8] TDO_ISPCLK
10K-0603SMT
SPI0_Q
R58
4_7K-0603SMT
CFG1
100R-0603SMT
GND
2
R66
100R-0603SMT
R59
4_7K-0603SMT
0(ON)
1
2
3
DONE
FPGA_D7
FPGA_D6
FPGA_D5
FPGA_D4
FPGA_D3
FPGA_D2
FPGA_D1
FPGA_D0
CSN
CS1N
3_3V
FPGA_CCLK
FPGA_SISPI
CSN
4
6
OUT Y2
OUT Y1
2_5V
TCK
TMS_BUF
4.7K
4.7K
4
6
4.7K
4.7K
U9
IN A2
IN A1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
3_3V
EXBV8V472JV
OUT Y2
OUT Y1
1
2
3
HEADER 3
3_3V
J6
HEADER 17X2
NC7WZ16-MACO6A/Fairchild TinyLogic
R63
220R-0603SMT
D12
LED-SMT1206_GREEN
This LED
indicates activity
on TDI.
TDI_BUF
TCK
TMS_EC
TDO_EC
TDI_EC
CFG2
CFG1
CFG0
R49
10K-0603SMT
J4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
3_3V
AA21
AA22
AB23
AC26
AB25
AA23
AB24
AC3
AC4
V8
W8
H19
HEADER 3
J3
CONFIG
CFG2
CFG1
CFG0
PROGRAMN
DONE
INITN
CCLK
TCK
TMS
TDO
TDI
XRES
NC7WZ16-MACO6A/Fairchild TinyLogic
R
CFG2
RN2B
D
RN2C
5
100NF-0603SMT
IN A2
CS1N
3
1
3
1
D a te :
S iz e
C
3_3V
LOCAL_TMS
LOCAL_TCK
DONE
INITN
LOCAL_TDO
LOCAL_TDI
4.7K
INITN GND
DONE
TCK
TMS
NC
4.7K
1
S he e t
ECP2M PCI EXPRESS Card
P roje c t
Configuration/Testpoints
4.7K
VCC
ispEN_N
TDI
TDO
HEADER 10
2
3
4
5
6
8
9
10
J8
4.7K
4
of
EXBV8V472JV
7
1
FROM ISPVM CABLE
sysCONFIG
Connector
WRITEN
CFG0
CFG1
CFG2
1
PROGRAMN
DONE
INITN
R43
4_7K-0603SMT
FPGA_D6
R50
10K-0603SMT
10K-0603SMT
R46
FPGA_CCLK
3_3V
INITN
PROGRAMN
Title
U13
IN A1
3_3V
R40
R41
R42
10K-0603SMT
10K-0603SMT
10K-0603SMT
C142
100NF-0603SMT
U1B
RN2D
C147
VCC
GND
2
5
VCC
GND
2
100NF-0603SMT
2
RN1B
3
RN1C
4_7K-0603SMT
R57
GND
7
3
6
RN1D
4
14
VCC
1
RN2A
8
TDO_EC
2
7
TCK
4
5
TDI_EC
4
5
1
RN1A
8
LOCAL_TDO
2
7
LOCAL_TCK
3
6
LOCAL_TMS
5
3_3V
11
C146
18
LOCAL_TDI
100NF-0603SMT
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 8. Configuration/Testpoints
A
B
C
D
PERp0
PERn0
PCIE_CLKP
PCIE_CLKN
PCIE_3V3
12_0V
PCIE_CLKN
C428
R232
PCIE_CLKN
PCIE_CLKP
R216
R80
R79
0R-0603SMT
0R-0603SMT
100R-0603SMT
Place near U1
100R-0603SMT
150R-0603SMT
R233
150R-0603SMT
R231
10NF-0402SMT
150R-0603SMT
R215
C425
10NF-0402SMT
L_HDINN2
L_HDINP2
L_REFCLKN
U_REFCLKN
OUT_SATA_HOST50
50
L_HDOUTN1
L_HDOUTP1
L_HDOUTN2
L_HDOUTP2
L_HDINN1
L_HDINP1
OUT_SATA_TGT-
C430
C426
C424
C422
PRSNT1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST#
GND
REFCLK+
REFCLKGND
PERp0
PERn0
GND
+12V
+12V
RSVD_B3
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1
3.3Vaux
WAKE#
RSVD_B12
GND
PETp0
PETn0
GND
PRSNT3#
GND
PCI Express x1 Edge Finger Conn.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
x1
X1 PCIe Board Fingers
x1
CN4
Populate for PCIe Clock
from Edge Finger
L_REFCLKP
U_REFCLKP
C423
10NF-0402SMT
150R-0603SMT
OUT_SATA_HOST+
PCIE_CLKP
50
C421
OUT_SATA_TGTOUT_SATA_TGT+
IN_SATA_TGT+
IN_SATA_TGT-
10NF-0402SMT
R230
10NF-0402SMT
10NF-0402SMT
10NF-0402SMT
10NF-0402SMT
1
2
3
4
5
6
7
L_REFCLKP
[8]
[8]
1
PETp0
PETn0
PCIE_WAKEN
PCIE_3V3
[6]
PCIE_SMCLK [6]
PCIE_SMDAT [6]
L_REFCLKN
L_HDINN0
L_HDOUTP0
L_HDOUTN0
50
50
50
L_HDINP0
50
5
C148
C156
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
C157
C149
PERn0
PERp0
PETn0
PETp0
SFP_TXFAULT
SFP_TXDIS
SFP_MODDEF2
SFP_MODDEF1
SFP_MODDEF0
SFP_RATESEL
SFP_LOS
4
L_HDINP3
L_HDINN3
L_HDINP2
L_HDINN2
L_HDINP1
L_HDINN1
L_HDINP0
L_HDINN0
U_HDINP3
U_HDINN3
U_HDINP2
U_HDINN2
U_HDINP1
U_HDINN1
U_HDINP0
U_HDINN0
A14
B14
A15
B15
A23
B23
A24
B24
D19
E19
AF14
AE14
AF15
AE15
AF23
AE23
AF24
AE24
AC19
AB19
3_3V
ecp2m-672fpbga
U_HDINP3
U_HDINN3
U_HDINP2
U_HDINN2
U_HDINP1
U_HDINN1
U_HDINP0
U_HDINN0
U_REFCLKP
U_REFCLKN
L_HDINP3
L_HDINN3
L_HDINP2
L_HDINN2
L_HDINP1
L_HDINN1
L_HDINP0
L_HDINN0
L_REFCLKP
L_REFCLKN
U1A
6
5
4
3
2
1
R71,R77==OPEN
STUFF OPTION A:
REPLACE C148,C149
WITH 0-OHM SHUNTS
10K-0603SMT
R229
SFP_CAGE
10K-0603SMT
R228
3
HDIN
6
5
4
3
2
1
CG1
Place Capacitors
and Resistors as
Physically close to
device pin as possible
200K
200K
PCIe Terminations
HDOUT
TP18
TESTPOINT
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[8] L_REFCLKP
[8] L_REFCLKN
[8] U_REFCLKP
[8] U_REFCLKN
AC Coupled receiver
+ 200K Ohm to GND
B side = Primary Component Side(TOP)
A side = Secondary Component Side(BOTTOM)
PCIE_CLKP
PCIE_CLKN
[4] PCIE_PERSTN
OUT_SATA_HOST-
50
G
A+
AG
BB+
G
SATA
OUT_SATA_TGT+
OUT_SATA_HOST+
50
OUT_SATA_TGT+
OUT_SATA_TGT-
50
IN_SATA_HOST-
50
50
IN_SATA_HOST+
50
50
50
IN_SATA_TGT+
IN_SATA_TGT-
50
Target
CN2
SATA
IN_SATA_HOST+
IN_SATA_HOST-
R234
OUT_SATA_HOST+
OUT_SATA_HOST-
10K-0603SMT
R226
1
2
3
4
5
6
7
10K-0603SMT
R227
G
A+
AG
BB+
G
7
11
10
9
8
8
7
VeeT
TDTD+
VeeT
VccT
VccR
VeeR
RD+
RDVeeR
J23
Rosenberger 32K153-400E3
J20
Rosenberger 32K153-400E3
J32
Rosenberger 32K153-400E3
J29
Rosenberger 32K153-400E3
J26
Rosenberger 32K153-400E3
J24
Rosenberger 32K153-400E3
J21
Rosenberger 32K153-400E3
R223
L_HDINN3
SFP_RDN
J25
Rosenberger 32K153-400E3
J27
Rosenberger 32K153-400E3
J30
Rosenberger 32K153-400E3
J33
Rosenberger 32K153-400E3
J28
Rosenberger 32K153-400E3
J31
Rosenberger 32K153-400E3
U_HDINP1
U_HDINN1
U_HDINN2
U_HDINP2
U_HDINP3
U_HDINN3
1
1
1
1
1
1
2
J22
Rosenberger 32K153-400E3
U_HDINN0
1
3G SMAs
J19
Rosenberger 32K153-400E3
C438
100NFX5R-0402SMT
L_HDINP3
SFP_RDP
U_HDOUTP0
U_HDOUTN0
U_HDOUTP1
U_HDOUTN1
U_HDOUTP2
U_HDOUTN2
U_HDOUTP3
U_HDOUTN3
1
1
1
1
1
1
1
C436
1
1UH-1206SMT
L2
L1
1UH-1206SMT
SGMII
SMA_REFCLKN
R69
R70
51R-0603SMT
1
50
SMA_REFCLKP
R67
R68
51R-0603SMT
1
C435
10UF-16V_TANTBSMT
L_HDOUTP3
C437
100NFX5R-0402SMT
C434
C431
C429
100NFX5R-0402SMT
SFP_TDP
SFP_RDN
L_HDOUTN3
150R-0603SMT
R224
C427
100NFX5R-0402SMT
SFP_TDN
150R-0603SMT
U_HDINP0
SFP_RDP
J15
Rosenberger 32K153-400E3
J14
Rosenberger 32K153-400E3
2
1
20
19
18
17
16
15
14
13
12
11
50
U_HDOUTP3
U_HDOUTN3
U_HDOUTP2
U_HDOUTN2
U_HDOUTP1
U_HDOUTN1
U_HDOUTP0
U_HDOUTN0
L_HDOUTP3
L_HDOUTN3
L_HDOUTP2
L_HDOUTN2
L_HDOUTP1
L_HDOUTN1
L_HDOUTP0
L_HDOUTN0
SFP
HOST_SFP
VeeT
TxFault
TxDisable
Mod_Def_2
Mod_Def_1
Mod_Def_0
RateSel
LOS
VeeR
VeeR
A17
B17
A18
B18
A20
B20
A21
B21
AF17
AE17
AF18
AE18
AF20
AE20
AF21
AE21
J18
Rosenberger 32K153-400E3
11
10
9
1
2
3
4
5
6
7
8
9
10
CN5
U_HDOUTP3
U_HDOUTN3
U_HDOUTP2
U_HDOUTN2
U_HDOUTP1
U_HDOUTN1
U_HDOUTP0
U_HDOUTN0
L_HDOUTP3
L_HDOUTN3
L_HDOUTP2
L_HDOUTN2
L_HDOUTP1
L_HDOUTN1
L_HDOUTP0
L_HDOUTN0
SERDES
10K-0603SMT
Host
R225
1K-0603SMT
3
100NF-0603SMT
CN1
4
100NF-0603SMT
SATA
PETp0
R77
R71
200K-0402SMT 200K-0402SMT
PETn0
2
2
2
2
2
2
2
2
100NF-0603SMT
5
C433
10UF-16V_TANTBSMT
U_REFCLKN
U_REFCLKP
1
1
S he e t
ECP2M PCI EXPRESS Card
P roje c t
SERDES
3_3V
D a te :
S iz e
C
Title
C432
0R-0603SMT
0R-0603SMT
100NF-0603SMT
2
2
2
2
2
2
2
2
2
19
2
5
of
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 9. SERDES
A
B
C
SP9
1_8V
SP11
SP6
SP8
SP10
SP12
5
DDR_VREF1
[10] TestArray11
R83
OPEN-0603SMT
1K_ADJ/SMT3MM
R82
R84
1K-0603SMT
R127
0R-0603SMT
R126
0R-0603SMT
[7] DDR2_DQS1
[7] DDR2_DQS1#
[7] DDR2_DQS0
[7] DDR2_DQS0#
[7] DDR2_DQ[0:15]
DDR2_DQ[0:15]
RN12
1
2
3
4
RN13
1
2
3
4
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
RN14
1
2
3
4
RN11
1
2
3
4
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQS1
DDR2_DQS1#
DDR2_DQS0
DDR2_DQS0#
RN10
1
2
3
4
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
33
33
33
33
33
4
741X083
8
7
6
5
741X083
8
7
6
5
741X083
8
7
6
5
741X083
8
7
6
5
741X083
8
7
6
5
Bank5
ecp2m-672fpbga
DQS1
DQS1#
DQS0
DQS0#
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
All these 741X083/33-ohm
devices should be placed
near the FPGA.
[10] TestArray10
[10] TestArray9
[10] TestArray13
[10] TestArray12
ODT0
CS0#
[10] TestArray15
[10] TestArray14
CAS#
RAS#
A4
A7
BA0
A11
A5
BA1
A1
A6
A3
A2
A0
A9
A12
DQ8
DQ9
DQ15
DQ14
DQ12
DQ13
DQ10
DQ11
DQS1
DQS1#
DM1
A8
Bank4
Bottom
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
C176
CTS-RT1402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
C177
C178
FPGA_VTT
R1=50 Ohm
R1
C179
R1
C180
RP1
A1
B1
C1
D1
E1
F1
G1
H1
J1
A1
B1
C1
D1
E1
F1
G1
H1
J1
K
K#
CS0#
BA0
BA1
WE#
RAS#
CAS#
ODT0
A12
DM0
DM1
CKE0#
FPGA_VTT
C181
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
3
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C175
A3
B3
C3
D3
E3
F3
G3
H3
J3
FPGA_VTT
This RT140287/50-ohm pack
should be placed near the FPGA.
TestArray8
TestArray7
TestArray6
TestArray5
TestArray4
TestArray3
TestArray2
TestArray1
OSC_IN_1 [8]
A8
A9
A10
A11
A4
A5
A6
A7
741X083
741X083
741X083
741X083
741X083
741X083
22
22
22
22
22
22
RN9
8
7
6
5
RN8
8
7
6
5
RN7
8
7
6
5
RN6
8
7
6
5
RN5
8
7
6
5
DDR2_K
DDR2_K#
DDR2_CS0#
DDR2_BA0
DDR2_BA1
DDR2_WE#
DDR2_RAS#
DDR2_CAS#
DDR2_ODT0
DDR2_A12
DDR2_DM0
DDR2_DM1
DDR2_CKE0#
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
741X083
DDR2_A0
8
DDR2_A1
7
DDR2_A2
6
DDR2_A3
5
RN4
8
7
6
5
22
1_8V
DDR_VREF1
R87
0R-0603SMT
2_5V
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
RN3
1
2
3
4
C169
1
1
1
1
1
1
1
1
1
1
SP7
R81
1K-0603SMT
1
1
SP5
C166
10NF-0603SMT
PLL_BYPASS [8]
PS0
[8]
PS1
[8]
GOE
[8]
SGATE [8]
REFSEL [8]
OEX
[8]
OEY
[8]
ISPCLK_RST [8]
ISPCLK_LOCK [8]
PCIE_SMCLK [5]
PCIE_SMDAT [5]
PCIE_WAKEN [5]
J2
J2
PB40A/PCLKT4_0
PB40B/PCLKC4_0
PB41B/VREF1_4
PB42A
PB42B
PB48A
PB49A
PB49B
PB50B
PB51A
PB52A
PB52B
PB54A
PB54B
PB57A
PB58A
PB59B
PB60A
PB61A
PB61B
PB63A
PB65A
PB65B
PB68B
PB69A
PB69B
PB70B
PB71A
PB71B
PB72B
PB73A
PB73B
AC13
Y14
AC14
AB14
AA14
AC15
AB15
AC16
AB16
AA15
Y15
AC17
W15
AB17
AB20
AC20
W16
AA17
AA18
Y17
AC21
W17
AA19
Y18
AC22
AB21
AD26
AC23
AC25
W20
V17
AA20
G2
H2
H2
R217
51R-0603SMT
DDR2_DQS1
SP4
E2
E2
R218
51R-0603SMT
DDR2_DQS1#
SP3
F2
F2
G2
R219
51R-0603SMT
DDR2_DQS0
A0
A1
A2
A3
C167
DM0
WE#
DQS0
DQS0#
DQ0
DQ1
DQ3
DQ7
DQ6
DQ4
DQ2
DQ5
CKE0#
A10
2
5
4
+
VDDQ
VREF
SD
U16
47UF-16V_TANTBSMT
2
LP2996-SO8
C168
D
100NF-0603SMT
SP2
D2
D2
All these 741X083/22-ohm
devices should be placed
near the FPGA.
100NF-0603SMT
SP1
C2
R220
51R-0603SMT
DDR2_DQS0#
PB2A
PB2B
PB3A
PB3B
PB4A
PB4B
PB5A
PB5B
PB6A
PB6B
PB7A
PB7B
PB8A
PB8B
PB9A
PB9B
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB33A
PB33B
PB34A/VREF2_5
PB34B/VREF1_5
PB35A/PCLKT5_0
PB35B/PCLKC5_0
C170
U1C
B2
B2
AB6
Y8
AD1
AD2
AC5
AA8
AC6
W9
AB7
Y9
AD3
AD4
AA9
W10
AC7
Y10
AE2
AD5
AE4
AE3
W11
AB8
AE5
AD6
AA10
AC8
W12
AC9
W13
AB10
AF3
AF4
AF5
AF6
Y12
AB11
AD7
AF7
AD8
AA12
AE8
AF8
AD9
AC10
AC11
AB12
AD10
Y13
AF9
AE9
AF10
AE10
AD11
AF11
AA13
AB13
W14
AC12
AF12
AD12
1UF-16V-0805SMT
K
K#
A2
A2
C2
2
1_8V
[7]
VTT
VSENSE
C172
8
3
+
DDR2_K [7]
DDR2_K# [7]
DDR2_CS0# [7]
DDR2_BA0 [7]
DDR2_BA1 [7]
C173
DDR2_WE# [7]
DDR2_RAS# [7]
DDR2_CAS# [7]
DDR2_ODT0 [7]
DDR2_DM0 [7]
DDR2_DM1 [7]
DDR2_CKE0 [7]
DDR2_A[0:12]
C171
[10] TestArray16
R85
4_7K-0603SMT
3
100UF-FKSMT
4
6
7
AVIN
PVIN
GND
1
100NF-0603SMT
1UF-16V-0805SMT
5
C174 +
R86
0R-0603SMT
1
Title
D a te :
S iz e
C
1
S he e t
ECP2M PCI EXPRESS Card
P roje c t
DDR2 FPGA Controller
PP9
FPGA_VTT
6
of
11
ALL Memory controller
buses, clocks, and control
traces must be 50 Ohm
Transmission lines
1
20
2
DDR2_A[0:12]
10UF-16V_TANTBSMT
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 10. DDR2 FPGA Controller
A
B
5
C197
10NF-0603SMT
1_8V
C202
FB4
BLM41PG600SN1
+ C211
VDDL
R93
OPEN-0603SMT
C203
R90
1K-0603SMT
1K_ADJ/SMT3MM
10NF-0603SMT
R94
1K-0603SMT
C212
+ C200
1_8V
+ C198
1_8V
1UF-16V-0805SMT
C201
C199
4
PP11
1_8V
R88
4_7K-0603SMT
2_5V
C182
100NF-0603SMT
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
VDDL
VSSDL
VDDQ
VREF
SD
U18B
5
U17
1UF-16V-0805SMT
DDR2-SDRAM-84FBGA
A1
E1
J9
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J2
J1
J7
2
C183
4
6
7
C184
8
3
DDR2-SDRAM-84FBGA
U18A
C194
+
1_8V
+
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
LDQS
LDQS#/NU
UDQS
UDQS#/NU
LDM
UDM
CK
CK#
CKE
WE#
RAS#
CAS#
ODT
CS#
BA0
BA1
NC_A2
NC_E2
NC_R8
RFU_L1
RFU_R3
RFU_R7
100NF-0603SMT
C185
LP2996-SO8
VTT
VSENSE
AVIN
PVIN
47UF-16V_TANTBSMT
C193
2_5V
100NF-0603SMT
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
F7
E8
B7
A8
F3
B3
J8
K8
K2
K3
K7
L7
K9
L8
L2
L3
A2
E2
R8
L1
R3
R7
C195
10UF-16V_TANTBSMT
DDR2_DQ15
DDR2_DQ14
DDR2_DQ13
DDR2_DQ12
DDR2_DQ11
DDR2_DQ10
DDR2_DQ9
DDR2_DQ8
DDR2_DQ7
DDR2_DQ6
DDR2_DQ5
DDR2_DQ4
DDR2_DQ3
DDR2_DQ2
DDR2_DQ1
DDR2_DQ0
DDR2_A0
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_DQS0
DDR2_DQS0#
DDR2_DQS1
DDR2_DQS1#
DDR2_DM0
DDR2_DM1
DDR2_K
DDR2_K#
DDR2_CKE0#
DDR2_WE#
DDR2_RAS#
DDR2_CAS#
DDR2_ODT0
DDR2_CS0#
DDR2_BA0
DDR2_BA1
C196 +
R89
0R-0603SMT
1UF-16V-0805SMT
4
3
PP10
DDR_VTT
3
[6]
[6]
DDR2_DQS0 [6]
DDR2_DQS0# [6]
DDR2_DQS1 [6]
DDR2_DQS1# [6]
DDR2_DM0 [6]
DDR2_DM1 [6]
DDR2_K [6]
DDR2_K# [6]
DDR2_CKE0 [6]
DDR2_WE# [6]
DDR2_RAS# [6]
DDR2_CAS# [6]
DDR2_ODT0 [6]
DDR2_CS0# [6]
DDR2_BA0 [6]
DDR2_BA1 [6]
DDR2_A[0:12]
DDR2_DQ[0:15]
DDR2_DM1
DDR2_DM0
VTT
C187
C188
C189
C190
C191
C192
C205
CTS-RT1402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
DDR_VTT
CTS-RT1402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
R1=50 Ohm
C206
R1
R1
C207
R1=50 Ohm
C208
R1
R1
C209
RP3
A1
B1
C1
D1
E1
F1
G1
H1
J1
RP2
A1
B1
C1
D1
E1
F1
G1
H1
J1
C210
A1
B1
C1
D1
E1
F1
G1
H1
J1
A1
B1
C1
D1
E1
F1
G1
H1
J1
DDR2_WE#
DDR2_RAS#
DDR2_CAS#
DDR2_BA1
DDR2_BA0
DDR2_CS0#
DDR2_ODT0
DDR2_CKE0#
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_A0
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
X2
2
DDR2_K#
DDR2_K
Termination
at end of line
VTT
RESISTOR
R96
R95
51R-0603SMT
51R-0603SMT
DDR2
Device Pin
X1
1
DDR_VTT
D a te :
S iz e
C
Title
1
S he e t
ECP2M PCI EXPRESS Card
P roje c t
DDR2 Device/Termination
U1 Pin X1
needs to be matched length
for all traces
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C204
DDR_VTT
A3
B3
C3
D3
E3
F3
G3
H3
J3
A3
B3
C3
D3
E3
F3
G3
H3
J3
DDR_VTT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C186
DDR_VTT
2
J2
R92
C213
J2
J2
F2
F2
R91
0R-0603SMT
100NF-0603SMT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
100NF-0603SMT
C
1_8V
1
2
H2
H2
J2
C2
E2
E2
D
C214
21
1UF-16V-0805SMT
10NF-0603SMT
DDR2_DQ[0:15]
C215
DDR2_A[0:12]
100NF-0603SMT
E2
E2
D2
D2
GND
1
D2
D2
C2
100UF-FKSMT
G2
G2
G2
H2
H2
B2
B2
B2
B2
1
2
F2
F2
G2
A2
A2
C2
A2
A2
C2
5
7
of
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 11. DDR2 Device/Termination
DDR2_A[0:12]
22UF-16V_TANTBSMT
1UF-16V-0805SMT
A
B
C
1_6R-0603SMT
C229
+
14
R99
130R-0603SMT
R104
82R-0603SMT
82R-0603SMT
OSC_P
OSC_N
8
1
R107
R97
130R-0603SMT
13
14
100NF-0603SMT
C230
R103 0R-0603SMT
R102 0R-0603SMT
C413
10UF-16V_TANTBSMT
3_3V
10
9
8
7
6
5
4
3
2
1
20
19
18
17
16
15
14
13
12
11
SW4
5
TDA10H0SK1
10
9
8
7
6
5
4
3
2
1
20
19
18
17
16
15
14
13
12
11
3_3V
1
R109
R121
1K-0603SMT
R120
2_2K-0603SMT
ISPCLK_LOCK [6]
PLL_BYPASS [6]
PS0
[6]
PS1
[6]
GOE
[6]
SGATE [6]
REFSEL [6]
OEX
[6]
OEY
[6]
ISPCLK_RST [6]
J36
Johnson 142-0711-201
D13
LED-SMT1206_ORANGE
O
51R-0603SMT
C412
100NF-0603SMT
R111
680R-0603SMT
J35
Johnson 142-0711-201
1
10NF-0603SMT
9
10NF-0603SMT
92
89
88
87
85
43
44
45
86
PLL_BYPASS
PS0
PS1
GOE
SGATE
REFSEL
OEX
OEY
ISPCLK_RST
C231
39
4
[6] OSC_IN_1
[10] OSC_IN_2
[4] TDI_ISPCLK
[4] TDO_ISPCLK
[4] TMS_ISPCLK
[4] TCK
REFB-
REFB+
LOCK
TEST1
TEST2
PLL_BYPASS
PS0
PS1
GOE
SGATE
REFSEL
OEX
OEY
RESET
REFA-
REFA+
U2
OSC_IN_1
OSC_IN_2
100NF-0603SMT
41
REFCLK_EXT_IN_N
R110
42
72
REFCLK_EXT_IN_P
3_3V
ISPCLK_LOCK
91
90
38
C416
10NF-0603SMT
100NF-0603SMT
C228
FB21
BLM41PG471SN1L
REFA_N
C415
10NF-0603SMT
REFA_P
EXB2HV102JV
C414
51R-0603SMT
To Drive any of the SERDES reference clocks directly from
SMAs, put ispCLOCK in bypass
Q_N
Q
Y1
110-93-314-41-001
VDD
GND
7
3_3V
15
R98
2
C220
1
2
3
4
3
GND
N/C
CY2304-1
REF
FBK
CLKA1
VDD
CLKA2 CLKB2
GND CLKB1
U19
Y2
OUT
Vcc
8
7
6
5
2
1
CTS-CB3LV-3C-100.00MHZ
4
C222
100NF-0603SMT
C226
FB7
BLM41PG471SN1L
C221
3
100NF-0603SMT
ispCLK5620A-100TQFP
31
GNDA
3_3V
3_3V
12
100NF-0603SMT
30
VCCA
D
16
RN15A
1
1K
RN15B
2
1K
RN15C
3
1K
RN15D
4
1K
RN15E
5
11
6
10
1K
RN15G
7
1K
RN15H
8
1K
RN15F
2
1K
100NF-0603SMT
47
71
VCCD1
VCCD2
FB22
BLM41PG471SN1L(DNP)
TDI
TDO
TMS
TCK
84
73
82
83
3
7
11
15
19
51
55
59
63
67
VCCO_0
VCCO_1
VCCO_2
VCCO_3
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_8
VCCO_9
RESERVED1
RESERVED3
RESERVED2
RESERVED4
40
REFVTT
80
95
81
96
3_3V
C224
C223
2_5V
74
VCCJ
2_5V
3
OSC_IN_3
OSC_IN_4
3_3V
100NF-0603SMT
32
33
34
35
36
37
46
93
6
10
14
18
22
54
58
62
66
70
10NF-0603SMT
C233
GNDD_1
GNDD_2
GNDD_3
GNDD_4
GNDD_5
GNDD_6
GNDD_7
GNDD_8
GNDO_0
GNDO_1
GNDO_2
GNDO_3
GNDO_4
GNDO_5
GNDO_6
GNDO_7
GNDO_8
GNDO_9
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
BANK_9B
5
4
9
8
13
12
17
16
21
20
53
52
57
56
61
60
65
64
69
68
100NF-0603SMT
OSC_IN_3 [10]
OSC_IN_4 [10]
100NF-0603SMT
C232
10NF-0603SMT
C227
3_3V
C225
R101 OPEN-0603SMT
R100 OPEN-0603SMT
R108
3_3V
R122
OPEN-0603SMT
2
R123
OPEN-0603SMT
R124
OPEN-0603SMT
R125
OPEN-0603SMT
R115
OPEN-0603SMT
R114
OPEN-0603SMT
3_3V
Trigger Out
D a te :
S iz e
C
Title
R116
100R-0603SMT
1
S he e t
ECP2M PCI EXPRESS Card
P roje c t
Clocks
8
R119
100R-0603SMT
1
R118
100R-0603SMT
LS_PLL_CLKP
R117
100R-0603SMT
Place near to U1
R113
OPEN-0603SMT
3_3V
51R-0603SMT
1
J34
Johnson 142-0711-201
L_REFCLKN [5]
L_REFCLKP [5]
[5]
U_REFCLKP [5]
U_REFCLKN
R112
OPEN-0603SMT
3_3V
RS_PLL_CLKP [9]
RS_PLL_CLKN [9]
RS_PCLK_CLKP [9]
RS_PCLK_CLKN [9]
LS_PLL_CLKP [10]
LS_PLL_CLKN [10]
LS_PCLK_CLKP [10]
LS_PCLK_CLKN [10]
BANK1_REFCLKP
R105 OPEN-0603SMT
BANK1_REFCLKN
R106 OPEN-0603SMT
BANK0_REFCLKN
BANK0_REFCLKP
2
U_REFCLKP
4
U_REFCLKN
3_3V
L_REFCLKP
NC1
NC2
NC3
NC4
NC5
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
1
2
23
24
25
26
27
28
29
48
49
50
75
76
77
78
79
94
97
98
99
100
2
L_REFCLKN
5
RS_PLL_CLKP
RS_PLL_CLKN
RS_PCLK_CLKP
LS_PLL_CLKN
LS_PCLK_CLKP
RS_PCLK_CLKN
22
LS_PCLK_CLKN
of
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 12. Clocks
100NF-0603SMT
A
B
C
5
J51
Johnson 142-0711-201
J49
Johnson 142-0711-201
J47
Johnson 142-0711-201
J45
Johnson 142-0711-201
J43
Johnson 142-0711-201
J41
Johnson 142-0711-201
2
2
2
2
2
2
2
2
LVDS_INP_1
LVDS_INN_1
LVDS_INP_2
LVDS_INN_2
LVDS_INP_3
1
1
1
1
1
1
LVDS_INN_3
DQS PAIR
LVDS_INN_0
R130
100R-0603SMT
R132
100R-0603SMT
R134
100R-0603SMT
R136
100R-0603SMT
4
J52
Johnson 142-0711-201
J50
Johnson 142-0711-201
J48
Johnson 142-0711-201
J46
Johnson 142-0711-201
J44
Johnson 142-0711-201
J42
Johnson 142-0711-201
J40
Johnson 142-0711-201
2
2
2
2
LVDS_OUTN_2
LVDS_OUTP_3
1
1
3
LVDS_OUTP_2
1
DP1
R138
LVDS_PROBEP
LVDS_PROBEN
Place this resistor
close to test point
100R-0603SMT
1
LVDS_OUTN_1
1
LVDS_OUTN_3
LVDS_OUTP_1
1
1
LVDS_OUTN_0
1
R131
100R-0603SMT
R133
100R-0603SMT
R135
100R-0603SMT
R137
100R-0603SMT
2
2
2
2
1
3
[8] RS_PCLK_CLKP
[8] RS_PCLK_CLKN
Bank2
ecp2m-672fpbga
2
Right
RS_PLL_CLKP
RS_PLL_CLKN
2
Bank3
PR9A/VREF1_2
PR9B/VREF2_2
PR11A*/RUM0_SPLLT_IN_A
PR11B*/RUM0_SPLLC_IN_A
PR37A*/PCLKT3_0
PR37B*/PCLKC3_0
PR12A/RUM0_SPLLT_FB_A
PR12B/RUM0_SPLLC_FB_A
PR38A/VREF1_3
PR13A*
PR38B/VREF2_3
PR13B*
PR39A*
PR14A
PR39B*
PR14B
PR40A
PR15A*
PR40B
PR15B*
PR41A*/RLM2_SPLLT_IN_A
PR41B*/RLM2_SPLLC_IN_A
PR16A
PR16B
PR42A/RLM2_SPLLT_FB_A
PR17A*
PR42B/RLM2_SPLLC_FB_A
PR17B*
PR44A*
PR18A
PR44B*
PR18B
PR45A
PR19A*
PR45B
PR19B*
PR46A*
PR46B*
PR20A
PR20B
PR47A
PR21A*
PR47B
PR21B*
PR48A*
PR22A
PR48B*
PR49A
PR22B
PR23A*
PR49B
PR23B*
PR50A*
PR24A
PR50B*
PR24B
PR51A
PR25A*
PR51B
PR25B*
PR53A*
PR26A
PR53B*
PR54A
PR26B
PR28A*/RUM1_SPLLT_IN_A
PR54B
PR28B*/RUM1_SPLLC_IN_A
PR55A*
PR55B*
PR29A/RUM1_SPLLT_FB_A
PR29B/RUM1_SPLLC_FB_A
PR56A
PR30A*
PR57A*/RLM0_GPLLT_FB_A
PR30B*
PR57B*/RLM0_GPLLC_FB_A
PR31A
PR58A/RLM0_GPLLT_IN_A
PR58B/RLM0_GPLLC_IN_A
PR31B
PR32A*
PR59A*/RLM0_GDLLT_IN_A
PR32B*
PR59B*/RLM0_GDLLC_IN_A
PR33A
PR60A/RLM0_GDLLT_FB_A
PR33B
PR60B/RLM0_GDLLC_FB_A
PR34A*
PR34B*
PR35A/PCLKT2_0
PR35B/PCLKC2_0
RS_PCLK_CLKP
RS_PCLK_CLKN
J39
Johnson 142-0711-201
LOOP_P0
LOOP_N0
LOOP_P15
LOOP_N15
LOOP_P1
LOOP_N1
LOOP_P14
LOOP_N14
LOOP_P2
LOOP_N2
LOOP_P13
LOOP_N13
LOOP_P3
LOOP_N3
LOOP_P12
LOOP_N12
LOOP_P4
LOOP_N4
LOOP_P11
LOOP_N11
LOOP_P5
LOOP_N5
LOOP_P10
LOOP_N10
LOOP_P6
LOOP_N6
LOOP_P9
LOOP_N9
LOOP_P7
LOOP_N7
LOOP_P8
LOOP_N8
LOOP_P8
LOOP_N8
LOOP_P7
LOOP_N7
LOOP_P9
LOOP_N9
LOOP_P6
LOOP_N6
LOOP_P10
LOOP_N10
LOOP_P5
LOOP_N5
LOOP_P11
LOOP_N11
RS_PCLK_CLKP
RS_PCLK_CLKN
LOOP_P0
LOOP_N0
[10] TestArray17
[10] TestArray18
DQS PAIR
LVDS_OUTP_3
LVDS_OUTN_3
LVDS_INP_3
LVDS_INN_3
LOOP_P12
LOOP_N12
LOOP_P4
LOOP_N4
LVDS_INP_1
LVDS_INN_1
LOOP_P3
LOOP_N3
LOOP_P13
LOOP_N13
LOOP_P2
LOOP_N2
LOOP_P14
LOOP_N14
LOOP_P1
LOOP_N1
LOOP_P15
LOOP_N15
LOOP_P0
LOOP_N0
LVDS_OUTP_0
LVDS_OUTN_0
LVDS_INP_2
LVDS_INN_2
LVDS_OUTP_1
LVDS_OUTN_1
LVDS_PROBEP
LVDS_PROBEN
LVDS_OUTP_2
LVDS_OUTN_2
LVDS_INP_0
LVDS_INN_0
TestArray22 [10]
TestArray23 [10]
RS_PLL_CLKP [8]
RS_PLL_CLKN [8]
TestArray21 [10]
TestArray19 [10]
TestArray20 [10]
Place these resistors
close to
U1 Device
N23
M21
P26
P25
N22
N20
P22
N21
P24
P23
N19
R22
R24
R23
P19
P21
R26
T26
R20
R21
R19
T19
U26
U25
T23
T22
T24
U24
V26
V25
U22
U18
W26
W25
U21
V24
W24
U20
V23
Y26
AA26
U19
V21
LOOP_P1
LOOP_N1
LVDS_OUTP_0
LOOP_P2
LOOP_N2
1
LOOP_P3
LOOP_N3
J38
Johnson 142-0711-201
LOOP_P4
LOOP_N4
LVDS_INP_0
LOOP_P5
LOOP_N5
1
LOOP_P6
D a te :
S iz e
C
Title
LOOP_N6
U1E
LOOP_P7
LOOP_N7
J37
Johnson 142-0711-201
E23
E24
F26
G26
F21
H20
F24
F23
F22
J18
G23
G24
K19
G22
H26
H25
H24
H23
J19
G21
J26
J25
J20
H22
K18
H21
J21
K20
J24
J23
K21
L19
K23
K24
K26
K25
M19
K22
L26
M26
M20
L23
L24
L22
N26
M23
M24
M22
N25
N24
LOOP_P8
1
LOOP_P14
LOOP_P15
1
S he e t
ECP2M PCI EXPRESS Card
P roje c t
Differential I/O Loops
LOOP_N8
Place these resistors
close to
SMA pair
LOOP_P9
LOOP_N9
2
LOOP_P10
LOOP_N10
Place these resistors
close to
U1 Device
3
LOOP_P11
LOOP_N11
4
LOOP_P12
LOOP_N12
D
5
LOOP_P13
LOOP_N13
R139
100R-0603SMT
R140
100R-0603SMT
R141
100R-0603SMT
R142
100R-0603SMT
R143
100R-0603SMT
R144
100R-0603SMT
R145
100R-0603SMT
R146
100R-0603SMT
R147
100R-0603SMT
R148
100R-0603SMT
R149
100R-0603SMT
R150
100R-0603SMT
R151
100R-0603SMT
R152
100R-0603SMT
R153
100R-0603SMT
R154
100R-0603SMT
R155
100R-0603SMT
R156
100R-0603SMT
LOOP_N14
23
LOOP_N15
9
of
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 13. Differential I/O Loops
A
B
C
5
TA49
TA50
TA51
TA52
TA53
TA54
TA55
TA56
TA57
TA58
TA59
TA60
TA37
TA38
TA39
TA40
TA41
TA42
TA43
TA44
TA45
TA46
TA47
TA48
TA25
TA26
TA27
TA28
TA29
TA30
TA31
TA32
TA33
TA34
TA35
TA36
TA13
TA14
TA15
TA16
TA17
TA18
TA19
TA20
TA21
TA22
TA23
TA24
TA1
TA2
TA3
TA4
TA5
TA6
TA7
TA8
TA9
TA10
TA11
TA12
TestArray49
TestArray50
TestArray51
TestArray52
TestArray53
TestArray54
TestArray55
TestArray56
TestArray57
TestArray58
TestArray59
TestArray60
TestArray37
TestArray38
TestArray39
TestArray40
TestArray41
TestArray42
TestArray43
TestArray44
TestArray45
TestArray46
TestArray47
TestArray48
TestArray13
TestArray14
TestArray15
TestArray16
TestArray17
TestArray18
TestArray19
TestArray20
TestArray21
TestArray22
TestArray23
TestArray24
TestArray1
TestArray2
TestArray3
TestArray4
TestArray5
TestArray6
TestArray7
TestArray8
TestArray9
TestArray10
TestArray11
TestArray12
BGA
H2
J3
G1
H3
J7
H5
G5
G6
F3
J8
E1
J9
E3
F5
D3
F6
C2
TestArray13
TestArray14
TestArray15
TestArray16
TestArray17
TestArray18
TestArray19
TestArray20
TestArray21
TestArray22
TestArray23
TestArray1
TestArray2
TestArray3
TestArray4
TestArray5
TestArray6
TestArray7
TestArray8
TestArray9
TestArray10
TestArray11
TestArray12
[6]
[6]
[6]
[6]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
18
12
9
RN17H 8
2
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[4]
38
50
37
49
2
26
14
13
25
1
3
51
39
27
15
4
52
40
28
16
53
41
29
17
5
54
42
30
18
6
7
4
55
43
31
19
8
56
44
32
20
9
57
45
33
21
10
58
46
34
22
11
59
47
35
23
12
60
48
36
24
TestArray24
TestArray37
TestArray38
TestArray39
TestArray40
GSRN
SFP_TXFAULT
SFP_TXDIS
SFP_MODDEF2
SFP_MODDEF1
SFP_MODDEF0
SFP_RATESEL
SFP_LOS
[8] LS_PLL_CLKP
[8] LS_PLL_CLKN
10
RN17G 7
1
9
12
8
11
EXB2HV121JV
14 150R
RN17C 3
6
13
15
RN17B 2
5
RN17E 5
16
RN17A 1
4
RN17F 6
10
RN16G 7
3
16
11
RN16F 6
17
13
12
RN16H 8
RN17D 4
13
9
RN16D 4
RN16E 5
15
[8] OSC_IN_2
14
RN16C 3
11
7
R157
150R-0603SMT
RN16A 1
16
EXB2HV121JV
RN16B 2
150R
15
14
10
LTP-587HR/16-SEGMENT
D14
Test Points Array on Component Side
2_5V
DP
U
T
S
R
P
N
M
K
H
G
F
E
D
C
B
D
SEGMENT
A
B
C
D
E
F
G
H
K
M
N
P
R
S
T
U
DP
TestArray53
TestArray54
TestArray51
TestArray52
TestArray49
TestArray50
C2
C1
F6
H9
D3
D2
F5
H8
E3
E2
J9
E4
E1
D1
J8
F4
F3
F1
G6
K9
G5
G4
H5
H6
J7
H4
H3
G3
G1
H1
J3
J4
H2
J2
K7
J6
K5
L5
K4
L4
K3
L3
J1
K2
K1
L1
K8
M5
M4
M3
L8
M6
M1
N1
N3
N2
N5
N4
M7
M8
Bank7
G7
G8
F8
J10
D4
C3
F7
G9
C4
B2
C5
B3
E7
H10
F9
G10
E6
D5
H11
D7
F10
C6
A3
A4
A5
A6
H12
D8
G12
C8
C7
D6
H13
D9
A7
B8
C9
G13
E10
F12
A8
B9
E8
C10
A9
H14
D10
F13
E11
G14
D11
B10
A10
H15
H18
H16
D12
A11
A12
F14
C11
G15
C12
3
ecp2m-672fpbga
Top
Bank6
E13
H17
E12
F15
D13
D14
E14
G17
E15
G18
D15
E16
F18
F19
D16
F17
D17
E17
TestArray59
TestArray60
TestArray57
TestArray58
TestArray55
TestArray56
Left
PL37A*/PCLKT6_0
PL37B*/PCLKC6_0
PL38A/VREF2_6
PL38B/VREF1_6
PL39A*
PL39B*
PL40A
PL40B
PL41A*/LLM2_SPLLT_IN_A
PL41B*/LLM2_SPLLC_IN_A
PL42A/LLM2_SPLLT_FB_A
PL42B/LLM2_SPLLC_FB_A
PL44A*
PL44B*
PL45A
PL45B
PL46A*
PL46B*
PL47A
PL47B
PL48A*
PL48B*
PL49A
PL49B
PL50A*
PL50B*
PL51A
PL51B
PL55A*
PL55B*
PL57A*/LLM0_GPLLT_IN_A
PL57B*/LLM0_GPLLC_IN_A
PL58A/LLM0_GPLLT_FB_A
PL58B/LLM0_GPLLC_FB_A
PL59A*/LLM0_GDLLT_IN_A
PL59B*/LLM0_GDLLC_IN_A
PL60A/LLM0_GDLLT_FB_A
PL60B/LLM0_GDLLC_FB_A
PL62A*
PL62B*
PL63A
PL63B
PL64A*
PL64B*
PL65A
PL65B
PL66A*
PL66B*
PL67A
PL67B
PL68A*
PL68B*
PL69A
PL69B
PT2A
PT2B
PT38A/PCLKT1_0
PT3A
PT38B/PCLKC1_0
PT3B
PT39A/VREF1_1
PT4A
PT39B/VREF2_1
PT4B
PT40A
PT5A
PT40B
PT41A
PT5B
PT41B
PT6A
PT6B
PT42A
PT7A
PT42B
PT43A
PT7B
PT43B
PT8A
PT8B
PT44A
PT44B
PT9A
PT9B
PT45A
PT45B
PT10A
PT46A
PT10B
PT11A
PT46B
PT11B
PT12A
PT12B
PT13A
PT13B
PT14A
PT14B
PT15A
PT15B
PT16A
PT16B
PT17A
PT17B
PT18A
PT18B
PT19A
PT19B
PT20A
PT20B
PT21A
PT21B
PT22A
PT22B
PT23A
PT23B
PT24B
PT29A
PT29B
PT30A
PT30B
PT31A
PT31B
PT32A
PT32B
PT33A
PT33B
PT34A
PT34B
PT35A
PT35B
PT36A/VREF1_0
PT36B/VREF2_0
PT37A/PCLKT0_0
PT37B/PCLKC0_0
U1F
ecp2m-672fpbga
PL2A*
PL2B*
PL3A
PL3B
PL4A*
PL4B*
PL5A
PL5B
PL6A*
PL6B*
PL7A
PL7B
PL8A*
PL8B*
PL9A/VREF2_7
PL9B/VREF1_7
PL11A*/LUM0_SPLLT_IN_A
PL11B*/LUM0_SPLLC_IN_A
PL12A/LUM0_SPLLT_FB_A
PL12B/LUM0_SPLLC_FB_A
PL13A*
PL13B*
PL14A
PL14B
PL16A
PL16B
PL17A*
PL17B*
PL19A*
PL19B*
PL20A
PL20B
PL21A*
PL21B*
PL22A
PL22B
PL23A*
PL23B*
PL24A
PL24B
PL25A*
PL25B*
PL26A
PL26B
PL28A*/LUM1_SPLLT_IN_A
PL28B*/LUM1_SPLLC_IN_A
PL29A/LUM1_SPLLT_FB_A
PL29B/LUM1_SPLLC_FB_A
PL30A*
PL30B*
PL31A
PL31B
PL32A*
PL32B*
PL33A
PL33B
PL34A*
PL34B*
PL35A/PCLKT7_0
PL35B/PCLKC7_0
U1D
Bank0
A
3
Bank1
4
P3
P2
P5
N6
P4
R3
P6
N7
P1
R1
N8
R5
T3
T4
P8
R6
T1
U1
R7
T5
U3
U4
U5
U6
U2
V1
W2
V2
V4
V3
W4
W3
W1
Y1
AA1
AB1
U7
V6
W5
Y4
U8
W6
Y3
AA3
V7
Y5
AB2
AA4
Y6
U9
AA5
AA6
Y7
V9
TestArray45
TestArray46
TestArray47
TestArray48
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
SWITCH6
SWITCH7
SWITCH8
RED1
YELLOW1
GREEN1
BLUE1
RED2
YELLOW2
GREEN2
BLUE2
TestArray41
TestArray42
TestArray43
TestArray44
7
7
2_5V
2
RN18E
Q12
2N2222/SOT23
LED-SMT1206_BLUE
D21
GREEN2
Title
YELLOW2
470R
7
10 RN19G
EXB2HV471JV
D a te :
1
S he e t
R173
680R-0603SMT
R172
680R-0603SMT
R171
680R-0603SMT
R170
680R-0603SMT
R169
680R-0603SMT
R168
680R-0603SMT
R167
680R-0603SMT
R166
680R-0603SMT
10
LED-SMT1206_BLUE
D22
SC PCI EXPRESS Card
P roje c t
FPGA TEST
BLUE2
RED2
470R
5
12 RN19E
EXB2HV471JV
470R
6
11 RN19F
EXB2HV471JV
RED1
BLUE1
S iz e
C
RN18H
LED-SMT1206_GREEN
D20
Q13
2N2222/SOT23
12_0V
470R-1206SMT
R165
8
91
EXB2HV103JV
10K
GREEN1
470R
RN18F
LED-SMT1206_YELLOW
D18
Q11
2N2222/SOT23
12_0V
470R-1206SMT
R163
1
6
11
EXB2HV103JV
10K
470R
4
13 RN19D
EXB2HV471JV
8
9 RN19H
EXB2HV471JV
RN18D
LED-SMT1206_RED
D15
Q9
2N2222/SOT23
12_0V
470R-1206SMT
R161
4
13
1
EXB2HV103JV
10K
470R
3
14 RN19C
EXB2HV471JV
470R
RN18B
Q7
2N2222/SOT23
12_0V
1
470R-1206SMT
R159
2
15
1
EXB2HV103JV
10K
YELLOW1
BLUE2
GREEN2
YELLOW2
RED2
470R
2
15 RN19B
EXB2HV471JV
1
16 RN19A
EXB2HV471JV
RN18G
7
10
1
EXB2HV103JV
10K
LED-SMT1206_GREEN
D19
Q10
2N2222/SOT23
12_0V
470R-1206SMT
R164
5
12
1
EXB2HV103JV
10K
LED-SMT1206_YELLOW
D17
Q8
2N2222/SOT23
12_0V
470R-1206SMT
R162
3
14
1
EXB2HV103JV
10K
RN18C
LED-SMT1206_RED
D16
Q6
2N2222/SOT23
12_0V
470R-1206SMT
R160
16
1
1
EXB2HV103JV
10K
RN18A
1
SW6A
SWITCH4
3
SW6B
SWITCH3
12
4
SW6C
SWITCH2
10
R158
12_0V
470R-1206SMT
1
SW5A
SWITCH8
3
SW5B
SWITCH7
12
4
SW5C
SWITCH6
10
BLUE1
GREEN1
YELLOW1
6
SW6D
SWITCH1
9
2
RED1
6
SW5D
SWITCH5
9
OSC_IN_3 [8]
OSC_IN_4 [8]
LS_PCLK_CLKP [8]
LS_PCLK_CLKN [8]
1
0
5
1
0
8
1
0
8
5
1
0
5
1
0
1
0
11
1
0
11
2
1
0
R
3
2
Y
3
2
G
3
2
B
3
2
R
3
2
Y
3
2
G
3
2
B
3
2
24
2
of
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 14. FPGA Test
25
A
B
C
D
5
5
VDDTX
VDDRX
VDDP
VDDOB
VDDIB
VCC CORE
C236
C237
C238
C239
C240
C241
C242
C246
C247
C258
C251
C261
C252
C277
C278
22PF-0402SMT
C267
C279
3_3V
1000PF-0402SMT
C268
C285
C286
C287
MH2
M HOLE2
MH1
M HOLE2
M HOLE2
MH3
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C284
VDDTX
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C276
VDDRX
1000PF-0402SMT
C266
VDDP
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C250
VDDOB
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C245
VDDIB
4
VDDAUX33
22PF-0402SMT
C269
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C235
VCC_CORE
4
ecp2m-672fpbga
VSS
U1K
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
A13
A19
A2
A25
AA2
AA25
AB18
AB22
AB5
AB9
AE1
AE11
AE16
AE22
AE26
AE6
AF13
AF19
AF2
AF25
B1
B11
B16
B22
B26
B6
E18
E22
E5
E9
F2
F25
G11
G16
J22
J5
K11
K13
K14
K16
L10
L11
L16
L17
L2
L20
L25
L7
M13
M14
N10
N12
N13
N14
N15
N17
P10
P12
P13
P14
P15
P17
R13
R14
T10
T11
T16
T17
T2
T20
T25
T7
U11
U13
U14
U16
V22
V5
Y11
Y16
ALL CAPS PLACED UNDER BGA
3
VCCIO5
VCCIO7
VCCIO6
VCCIO4
VCCIO3
VCCIO2
VCCIO1
VCCAUX
1_8V
2_5V
2_5V
2_5V
2_5V
2_5V
2_5V
2_5V
C254
C243
C255
C244
C256
C257
C259
C249
C260
C263
C264
C265
C271
C272
C273
C274
C275
C281
C282
C283
C289
C290
C291
C292
C294
C295
C296
C297
C299
C300
C301
C302
2
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C298
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C293
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C288
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C280
D a te :
S iz e
C
Title
1
1
SC PCI EXPRESS Card
P roje c t
VSS/Decoupling
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C270
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C262
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C248
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C253
2
S he e t
11
of
11
R ev
1.0
A
B
C
D
Lattice Semiconductor
LatticeECP2M SERDES
Evaluation Board User’s Guide
Figure 15. VSS/Decoupling