doc4158

Features
• Operating Voltage: 3.3V
• Access Time: 40 ns
• Very Low Power Consumption
•
•
•
•
•
•
•
•
– Active: 160 mW (Max)
– Standby: 70 µW (Typ)
Wide Temperature Range: -55⋅°C to +125⋅°C
MFP 32 leads 400 Mils Width Package
TTL Compatible Inputs and Outputs
Asynchronous
Designed on 0.35µm Process
No Single Event Latch-up below a LET threshold of 80 [email protected] °C
Radiation Tolerance(1)
– Tested up to a Total Dose of 300 krad (Si)
– RHA capability of 100 krad (Si) according to MIL STD 883 Method 1019
Quality grades: QML Q or V with SMD 5962-02501
Notes:
1. tolerance to MBU’s may need to be enhanced by the application
Description
Rad Hard
128K x 8
3.3-volt
Very Low Power
CMOS SRAM
The M65609E is a very low power CMOS static RAM organized as 131,072 x 8 bits.
Utilizing an array of six transistors (6T) memory cells, the M65609E combines an
extremely low standby supply current with a fast access time at 40 ns. The high stability of the 6T cell provides excellent protection against soft errors due to noise.
M65609E
The M65609E is processed according to the methods of the latest revision of the MIL
PRF 38535 and ESCC 9000.
It is produced on the same process as the MH1RT sea of gates series.
4158J–AERO–11/13
Block Diagram
I/O7
GND
1024 ROWS
I/O0
Vcc
COLUMN DECODER
A5
A6
A7
A8
A9
A11
A13
A14
A15
A16
MEMORY ARRAY
1024x128x8
INPUT
DATA
CIRCUIT
128 COLUMNS
COLUMN DECODER
A0
A1
A2
A3
A4
A10
A12
CS1
OE
WE
CONTROL
CIRCUIT
CS2
Pin Assignment
Figure 1. 32 pins Flatpack 400 MILS
2
M65609E
4158J–AERO–11/13
M65609E
Pin Description
Name
Description
A0 - A16
Address Inputs
I/O1 - I/O8
Data Input/Output
CS1
Chip Select 1
CS2
Chip Select 2
WE
Write Enable
OE
Output Enable
VCC
Power
GND
Ground
Table 1. Truth Table
CS1
CS2
WE
OE
Inputs/
Outputs
H
X
X
X
Z
Deselect/ Power-down
X
L
X
X
Z
Deselect/ Power-down
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
H
H
H
Z
L
Note:
Mode
Output Disable
L = low, H = high, X = H or L, Z = high impedance.
3
4158J–AERO–11/13
Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage to GND Potential............................ -0.5V + 5V
*NOTE:
DC Input Voltage............................ GND - 0.3V to VCC + 0.3V
DC Output Voltage High Z State .... GND - 0.3V to VCC + 0.3V
Storage Temperature ......................................-65⋅C to + 150⋅C
Output Current Into Outputs (Low) ............................... 20 mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
Electro Statics Discharge Voltage................................. > 500V
(MIL STD 883D Method 3015.3)
Military Operating Range
Operating Voltage
Operating Temperature
3.3V + 0.3V
-55⋅C to + 125⋅C
Recommended DC Operating Conditions
Parameter
Description
VCC
Supply voltage
Gnd
Ground
Min
Typ
Max
Unit
3
3.3
3.6
V
0.0
0.0
0.0
V
VIL
Input low voltage
GND - 0.3
0.0
0.8
V
VIH
Input high voltage
2.2
–
VCC + 0.3
V
Description
Min
Typ
Max
Unit
Input low voltage
–
–
8
pF
Output high voltage
–
–
8
pF
Capacitance
Parameter
CIN(1)
COUT(1)
Note:
4
1. Guaranteed but not tested.
M65609E
4158J–AERO–11/13
M65609E
DC Parameters
DC Test Conditions
Parameter
IIX
(1)
IOZ (1)
1.
2.
3.
Description
Minimum
Typical
Maximum
Unit
Input leakage
current
-1
–
1
µA
Output leakage
current
-1
–
1
µA
VOL
(2)
Output low voltage
-
–
0.4
V
VOH
(3)
Output high voltage
2.4
–
–
V
Gnd < Vin < VCC, Gnd < Vout < VCC Output Disabled.
VCC min. IOL = 4 mA.
VCC min. IOH = -2 mA.
Consumption
1.
2.
3.
Symbol
Description
65609E-40
Unit
Value
ICCSB (1)
Standby supply current
1.5
mA
max
ICCSB1 (2)
Standby supply current
1
mA
max
ICCOP (3)
Dynamic operating
current
45
mA
max
CS1 > VIH or CS2 < VIL and CS1 < VIL.
CS1 > VCC - 0.3V or, CS2 < Gnd + 0.3V and CS1 < 0.2V
F = 1/TAVAV, IOUT = 0 mA, W = OE = VIH, Vin = Gnd or VCC, VCC max.
5
4158J–AERO–11/13
AC Parameters
Test Conditions
Temperature Range................................................................................................. -55 +125 °C
Supply Voltage: ........................................................................................................... 3.3 +0.3V
Input and Output Timing Reference Levels ......................................................................... 1.5V
Test Loads and Waveforms
Figure 2. Test Loads
View A
View B
R1 2552
3.3V
3.3V
R1 2552
2824
2824
1340
V
V
Figure 3. CMOS Input Pulses
6
M65609E
4158J–AERO–11/13
M65609E
Data Retention Mode
Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention:
1. During data retention CS1 must be held high within VCC to VCC - 0.2V or chip select CS2
must be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation.
3. During power-up and power-down transitions CS1 and OE must be kept between VCC +
0.3V and 70% of VCC, or with BS between GND and GND -0.3V.
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages
(3V).
Figure 4. Data Retention Timing
Data Retention Characteristics
Parameter
Description
Min
Typical TA = 25⋅C
Max
Unit
VCCDR
VCC for data retention
2.0
–
–
V
TCDR
Chip deselect to data retention time
0.0
–
–
ns
tR
Operation recovery time
tAVAV(1)
–
–
ns
ICCDR1(2)
Data retention current at 2.0V
–
0.010
1.0
mA
Notes:
1. TAVAV = Read Cycle Time
2. CS1 = VCC or CS2 = CS1 = GND, VIN = GND/VCC.
7
4158J–AERO–11/13
Write Cycle
Symbol
Note:
Write Cycle 1
8
Parameter
65609E-40
Unit
Value
tAVAW
Write cycle time
35
ns
min
tAVWL
Address set-up time
0
ns
min
tAVWH
Address valid to end of write
28
ns
min
tDVWH
Data set-up time
18
ns
min
tE1LWH
CS1 low to write end
28
ns
min
tE2HWH
CS2 high to write end
28
ns
min
tWLQZ
Write low to high Z (1)
15
ns
max
tWLWH
Write pulse width
28
ns
min
tWHAX
Address hold from to end of write
3
ns
min
tWHDX
Data hold time
0
ns
min
tWHQX
Write high to low Z (1)
0
ns
min
1. Parameters guaranteed, not tested, with 5 pF output loading (see view B on Figure 2 on page
6 ).
WE Controlled. OE High During Write
M65609E
4158J–AERO–11/13
M65609E
Write Cycle 2
WE Controlled. OE Low
Write Cycle 3.
CS1 or CS2 Controlled(1)
Note:
1. The internal write time of the memory is defined by the overlap of CS1 LOW and CS2 HIGH
and W LOW. Both signals must be activated to initiate a write and either signal can terminate a
write by going in activated. The data input setup and hold timing should be referenced to the
actived edge of the signal that terminates the write. Data out is high impedance if OE = VIH.
9
4158J–AERO–11/13
Read Cycle
Symbol
Note:
Parameter
65609E-40
Unit
Value
tAVAV
Read cycle time
40
ns
min
tAVQV
Address access time
40
ns
max
tAVQX
Address valid to low Z
3
ns
min
tE1LQV
Chip-select1 access time
40
ns
max
tE1LQX
CS1 low to low Z (1)
3
ns
min
tE1HQZ
CS1 high to high Z (1)
15
ns
max
tE2HQV
Chip-select2 access time
40
ns
max
tE2HQX
CS2 high to low Z (1)
3
ns
min
tE2LQZ
CS2 low to high Z (1)
15
ns
max
tGLQV
Output Enable access time
12
ns
max
tGLQX
OE low to low Z (1)
0
ns
min
tGHQZ
OE high to high Z (1)
10
ns
max
1. Parameters guaranteed, not tested, with 5 pF output loading (see view B on Figure 2 on page
6).
Read Cycle 1
10
M65609E
4158J–AERO–11/13
M65609E
Read Cycle 2
Read Cycle 3
11
4158J–AERO–11/13
Ordering Information
Part Number
MMDJ-65609EV-40-E
Temperature Range
Speed
Package
Flow
25 °C
40 ns
FP32.4
Engineering Samples
5962-0250101QXC
-55 to +125 °C
40 ns
FP32.4
QML Q
5962-0250101VXC
-55 to +125 °C
40 ns
FP32.4
QML V
5962R0250101VXC
-55 to +125 °C
40 ns
FP32.4
QML V RHA
SMDJ-65609EV-40SCC
-55 to +125° C
40 ns
FP32.4
ESCC
MM0 -65609EV-40-E(1)
25 °C
40 ns
Die
Engineering Samples
MM0 -65609EV-40SV(1)
-55 to +125 °C
40 ns
Die
QML V
Note:
12
1. Contact Atmel for availability.
M65609E
4158J–AERO–11/13
M65609E
Package Drawing
32-pin Flat Pack (400 Mils)
13
4158J–AERO–11/13
Document Revision History
Changes from Rev. I to Rev. J
Add-on: MBU’s note in features section
Update: radiation tolerance specification in features section
Update: block diagram
Update: AC test conditions section
Update: package drawing
14
M65609E
4158J–AERO–11/13
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4158J–AERO–11/13
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