IPD50R399CP CoolMOSTM Power Transistor Product Summary Features • Lowest figure of merit RON x Qg • Ultra low gate charge VDS @Tjmax 550 V RDS(on),max 0.399 17 nC Qg,typ • Extreme dv/dt rated • High peak current capability • Pb-free lead plating; RoHS compliant • Quailfied according to JEDEC1) for target applications PG-TO252 CoolMOS CP is designed for: • Hard and softswitching SMPS topologies • DCM PFC for Lamp Ballast • PWM for Lamp Ballast & PDP and LCD TV Type Package Marking IPD50R399CP PG-TO252 5R399P Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value T C=25 °C 9 T C=100 °C 6 Pulsed drain current2) I D,pulse T C=25 °C 20 Avalanche energy, single pulse E AS I D=3.3 A, V DD=50 V 215 Avalanche energy, repetitive t AR2),3) E AR I D=3.3 A, V DD=50 V 0.33 Avalanche current, repetitive t AR2),3) I AR MOSFET dv /dt ruggedness dv /dt Gate source voltage V GS Power dissipation P tot Operating and storage temperature T j, T stg Rev. 2.0 Unit A mJ 3.3 A V DS=0...400 V 50 V/ns static ±20 V AC (f>1 Hz) ±30 T C=25 °C 83 W -55 ... 150 °C page 1 2007-11-21 IPD50R399CP Maximum ratings, at T j=25 °C, unless otherwise specified Value Parameter Symbol Conditions Unit Continuous diode forward current IS Diode pulse current2) I S,pulse 20 Reverse diode dv /dt 4) dv /dt 15 V/ns Parameter Symbol Conditions Values Unit 4.9 T C=25 °C A min. typ. max. - - 1.5 Thermal characteristics K/W Thermal resistance, junction - case R thJC Thermal resistance, junction ambient R thJA leaded - - 62 Soldering temperature, reflowsoldering T sold 1.6 mm (0.063 in.) from case for 10 s - - 260 °C 500 - - V Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V V, I D=250 µA Gate threshold voltage V GS(th) V DS=V GS, I D=0.33 mA 2.5 3 3.5 Zero gate voltage drain current I DSS V DS=500 V, V GS=0 V, T j=25 °C - - 1 V DS=500 V, V GS=0 V, T j=150 °C - 10 - µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - - 100 nA Drain-source on-state resistance R DS(on) V GS=10 V, I D=4.9 A, T j=25 °C - 0.36 0.399 V GS=10 V, I D=4.9 A, T j=150 °C - 0.90 - f =1 MHz, open drain - 2.2 - Gate resistance Rev. 2.0 RG page 2 2007-11-21 IPD50R399CP Parameter Values Symbol Conditions Unit min. typ. max. - 890 - - 40 - - 38 - Dynamic characteristics Input capacitance C iss Output capacitance C oss Effective output capacitance, energy C o(er) related6) V GS=0 V, V DS=100 V, f =1 MHz pF V GS=0 V, V DS=0 V to 400 V Effective output capacitance, time related7) C o(tr) - 81 - Turn-on delay time t d(on) - 35 - Rise time tr - 14 - Turn-off delay time t d(off) - 80 - Fall time tf - 14 - Gate to source charge Q gs - 4 - Gate to drain charge Q gd - 6 - Gate charge total Qg - 17 23 Gate plateau voltage V plateau - 5.2 - V - 0.9 1.2 V - 260 - ns - 1.9 - µC - 12.2 - A V DD=400 V, V GS=10 V, I D=4.9 A, R G=35.1 ns Gate Charge Characteristics V DD=400 V V, I D=4.9 =4 9 A A, V GS=0 to 10 V nC Reverse Diode Diode forward voltage V SD Reverse recovery time t rr Reverse recovery charge Q rr Peak reverse recovery current I rrm V GS=0 V, I F=4.9 A, T j=25 °C V R=400 V, I F=I S, di F/dt =100 A/µs 1) J-STD20 and JESD22 2) Pulse width t p limited by T j,max 3) Repetitive avalanche causes additional power losses that can be calculated as P AV=E AR*f. 4) I SD≤I D, di /dt ≤400A/µs, V DClink=400V, V peak<V (BR)DSS, T j<T jmax, identical low and high side switch 5) Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70mm thick) copper area for drain connection. PCB without blown air. 6) C o(er) is a fixed capacitance that gives the same stored energy as C oss while V DS is rising from 0 to 80% V DSS. 7) C o(tr) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Rev. 2.0 page 3 2007-11-21 IPD50R399CP 1 Power dissipation 2 Safe operating area P tot=f(T C) I D=f(V DS); T C=25 °C; D =0 parameter: t p 160 102 140 1 µs limited by on-state resistance 10 µs 120 100 µs 101 1 ms 10 ms ID [A] Ptot [W] 100 80 DC 60 100 40 20 10-1 0 0 25 50 75 100 125 150 100 175 101 TC [°C] 102 103 VDS [V] 3 Max. transient thermal impedance 4 Typ. output characteristics Z(thJC)=f(tp); I D=f(V DS); T j=25 °C parameter: D=t p/T parameter: V GS 101 60 20 V 10 V 50 8V 7V 100 40 ZthJC [K/W] 0.5 ID [A] 0.2 0.1 30 6V 0.05 10-1 0.02 20 5.5 V 0.01 single pulse 5V 10 4.5 V 10-2 0 10-5 10-4 10-3 10-2 10-1 100 tp [s] Rev. 2.0 0 5 10 15 20 VDS [V] page 4 2007-11-21 IPD50R399CP 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D=f(V DS); T j=150 °C R DS(on)=f(I D); T j=150 °C parameter: V GS parameter: V GS 1 40 6V 5.5 V 20 V 6.5 V 0.9 10 V 30 0.8 8V 7V 6V 20 RDS(on) [] ID [A] 0.7 5.5 V 10 V 7V 0.6 0.5 5V 0.4 10 4.5 V 0.3 0.2 0 0 5 10 15 20 0 25 5 10 15 VDS [V] 20 25 30 35 ID [A] 7 Drain-source on-state resistance 8 Typ. transfer characteristics R DS(on)=f(T j); I D=4.9 A; V GS=10 V I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 0.6 30 25 °C 0.5 25 20 98 % typ ID [A] RDS(on) [] 0.4 0.3 150 °C 15 0.2 10 0.1 5 0 0 -60 -20 20 60 100 140 180 Tj [°C] Rev. 2.0 0 2 4 6 8 10 VGS [V] page 5 2007-11-21 IPD50R399CP 9 Typ. gate charge 10 Forward characteristics of reverse diode V GS=f(Q gate); I D=4.9 A pulsed I F=f(V SD) parameter: V DD parameter: T j 102 10 25 °C, 98% 100 V 8 150 °C, 98% 400 V 150 °C 101 25 °C VGS [V] IF [A] 6 4 100 2 10-1 0 0 0 5 10 15 0.5 1 20 1.5 2 VSD [V] Qgate [nC] 11 Avalanche energy 12 Drain-source breakdown voltage E AS=f(T j); I D=3.3 A; V DD=50 V V BR(DSS)=f(T j); I D=0.25 mA 580 450 400 560 350 540 VBR(DSS) [V] EAS [mJ] 300 250 200 520 500 150 480 100 460 50 440 0 25 75 125 175 Tj [°C] Rev. 2.0 -60 -20 20 60 100 140 180 Tj [°C] page 6 2007-11-21 IPD50R399CP 13 Typ. capacitances 14 Typ. Coss stored energy C =f(V DS); V GS=0 V; f =1 MHz E oss= f(V DS) 5 104 Ciss 4 103 3 Eoss [µJ] C [pF] Coss 102 2 101 1 Crss 100 0 0 100 200 300 400 500 VDS [V] Rev. 2.0 0 100 200 300 400 500 VDS [V] page 7 2007-11-21 IPD50R399CP Definition of diode switching characteristics Rev. 2.0 page 8 2007-11-21 IPD50R399CP PG-TO252-3-1/PG-TO252-3-11/PG-TO252-3-21: Outline Rev. 2.0 page 9 2007-11-21 IPD50R399CP Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 2.0 page 10 2007-11-21