LH7A400 32-Bit System-on-Chip Preliminary data sheet FEATURES • Three Programmable Timers • 32-bit ARM9TDMI™ RISC Core – 16 kB Cache: 8 kB Instruction and 8 kB Data – MMU (Windows CE™ Enabled) – Up to 250 MHz; see Table 1 for options • Three UARTs – Classic IrDA (115 kbit/s) • Smart Card Interface (ISO7816) • Two DC-to-DC Converters • MultiMediaCard™ Interface • AC97 Codec Interface • Smart Battery Monitor Interface • Real Time Clock (RTC) • Up to 60 General Purpose I/Os • Watchdog Timer • JTAG Debug Interface and Boundary Scan • Operating Voltage – 1.8 V Core – 3.3 V Input/Output • 80 kB On-Chip Static RAM • Programmable Interrupt Controller • External Bus Interface – Up to 125 MHz; see Table 1 for options – Asynchronous SRAM/ROM/Flash – Synchronous DRAM/Flash – PCMCIA – CompactFlash • Clock and Power Management – 32.768 kHz and 14.7456 MHz Oscillators – Programmable PLL • Programmable LCD Controller – Up to 1,024 × 768 Resolution – Supports STN, Color STN, AD-TFT, HR-TFT, TFT – Up to 64 k-Colors and 15 Gray Shades • 5 V Tolerant Digital Inputs (except oscillator pins) – Oscillator pins P15, P16, R13, and T13 are 1.8 V ± 10 %. • Operating Temperature: −40°C to +85°C • 256-ball BGA or 256-ball LFBGA Package • DMA (10 Channels) – AC97 – MMC – USB DESCRIPTION • USB Device Interface (USB 2.0, Full Speed) • Synchronous Serial Port (SSP) – Motorola SPI™ – Texas Instruments SSI – National MICROWIRE™ The LH7A400, powered by an ARM922T, is a complete System-on-Chip with a high level of integration to satisfy a wide range of requirements and expectations. This high degree of integration lowers overall system costs, reduces development cycle time and accelerates product introduction. Table 1. LH7A400 versions CORE CLOCK BUS CLOCK LOW POWER CURRENT BY MODE (TYP.) TEMP. RANGE LH7A400N0F076B5 250 MHz/ 245 MHz 125 MHz Run = 250 mA; Halt = 50 mA; Standby = 129 µA −40°C to +85°C LH7A400N0F000B3A 200 MHz/ 195 MHz 100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA LH7A400N0F000B5 200 MHz/ 195 MHz 100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA LH7A400N0G000B5 200 MHz/ 195 MHz 100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA PART NUMBER Preliminary data sheet 0°C to +70°C/ 0°C to +70°C/ −40°C to +85°C 0°C to +70°C/ −40°C to +85°C 0°C to +70°C/ −40°C to +85°C 1 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 2. Ordering information Package Type number Version Name Description LH7A400N0G000B5 BGA256 plastic ball grid array package; 256 balls SOT1018-1 LH7A400N0F000B3A LFBGA256 plastic low profile fine-pitch ball grid array package; 256 balls SOT1020-1 LH7A400N0F000B5 LFBGA256 plastic low profile fine-pitch ball grid array package; 256 balls SOT1020-1 LH7A400N0F076B5 LFBGA256 plastic low profile fine-pitch ball grid array package; 256 balls SOT1020-1 2 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors LH7A400 14.7456 MHz 32.768 kHz OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET CONTROL WATCHDOG TIMER TIMER (3) ARM922T INTERRUPT CONTROLLER STATIC (ASYNCHRONOUS) MEMORY CONTROLLER (SMC) EXTERNAL BUS INTERFACE REAL TIME CLOCK ADVANCED PERIPHERAL BUS BRIDGE GENERAL PURPOSE I/O (60) SYNCHRONOUS SERIAL PORT PCMCIA/CF CONTROLLER BATTERY MONITOR INTERFACE SYNCHRONOUS DYNAMIC RAM CONTROLLER (SDMC) UART (3) LCD AHB BUS IrDA INTERFACE USB DEVICE INTERFACE 80KB SRAM COLOR LCD CONTROLLER DMA CONTROLLER MULTIMEDIACARD INTERFACE ADVANCED AUDIO CODEC (AC97) ADVANCED LCD INTERFACE AUDIO CODEC INTERFACE ADVANCED HIGH-PERFORMANCE BUS (AHB) ADVANCED PERPHERAL BUS (APB) SMART CARD INTERFACE (ISO7816) DC to DC INTERFACE (2) LH7A400-1 Figure 1. LH7A400 block diagram Preliminary data sheet Rev. 01 — 16 July 2007 3 LH7A400 32-Bit System-on-Chip NXP Semiconductors LH7A400 ball A1 index area 2 1 4 3 6 5 8 7 10 12 9 11 14 13 16 15 A B C D E F G H J K L M N P R T 002aad223 Transparent top view Figure 2. Pin configuration (BGA256) LH7A400 ball A1 index area 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 A B C D E F G H J K L M N P R T 002aad224 Transparent top view Figure 3. Pin configuration (LFBGA256) 4 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors Table 3. Functional Pin List BGA PIN LFBGA PIN G7 C10 F1 F9 K7 F11 M1 F14 M5 G8 T6 H13 R14 J9 M14 K15 J11 L7 J12 N6 F13 N8 B14 N12 E10 N13 B8 P11 H7 B8 G3 C6 K4 D5 N5 D13 P6 E8 T14 F7 R16 G13 N16 H9 K13 J14 H9 K7 C15 L8 A11 L10 E8 L12 A5 M11 F7 M14 E1 C4 J4 D7 P3 D10 T8 F4 K9 F10 L13 J4 E15 J8 D12 K8 A7 L6 H5 G7 M3 H4 L9 H8 T10 L4 N15 L9 H12 N3 B15 N7 C9 N10 G6 R5 SIGNAL DESCRIPTION VDD I/O Ring Power VSS I/O Ring Ground VDDC Core Power VSSC Core Ground Preliminary data sheet Rev. 01 — 16 July 2007 RESET STATE STANDBY STATE OUTPUT I/O NOTES DRIVE 5 LH7A400 32-Bit System-on-Chip NXP Semiconductors Table 3. Functional Pin List (Cont’d) BGA PIN 6 LFBGA PIN R11 P12 N12 M10 P12 R13 T11 N11 D3 E4 SIGNAL DESCRIPTION VDDA Analog Power for PLL VSSA Analog Ground for PLL RESET STATE STANDBY STATE OUTPUT I/O NOTES DRIVE nPOR Power On Reset Input No Change I 3 Input No Change I 3 H6 D1 nURESET User Reset; should be pulled HIGH for normal or JTAG operation. D4 E2 WAKEUP Wake Up Input No Change I 3 E4 F2 nPWRFL Power Fail Signal Input No Change I 3 C2 D2 nEXTPWR External Power Input No Change I 3 14.7456 MHz Crystal Oscillator pins. An external clock source can be connected to XTALIN leaving XTALOUT open. Input No Change I HIGH HIGH O Input No Change I Output No Change O R13 R14 XTALIN T13 R15 XTALOUT P16 N14 XTAL32IN P15 M13 XTAL32OUT 32.768 kHz Real Time Clock Crystal Oscillator pins. An external clock source can be connected to XTAL32IN leaving XTAL32OUT open. P14 M12 CLKEN External Osc Clock Enable Output LOW LOW 8 mA J6 J5 PGMCLK Programmable Clock (14.7456 MHz MAX.) LOW LOW or HIGH 8 mA O K11 P14 nCS0 Async Memory Chip Select 0 HIGH No Change 12 mA O O K10 P16 nCS1 Async Memory Chip Select 1 HIGH No Change 12 mA O P13 N15 nCS2 Async Memory Chip Select 2 HIGH No Change 12 mA O M12 N16 nCS3/ nMMSPICS • Async Memory Chip Select 3 • MultiMediaCard SPI Mode Chip Select HIGH: nCS3 No Change 12 mA O Data Bus LOW LOW 12 mA I/O L12 L11 D0 M15 L13 D1 N13 L14 D2 L16 K11 D3 L15 L16 D4 L14 K14 D5 H11 J15 D6 K12 J12 D7 J15 J10 D8 J13 H16 D9 J10 H14 D10 H15 H11 D11 H13 G16 D12 G15 G9 D13 G11 G14 D14 G12 G12 D15 F15 F15 D16 F12 E15 D17 E14 D16 D18 D16 F12 D19 H10 E13 D20 D14 D14 D21 F10 E12 D22 A16 B16 D23 A14 D12 D24 B13 A16 D25 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors Table 3. Functional Pin List (Cont’d) BGA PIN LFBGA PIN RESET STATE STANDBY STATE Data Bus LOW LOW 12 mA I/O SIGNAL C13 B13 D26 E12 B14 D27 G10 C12 D28 B12 A14 D29 DESCRIPTION OUTPUT I/O NOTES DRIVE B11 B12 D30 D11 A12 D31 M16 M15 A0/nWE1 • Asynchronous Address Bus • Asynchronous Memory Write Byte Enable 1 HIGH: nWE1 HIGH 12 mA O N14 M16 A1/nWE2 • Asynchronous Address Bus • Asynchronous Memory Write Byte Enable 2 HIGH: nWE2 HIGH 12 mA O • Asynchronous Address Bus • Synchronous Address Bus LOW LOW 12 mA O M13 L15 A2/SA0 K16 K12 A3/SA1 K15 K13 A4/SA2 K14 K16 A5/SA3 J8 J13 A6/SA4 J16 J11 A7/SA5 J14 J16 A8/SA6 J9 H15 A9/SA7 H16 H10 A10/SA8 H14 H12 A11/SA9 G16 G15 A12/SA10 G14 G10 A13/SA11 G13 G11 A14/SA12 F16 F16 A15/SA13 F14 E16 A16/SB0 • Async Address Bus • Sync Device Bank Address 0 LOW LOW 12 mA O E16 F13 A17/SB1 • Async Address Bus • Sync Device Bank Address 1 LOW LOW 12 mA O Asynchronous Address Bus LOW LOW 12 mA O E13 E14 A18 F11 D15 A19 D15 C16 A20 C16 C15 A21 B16 C14 A22 A15 B15 A23 A13 E11 A24 G8 D8 A25/SCIO • Async Memory Address Bus • Smart Card Interface I/O (Data) LOW: A25 LOW 12 mA I/O F8 B7 A26/SCCLK • Async Memory Address Bus • Smart Card Interface Clock LOW: A26 LOW 12 mA I/O A8 A7 A27/SCRST • Async Memory Address Bus • Smart Card Interface Reset LOW: A27 LOW 12 mA O D8 C8 nOE Async Memory Output Enable HIGH No Change 12 mA O C8 F8 nWE0 Async Memory Write Byte Enable 0 HIGH No Change 12 mA O D10 D9 nWE3 Async Memory Write Byte Enable 3 HIGH No Change 8 mA O B10 E9 • Async Memory Chip Select 6 CS6/SCKE1_2 • Sync Memory Clock Enable 1 or 2 LOW: CS6 No Change 12 mA O C10 A10 CS7/SCKE0 • Async Memory Chip Select 7 • Sync Memory Clock Enable 0 LOW: CS7 No Change 12 mA O G9 A11 SCKE3 Sync Memory Clock Enable 3 LOW LOW 12 mA O A10 B10 SCLK Sync Memory Clock LOW No Change C14 C13 nSCS0 Sync Memory Chip Select 0 HIGH No Change Preliminary data sheet Rev. 01 — 16 July 2007 I/O 12 mA 2 O 7 LH7A400 32-Bit System-on-Chip NXP Semiconductors Table 3. Functional Pin List (Cont’d) BGA PIN 8 LFBGA PIN SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT I/O NOTES DRIVE D13 A15 nSCS1 Sync Memory Chip Select 1 HIGH No Change 12 mA O E11 D11 nSCS2 Sync Memory Chip Select 2 HIGH No Change 12 mA O A12 E10 nSCS3 Sync Memory Chip Select 3 HIGH No Change 12 mA O C12 A13 nSWE Sync Memory Write Enable HIGH No Change 12 mA O C11 B11 nCAS Sync Memory Column Address Strobe Signal HIGH No Change 12 mA O F9 C11 nRAS Sync Memory Row Address Strobe Signal HIGH No Change 12 mA O A9 C9 DQM0 Sync Memory Data Mask 0 HIGH No Change 12 mA O B9 A9 DQM1 Sync Memory Data Mask 1 HIGH No Change 12 mA O D9 B9 DQM2 Sync Memory Data Mask 2 HIGH No Change 12 mA O E9 A8 DQM3 Sync Memory Data Mask 3 HIGH No Change 12 mA O J5 K1 • GPIO Port A PA0/LCDVD16 • LCD Data bit 16. This CLCDC output signal is always LOW. Input: PA0 No Change 8 mA I/O K1 K2 • GPIO Port A PA1/LCDVD17 • LCD Data bit 17. This CLCDC output signal is always LOW. Input: PA1 No Change 8 mA I/O K2 K3 PA2 I/O K3 K4 PA3 I/O K5 K6 PA4 L1 K5 PA5 L2 L1 PA6 I/O L3 L2 PA7 I/O L4 L3 PB0/ UARTRX1 GPIO Port A Input • GPIO Port B • UART1 Receive Data Input No Change 8 mA I/O I/O Input: PB0 No Change 8 mA I/O 8 mA I/O L5 M1 PB1/UARTTX3 • GPIO Port B • UART3 Transmit Data Out Input: PB1 LOW if PINMUX: UART3CON = 1 (bit 3); otherwise No Change L7 M2 PB2/ UARTRX3 • GPIO Port B • UART3 Receive Data In Input: PB2 No Change 8 mA I/O M2 M3 PB3/ UARTCTS3 • GPIO Port B • UART3 Clear to Send Input: PB3 No Change 8 mA I/O M4 L5 PB4/ UARTDCD3 • GPIO Port B • UART3 Data Carrier Detect Input: PB4 No Change 8 mA I/O N1 N1 PB5/ UARTDSR3 • GPIO Port B • UART3 Data Set Ready Input: PB5 No Change 8 mA I/O N2 N2 PB6/SWID/ SMBD • GPIO Port B • Single Wire Data • Smart Battery Data Input: PB6 No Change 8 mA I/O N3 M4 PB7/ SMBCLK • GPIO Port B • Smart Battery Clock Input: PB7 No Change 8 mA I/O P1 P1 PC0/ UARTTX1 • GPIO Port C • UART1 Transmit Data Output LOW: PC0 No Change 12 mA I/O P2 P2 PC1/LCDPS • GPIO Port C • HR-TFT Power Save LOW: PC1 No Change 12 mA I/O R1 R1 PC2/ LCDVDDEN • GPIO Port C • HR-TFT Power Sequence Control LOW: PC2 No Change 12 mA I/O K6 M5 PC3/LCDREV • GPIO Port C • HR-TFT Gray Scale Voltage Reverse LOW: PC3 No Change 12 mA I/O L8 P3 PC4/ LCDSPS • GPIO Port C • HR-TFT Reset Row Driver Counter LOW: PC4 No Change 12 mA I/O Rev. 01 — 16 July 2007 7 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors Table 3. Functional Pin List (Cont’d) BGA PIN LFBGA PIN RESET STATE STANDBY STATE T1 N4 PC5/ LCDCLS • GPIO Port C • HR-TFT Row Driver Clock LOW: PC5 No Change 12 mA I/O T2 R2 PC6/LCDHRLP • GPIO Port C • LCD Latch Pulse LOW: PC6 No Change 12 mA I/O R2 N5 PC7/ LCDSPL • GPIO Port C • LCD Start Pulse Left LOW: PC7 No Change 12 mA I/O M11 M9 PD0/LCDVD8 LOW: PD0 SIGNAL DESCRIPTION L11 K10 PD1/LCDVD9 LOW: PD1 K8 P10 PD2/LCDVD10 LOW: PD2 N11 T11 LOW: PD3 R9 T12 PD3/LCDVD11 • GPIO Port D PD4/LCDVD12 • LCD Video Data Bus LOW: PD4 T9 R11 PD5/LCDVD13 LOW: PD5 P10 R12 PD6/LCDVD14 LOW: PD6 R10 T13 PD7/LCDVD15 LOW: PD7 L10 T9 PE0/LCDVD4 Input: PE0 N10 K9 PE1/LCDVD5 M9 T10 PE2/LCDVD6 M10 R10 PE3/LCDVD7 A6 A5 PF0/INT0 B6 B4 PF1/INT1 C6 E7 PF2/INT2 H8 B3 PF3/INT3 • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. C5 PF4/INT4/ SCVCCEN B5 D6 E6 OUTPUT I/O NOTES DRIVE I/O I/O LOW if PINMUX: PDOCON = 1 (bit 1); otherwise, No Change I/O 12 mA I/O I/O I/O I/O I/O I/O LOW if PINMUX: PDOCON or PEOCON = 1 (bits [1:0]); otherwise No Change 12 mA Input: PF0 No Change 8 mA I/O 3 Input: PF1 No Change 8 mA I/O 3 Input: PF2 No Change 8 mA I/O 3 Input: PF3 No Change 8 mA I/O 3 • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • Smart Card Supply Voltage Enable Input: PF4 LOW if SCI is Enabled; otherwise No Change 8 mA I/O 3 D6 PF5/INT5/ SCDETECT • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • Smart Card Detection Input: PF5 No Change 8 mA I/O 3 A4 PF6/INT6/ PCRDY1 • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • Ready for Card 1 for PC Card (PCMCIA or CF) in single or dual card mode Input: PF6 No Change 8 mA I/O 3 Input: PF7 No Change 8 mA I/O 3 Input: PE1 • GPIO Port E • LCD Video Data Bus Input: PE2 Input: PE3 • GPIO Port F • External FIQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • GPIO Port F • External IRQ Interrupts. Interrupts can be level or edge triggered and are internally debounced. I/O I/O I/O C5 A3 PF7/INT7/ PCRDY2 • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • Ready for Card 2 for PC Card (PCMCIA or CF) in single or dual card mode R3 M6 PG0/nPCOE • GPIO Port G • Output Enable for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG0 No Change 8 mA I/O T3 T1 PG1/nPCWE • GPIO Port G • Write Enable for PC Card (PCMCIA or CF) in sin- LOW: PG1 gle or dual card mode No Change 8 mA I/O Preliminary data sheet Rev. 01 — 16 July 2007 9 LH7A400 32-Bit System-on-Chip NXP Semiconductors Table 3. Functional Pin List (Cont’d) BGA PIN LFBGA PIN L6 P4 M6 N6 M7 DESCRIPTION RESET STATE STANDBY STATE PG2/ nPCIOR • GPIO Port G • I/O Read Strobe for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG2 No Change 8 mA I/O R3 PG3/ nPCIOW • GPIO Port G • I/O Write Strobe for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG3 No Change 8 mA I/O T2 PG4/nPCREG • GPIO Port G • Register Memory Access for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG4 No Change 8 mA I/O PG5/nPCCE1 • GPIO Port G • Card Enable 1 for PC Card (PCMCIA or CF) in single or dual card mode. This signal and nPCCE2 are used by the PC Card for decoding low and high byte accesses. LOW: PG5 No Change 8 mA I/O LOW: PG6 No Change 8 mA I/O P5 SIGNAL OUTPUT I/O NOTES DRIVE M8 R4 PG6/nPCCE2 • GPIO Port G • Card Enable 2 for PC Card (PCMCIA or CF) in single or dual card mode. This signal and nPCCE1 are used by the PC Card for decoding low and high byte accesses. N4 T3 PG7/PCDIR • GPIO Port G • Direction for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG7 No Change 8 mA I/O P4 P6 PH0/ PCRESET1 • GPIO Port H • Reset Card 1 for PC Card (PCMCIA or CF) in sin- Input: PH0 gle or dual card mode No Change 8 mA I/O R4 T4 PH1/CFA8/ PCRESET2 • GPIO Port H • Address Bit 8 for PC Card (CF) in single card mode Input: PH1 • Reset Card 2 for PC Card (PCMCIA or CF) in dual card mode No Change 8 mA I/O T4 M7 PH2/ nPCSLOTE1 • GPIO Port H • Enable Card 1 for PC Card (PCMCIA or CF) in sinInput: PH2 gle or dual card mode. This signal is used for gating other control signals to the appropriate PC Card. No Change 8 mA I/O Input: PH3 No Change 8 mA I/O N7 T5 PH3/CFA9/ PCMCIAA25/ nPCSLOTE2 • GPIO Port H • Address Bit 9 for PC Card (CF) in single card mode • Address Bit 25 for PC Card (PCMCIA) in single card mode • Enable Card 2 for PC Card (PCMCIA or CF) in dual card mode. This signal is used for gating other control signals to the appropriate PC Card. P8 R6 PH4/ nPCWAIT1 • GPIO Port H • WAIT Signal for Card 1 for PC Card (PCMCIA or CF) in single or dual card mode Input: PH4 No Change 8 mA I/O Input: PH5 No Change 8 mA I/O P5 R7 PH5/CFA10/ PCMCIAA24/ nPCWAIT2 • GPIO Port H • Address Bit 10 for PC Card (CF) in single card mode • Address Bit 24 for PC Card (PCMCIA) in single card mode • WAIT Signal for Card 2 for PC Card (PCMCIA or F) in dual card mode R5 P7 PH6/ nAC97RESET • GPIO Port H • Audio Codec (AC97) Reset Input: PH6 No Change 8 mA I/O T5 T6 PH7/ nPCSTATRE • GPIO Port H • Status Read Enable for PC Card (PCMCIA or F) in single or dual card mode Input: PH7 No Change 8 mA I/O R6 T7 LCDFP LCD Frame Synchronization pulse LOW LOW 12 mA O R8 R9 LCDLP LCD Line Synchronization pulse LOW LOW 12 mA O 10 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors Table 3. Functional Pin List (Cont’d) BGA PIN LFBGA PIN P9 P9 SIGNAL DESCRIPTION LCDENAB/ LCDM LCD TFT Data Enable LCD STN AC Bias LCD Data Clock N9 N9 LCDDCLK P7 M8 LCDVD0 R7 P8 LCDVD1 RESET STATE STANDBY STATE OUTPUT I/O NOTES DRIVE LOW: LCDENAB LOW 12 mA LOW LOW 12 mA O O O LCD Video Data Bus LOW LOW 12 mA O T7 R8 LCDVD2 N8 T8 LCDVD3 O T15 T16 USBDP USB Data Positive (Differential Pair) Input No Change I/O 10 T16 R16 USBDN USB Data Negative (Differential Pair) Input No Change I/O 10 E7 C7 nPWME0 • DC-DC Converter Pulse Width • Modulator 0 Enable Input No Change I D7 A6 nPWME1 • DC-DC Converter Pulse Width • Modulator 1 Enable Input No Change I C7 B6 PWM0 • DC-DC Converter Pulse Width • Modulator 0 Output during normal operation and Polarity Selection input at reset Input No Change 8 mA I/O B7 B5 PWM1 • DC-DC Converter Pulse Width • Modulator 1 Output during normal operation and Polarity Selection input at reset Input No Change 8 mA I/O C4 A2 ACBITCLK • Audio Codec (AC97) Clock • Audio Codec (ACI) Clock Input No Change 8 mA I/O D5 A1 ACOUT • Audio Codec (AC97) Output • Audio Codec (ACI) Output LOW No Change 8 mA O B4 B2 ACSYNC • Audio Codec (AC97) Synchronization • Audio Codec (ACI) Synchronization LOW No Change 8 mA O A4 E6 ACIN • Audio Codec (AC97) Input • Audio Codec (ACI) Input Input No Change A3 C3 MMCCLK/ MMSPICLK • MultiMediaCard Clock (20 MHz MAX.) • MultiMediaCard SPI Mode Clock LOW: MMCCLK LOW 8 mA O B3 B1 MMCCMD/ MMSPIDIN • MultiMediaCard Command • MultiMediaCard SPI Mode Data Input Input: MMCCMD Input 8 mA I/O A2 D4 MMCDATA/ MMSPIDOUT • MultiMediaCard Data • MultiMediaCard SPI Mode Data Output Input: MMCDATA Input 8 mA I/O E2 E1 UARTCTS2 • UART2 Clear to Send Signal. This pin is an output for JTAG boundary scan only. Input No Change I E3 F3 UARTDCD2 • UART2 Data Carrier Detect Signal. This pin is output for JTAG boundary scan only. Input No Change I E5 G4 UARTDSR2 UART2 Data Set Ready Signal Input No Change F2 G5 UARTIRTX1 IrDA Transmit LOW No Change F3 G6 UARTIRRX1 IrDA Receive. This pin is an output for JTAG boundary scan only. Input No Change F4 F1 UARTTX2 UART2 Transmit Data Output HIGH No Change Input No Change O I I 8 mA O I 8 mA O J7 G3 UARTRX2 UART2 Receive Data Input. This pin is an output for JTAG boundary scan only. H4 J3 SSPCLK Synchronous Serial Port Clock LOW No Change J1 J6 SSPRX Synchronous Serial Port Receive Input No Change J2 J7 SSPTX Synchronous Serial Port Transmit LOW LOW 8 mA I/O J2 SSPFRM/ nSSPFRM Synchronous Serial Port Frame Sync Input Input 8 mA I/O J3 Preliminary data sheet Rev. 01 — 16 July 2007 I 8 mA O I 11 LH7A400 32-Bit System-on-Chip NXP Semiconductors Table 3. Functional Pin List (Cont’d) BGA PIN LFBGA PIN RESET STATE STANDBY STATE F6 G2 F5 G1 COL1 G1 H3 COL2 G2 H5 COL3 G4 H6 COL4 Keyboard Interface HIGH HIGH 8 mA O G5 H7 COL5 H1 H2 COL6 H2 H1 COL7 H3 J1 TBUZ Timer Buzzer (254 kHz MAX.) LOW LOW 8 mA O Boot Device Media Change. Used with WIDTH0 and WIDTH1 to specify boot memory device. Input No Change I 3 Input No Change I 3 SIGNAL DESCRIPTION OUTPUT I/O NOTES DRIVE COL0 C3 F5 MEDCHG P11 T14 WIDTH0 R12 T15 WIDTH1 External Memory Width Pins. Also, used with MEDCHG to specify the boot memory device size. The pins must be pulled HIGH with a 33 kΩ resistor. D1 E3 BATOK Battery OK Input No Change I 3 D2 F6 nBATCHG Battery Change Input No Change I 3 A1 E5 TDI JTAG Data In. This signal is internally pulled-up t o VDD. Input No Change I 4 B1 C2 TCK JTAG Clock. This signal should be externally pulled-up to VDD with a 33 kΩ resistor. Input No Change I 3 B2 D3 TDO JTAG Data Out. This signal should be externally pulled up to VDD with a 33 kΩ resistor. High-Z No Change C1 C1 TMS JTAG Test Mode select. This signal is internally pulled-up to VDD. Input No Change I 4 T12 P15 nTEST0 Test Pin 0. Internally pulled up to VDD. For Normal mode, leave open. For JTAG mode, tie to GND. See Table 4. Input No Change I 4 nTEST1 Test Pin 1. internally pulled up to VDD. For Normal and JTAG mode, leave open. See Table 4. R15 P13 4 mA O 1. 2. 3. 4. 5. 6. 7. 8. 9. Signals beginning with ‘n’ are Active LOW. The SCLK pin can source up to 12 mA and sink up to 20 mA. See ‘DC Characteristics’. Schmitt trigger input; see ’DC Specifications’, page 31 for triggers points and hysteresis. Input only for JTAG boundary scan mode. Output only for JTAG boundary scan mode. The internal pullup and pull-down resistance on all digital I/O pins is 50 kΩ When used as SMBCLK, this pin must have a resistor. The RESET STATE is defined as the state during power-on reset. The STANDBY STATE is defined as the state when the device is in standby. During this state, I/O cells are forced to input (Input), output driving low (LOW), output driving high (HIGH), or their current state is preserved (No Change). In some case, function selection has an overall effect on the standby state. 10. All unused USB Device pins with a differential pair must be pulled to ground with a 15 kΩ resistor. Table 4. nTest Pin Function 12 MODE nTEST0 nTEST1 nURESET JTAG 0 1 1 Normal 1 1 x Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors Table 5. LCD Data Multiplexing STN BGA PIN LFBGA PIN LCD DATA SIGNAL MONO 4-BIT SINGLE PANEL MONO 8-BIT DUAL PANEL SINGLE PANEL DUAL PANEL COLOR SINGLE PANEL TFT DUAL PANEL AD-TFT/ HR-TFT K1 K2 LCDVD17 LOW J5 K1 LCDVD16 LOW R10 T13 LCDVD15 MLSTN7 CLSTN7 Intensity Intensity P10 R12 LCDVD14 MLSTN6 CLSTN6 BLUE4 BLUE4 T9 R11 LCDVD13 MLSTN5 CLSTN5 BLUE3 BLUE3 R9 T12 LCDVD12 MLSTN4 CLSTN4 BLUE2 BLUE2 N11 T11 LCDVD11 MLSTN3 CLSTN3 BLUE1 BLUE1 K8 P10 LCDVD10 MLSTN2 CLSTN2 BLUE0 BLUE0 L11 K10 LCDVD9 MLSTN1 CLSTN1 GREEN4 GREEN4 M11 M9 LCDVD8 MLSTN0 CLSTN0 GREEN3 GREEN3 M10 R10 LCDVD7 MLSTN3 MUSTN7 MUSTN7 CUSTN7 CUSTN7 GREEN2 GREEN2 M9 T10 LCDVD6 MLSTN2 MUSTN6 MUSTN6 CUSTN6 CUSTN6 GREEN1 GREEN1 N10 K9 LCDVD5 MLSTN1 MUSTN5 MUSTN5 CUSTN5 CUSTN5 GREEN0 GREEN0 L10 T9 LCDVD4 MLSTN0 MUSTN4 MUSTN4 CUSTN4 CUSTN4 RED4 RED4 N8 T8 LCDVD3 MUSTN3 MUSTN3 MUSTN3 MUSTN3 CUSTN3 CUSTN3 RED3 RED3 T7 R8 LCDVD2 MUSTN2 MUSTN2 MUSTN2 MUSTN2 CUSTN2 CUSTN2 RED2 RED2 R7 P8 LCDVD1 MUSTN1 MUSTN1 MUSTN1 MUSTN1 CUSTN1 CUSTN1 RED1 RED1 P7 M8 LCDVD0 MUSTN0 MUSTN0 MUSTN0 MUSTN0 CUSTN0 CUSTN0 RED0 RED0 Notes: 1. The Intensity bit is identically generated for all three colors. 2. MU = Monochrome Upper 3. CU = Color Upper 4. CL = Color Lower Preliminary data sheet Rev. 01 — 16 July 2007 13 LH7A400 Table 6. 256-Ball BGA Package Numerical Pin List BGA PIN 14 32-Bit System-on-Chip NXP Semiconductors SIGNAL Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) BGA PIN SIGNAL A1 TDI C14 nSCS0 A2 MMCDATA/MMSPIDOUT C15 VSS A3 MMCCLK/MMSPICLK C16 A21 A4 ACIN D1 BATOK A5 VSS D2 nBATCHG A6 PF0/INT0 D3 nPOR A7 VDDC D4 WAKEUP A8 A27/SCRST D5 ACOUT A9 DQM0 D6 PF5/INT5/SCDETECT A10 SCLK D7 nPWME1 A11 VSS D8 nOE A12 nSCS3 D9 DQM2 A13 A24 D10 nWE3 A14 D24 D11 D31 A15 A23 D12 VDDC A16 D23 D13 nSCS1 B1 TCK D14 D21 B2 TDO D15 A20 B3 MMCCMD/MMSPIDIN D16 D19 B4 ACSYNC E1 VDDC B5 PF4/INT4/SCVCCEN E2 UARTCTS2 B6 PF1/INT1 E3 UARTDCD2 B7 PWM1 E4 nPWRFL B8 VDD E5 UARTDSR2 B9 DQM1 E6 PF6/INT6/PCRDY1 B10 CS6/SCKE1_2 E7 nPWME0 B11 D30 E8 VSS B12 D29 E9 DQM3 B13 D25 E10 VDD B14 VDD E11 nSCS2 B15 VSSC E12 D27 B16 A22 E13 A18 C1 TMS E14 D18 C2 nEXTPWR E15 VDDC C3 MEDCHG E16 A17/SB1 C4 ACBITCLK F1 VDD C5 PF7/INT7/PCRDY2 F2 UARTIRTX1 C6 PF2/INT2 F3 UARTIRRX1 C7 PWM0 F4 UARTTX2 C8 nWE0 F5 COL1 C9 VSSC F6 COL0 C10 CS7/SCKE0 F7 VSS C11 nCAS F8 A26/SCCLK C12 nSWE F9 nRAS C13 D26 F10 D22 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) BGA PIN LH7A400 NXP Semiconductors SIGNAL Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) BGA PIN SIGNAL F11 A19 J8 A6/SA4 F12 D17 J9 A9/SA7 F13 VDD J10 D10 F14 A16/SB0 J11 VDD F15 D16 J12 VDD F16 A15/SA13 J13 D9 G1 COL2 J14 A8/SA6 G2 COL3 J15 D8 G3 VSS J16 A7/SA5 G4 COL4 K1 PA1/LCDVD17 G5 COL5 K2 PA2 G6 VSSC K3 PA3 G7 VDD K4 VSS G8 A25/SCIO K5 PA4 G9 SCKE3 K6 PC3/LCDREV G10 D28 K7 VDD G11 D14 K8 PD2/LCDVD10 G12 D15 K9 VDDC G13 A14/SA12 K10 nCS1 G14 A13/SA11 K11 nCS0 G15 D13 K12 D7 G16 A12/SA10 K13 VSS H1 COL6 K14 A5/SA3 H2 COL7 K15 A4/SA2 H3 TBUZ K16 H4 SSPCLK L1 PA5 H5 VSSC L2 PA6 H6 nURESET L3 PA7 H7 VSS L4 PB0/UARTRX1 H8 PF3/INT3 L5 PB1/UARTTX3 H9 VSS L6 PG2/nPCIOR H10 D20 L7 PB2/UARTRX3 H11 D6 L8 PC4/LCDSPS H12 VSSC L9 VSSC H13 D12 L10 PE0/LCDVD4 H14 A11/SA9 L11 PD1/LCDVD9 H15 D11 L12 D0 H16 A10/SA8 L13 VDDC J1 SSPRX L14 D5 J2 SSPTX L15 D4 J3 SSPFRM/nSSPFRM L16 D3 J4 VDDC M1 VDD J5 PA0/LCDVD16 M2 PB3/UARTCTS3 J6 PGMCLK M3 VSSC J7 UARTRX2 Preliminary data sheet Rev. 01 — 16 July 2007 A3/SA1 15 LH7A400 Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) BGA PIN Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) SIGNAL BGA PIN SIGNAL M4 PB4/UARTDCD3 P16 XTAL32IN M5 VDD R1 PC2/LCDVDDEN M6 PG3/nPCIOW R2 PC7/LCDSPL M7 PG5/nPCCE1 R3 PG0/nPCOE M8 PG6/nPCCE2 R4 PH1/CFA8/PCRESET2 M9 PE2/LCDVD6 R5 PH6/nAC97RESET M10 PE3/LCDVD7 R6 LCDFP M11 PD0/LCDVD8 R7 LCDVD1 M12 nCS3/nMMSPICS R8 LCDLP M13 A2/SA0 R9 PD4/LCDVD12 M14 VDD R10 PD7/LCDVD15 M15 D1 R11 VDDA M16 A0/nWE1 R12 WIDTH1 PB5/UARTDSR3 R13 XTALIN N2 PB6/SWID/SMBD R14 VDD N3 PB7/SMBCLK R15 nTEST1 N4 PG7/PCDIR R16 N5 VSS T1 PC5/LCDCLS N6 PG4/nPCREG T2 PC6/LCDHRLP N7 PH3/CFA9/PCMCIAA25/nPCSLOTE2 T3 PG1/nPCWE N8 LCDVD3 T4 PH2/nPCSLOTE1 N9 LCDDCLK T5 PH7/nPCSTATRE N10 PE1/LCDVD5 T6 VDD N11 PD3/LCDVD11 T7 LCDVD2 N12 VDDA T8 VDDC N13 D2 T9 PD5/LCDVD13 N14 A1/nWE2 T10 VSSC N15 VSSC T11 VSSA N16 VSS T12 nTEST0 PC0/UARTTX1 T13 XTALOUT P2 PC1/LCDPS T14 VSS P3 VDDC T15 USBDP P4 PH0/PCRESET1 T16 USBDN P5 PH5/CFA10/PCMCIAA24/nPCWAIT2 P6 VSS P7 LCDVD0 P8 PH4/nPCWAIT1 P9 LCDENAB/LCDM N1 P1 16 32-Bit System-on-Chip NXP Semiconductors P10 PD6/LCDVD14 P11 WIDTH0 P12 VSSA P13 nCS2 P14 CLKEN P15 XTAL32OUT Rev. 01 — 16 July 2007 VSS Preliminary data sheet 32-Bit System-on-Chip Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN LH7A400 NXP Semiconductors SIGNAL Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN SIGNAL A1 ACOUT C14 A22 A2 ACBITCLK C15 A21 A3 PF7/INT7/PCRDY2 C16 A20 A4 PF6/INT6/PCRDY1 D1 nURESET A5 PF0/INT0 D2 nEXTPWR A6 nPWME1 D3 TDO A7 A27/SCRST D4 MMCDATA/MMSPIDOUT A8 DQM3 D5 VSS A9 DQM1 D6 PF5/INT5/SCDETECT A10 CS7/SCKE0 D7 VDDC A11 SCKE3 D8 A25/SCIO A12 D31 D9 nWE3 A13 nSWE D10 VDDC A14 D29 D11 nSCS2 A15 nSCS1 D12 D24 A16 D25 D13 VSS B1 MMCCMD/MMSPIDIN D14 D21 B2 ACSYNC D15 A19 B3 PF3/INT3 D16 D18 B4 PF1/INT1 E1 B5 PWM1 E2 WAKEUP B6 PWM0 E3 BATOK B7 A26/SCCLK E4 nPOR B8 VSS E5 TDI UARTCTS2 B9 DQM2 E6 ACIN B10 SCLK E7 PF2/INT2 B11 nCAS E8 VSS B12 D30 E9 CS6/SCKE1_2 B13 D26 E10 nSCS3 B14 D27 E11 A24 B15 A23 E12 D22 B16 D23 E13 D20 C1 TMS E14 A18 C2 TCK E15 D17 C3 MMCCLK/MMSPICLK E16 C4 VDDC F1 C5 PF4/INT4/SCVCCEN F2 nPWRFL C6 VSS F3 UARTDCD2 C7 nPWME0 F4 VDDC C8 nOE F5 MEDCHG nBATCHG A16/SB0 UARTTX2 C9 DQM0 F6 C10 VDD F7 VSS C11 nRAS F8 nWE0 C12 D28 F9 VDD C13 nSCS0 Preliminary data sheet Rev. 01 — 16 July 2007 17 LH7A400 Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN SIGNAL Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN SIGNAL F10 VDDC J6 SSPRX F11 VDD J7 SSPTX F12 D19 J8 VDDC F13 A17/SB1 J9 VDD F14 VDD J10 D8 F15 D16 J11 A7/SA5 F16 A15/SA13 J12 D7 G1 COL1 J13 A6/SA4 G2 COL0 J14 VSS G3 UARTRX2 J15 D6 G4 UARTDSR2 J16 A8/SA6 G5 UARTIRTX1 K1 PA0/LCDVD16 G6 UARTIRRX1 K2 PA1/LCDVD17 G7 VSSC K3 PA2 G8 VDD K4 PA3 G9 D13 K5 PA5 G10 A13/SA11 K6 PA4 G11 A14/SA12 K7 VSS G12 D15 K8 VDDC G13 VSS K9 PE1/LCDVD5 G14 D14 K10 PD1/LCDVD9 G15 A12/SA10 K11 D3 G16 D12 K12 A3/SA1 H1 COL7 K13 A4/SA2 H2 COL6 K14 D5 H3 COL2 K15 VDD H4 VSSC K16 H5 COL3 L1 PA6 H6 COL4 L2 PA7 H7 COL5 L3 PB0/UARTRX1 H8 VSSC L4 VSSC H9 VSS L5 PB4/UARTDCD3 H10 A10/SA8 L6 VDDC H11 D11 L7 VDD H12 A11/SA9 L8 VSS H13 VDD L9 VSSC H14 D10 L10 VSS H15 A9/SA7 L11 D0 H16 18 32-Bit System-on-Chip NXP Semiconductors A5/SA3 D9 L12 VSS J1 TBUZ L13 D1 J2 SSPFRM/nSSPFRM L14 D2 J3 SSPCLK L15 A2/SA0 J4 VDDC L16 D4 J5 PGMCLK M1 PB1/UARTTX3 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN LH7A400 NXP Semiconductors SIGNAL Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN SIGNAL M2 PB2/UARTRX3 P14 nCS0 M3 PB3/UARTCTS3 P15 nTEST0 M4 PB7/SMBCLK P16 nCS1 M5 PC3/LCDREV R1 PC2/LCDVDDEN M6 PG0/nPCOE R2 PC6/LCDHRLP M7 PH2/nPCSLOTE1 R3 PG3/nPCIOW M8 LCDVD0 R4 PG6/nPCCE2 M9 PD0/LCDVD8 R5 VSSC M10 VDDA R6 PH4/nPCWAIT1 M11 VSS R7 PH5/CFA10/PCMCIAA24/nPCWAIT2 M12 CLKEN R8 LCDVD2 M13 XTAL32OUT R9 LCDLP M14 VSS R10 PE3/LCDVD7 M15 A0/nWE1 R11 PD5/LCDVD13 M16 A1/nWE2 R12 PD6/LCDVD14 PB5/UARTDSR3 R13 VSSA N2 PB6/SWID/SMBD R14 XTALIN N3 VSSC R15 XTALOUT N4 PC5/LCDCLS R16 USBDN N5 PC7/LCDSPL T1 PG1/nPCWE N6 VDD T2 PG4/nPCREG N7 VSSC T3 PG7/PCDIR N8 VDD T4 PH1/CFA8/PCRESET2 N9 LCDDCLK T5 PH3/CFA9/PCMCIAA25/nPCSLOTE2 N10 VSSC T6 PH7/nPCSTATRE N11 VSSA T7 LCDFP N12 VDD T8 LCDVD3 N13 VDD T9 PE0/LCDVD4 N14 XTAL32IN T10 PE2/LCDVD6 N15 nCS2 T11 PD3/LCDVD11 N1 N16 nCS3/nMMSPICS T12 PD4/LCDVD12 P1 PC0/UARTTX1 T13 PD7/LCDVD15 P2 PC1/LCDPS T14 WIDTH0 P3 PC4/LCDSPS T15 WIDTH1 P4 PG2/nPCIOR T16 USBDP P5 PG5/nPCCE1 P6 PH0/PCRESET1 P7 PH6/AC97RESET P8 LCDVD1 P9 LCDENAB/LCDM P10 PD2/LCDVD10 P11 VDD P12 VDDA P13 nTEST1 Preliminary data sheet Rev. 01 — 16 July 2007 19 LH7A400 32-Bit System-on-Chip NXP Semiconductors TOUCH SCREEN CONTR. ROM FLASH 1 2 4 5 7 8 3 9 * 0 # 6 SMART CARD SRAM STN/TFT/ AD-TFT GPIO SSP UART SCI MMC MULTIMEDIA CARD SDRAM LH7A400 DMA COMPACT FLASH CODEC AC97 PC CARD PCMCIA UART USB IR BMI DC to DC BATTERY VOLTAGE GENERATION CIRCUITRY LH7A400-3 Figure 4. Application Diagram SYSTEM DESCRIPTIONS ARM922T Processor The LH7A400 microcontroller features the ARM922T cached core with an Advanced High Performance Bus (AHB) interface. The processor is a member of the ARM9T family of processors. For more information, see the ARM document, ‘ARM922T Technical Reference Manual’, available on ARM’s website at www.arm.com. Clock and State Controller The clocking scheme in the LH7A400 is based around two primary oscillator inputs. These are the 14.7456 MHz input crystal and the 32.768 kHz real time clock oscillator. See Figure 5. The 14.7456 MHz oscillator is used to generate the main system clock domains for the LH7A400, where as the 32.768 kHz is used for controlling the power down operations and real time clock peripheral. The clock and state controller provides the clock gating and frequency division necessary, and then supplies the clocks to the processor and to the rest of the system. The amount of clock gating that actually takes place is dependent on the current power saving mode selected. 20 The 32.768 kHz clock provides the source for the Real Time Clock tree and power-down logic.This clock is used for the power state control in the design and is the only clock in the LH7A400 that runs permanently. The 32.768 kHz clock is divided down to 1 Hz using a ripple divider to save power. This generated 1 Hz clock is used in the Real Time Clock counter. The 14.7456 MHz source is used to generate the main system clocks for the LH7A400. It is the source for PLL1 and PLL2, it acts as the primary clock to the peripherals and is the source clock to the Programmable clock (PGM) divider. PLL1 provides the main clock tree for the chip, it generates the following clocks: FCLK, HCLK and PCLK. FCLK is the clock that drives the ARM922T core. HCLK is the main bus (AHB) clock, as such it clocks all memory interfaces, bus arbitrators and the AHB peripherals. HCLK is generated by dividing FCLK by 1, 2, 3, or 4. HCLK can be gated by the system to enable low power operation. PCLK is the peripheral bus (APB) clock. It is generated by dividing HCLK by either 2, 4, or 8. PLL2 is used to generate a fixed frequency of 48 MHz for the USB peripheral. Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors 14.7456 MHz MAIN OSC. 32.768 kHz RTC OSC. FCLK STATE CONTROLLER HCLK (TO PROCESSOR CORE) DIVIDE REGISTER HCLK /2, /4, /8 PCLKs LH7A400-4 Figure 5. Clock and State Controller Block Diagram Power Modes Data Paths The LH7A400 has three operational states: Run, Halt, and Standby. In Run mode, all clocks are hardware-enabled and the processor is clocked. Halt mode stops the processor clock while waiting for an event such as a key press, but the device continues to function. Finally, Standby equates to the computer being switched ‘off’, i.e. no display (LCD disabled) and the main oscillator is shut down. The 32.768 kHz oscillator operates in all three modes. Reset Modes There are three external signals that can generate resets to the LH7A400; these are nPOR (power on reset), nPWRFL (power failure) and nURESET (user reset). If any of these are active, a system reset is generated internally. A nPOR reset performs a full system reset. The nPWRFL and nURESET resets will perform a full system reset except for the SDRAM refresh control, SDRAM Global Configuration, SDRAM Device Configuration and the RTC peripheral registers. The SDRAM controller will issue a self-refresh command to external SDRAM before the system enters this reset (the nPWRFL and nURESET resets only, not so for the nPOR reset). This allows the system to maintain its Real Time Clock and SDRAM contents. On coming out of reset, the chip enters Standby mode. Once in Run mode the PWRSR register can be interrogated to determine the nature of the reset, and the trigger source, after which software can then take appropriate actions. Preliminary data sheet The data paths in the LH7A400 are: • The AMBA AHB bus • The AMBA APB bus • The External Bus Interface • The LCD AHB bus • The DMA busses. AMBA AHB BUS The Advanced Microprocessor Bus Architecture Advanced High-performance Bus (AMBA AHB) bus is a high speed 32-bit-wide data bus. The AMBA AHB is for high-performance, high clock frequency system modules. Peripherals that have high bandwidth requirements are connected to the LH7A400 core processor using the AHB bus. These include the external and internal memory interfaces, the LCD registers, palette RAM and the bridge to the Advanced Peripheral Bus (APB) interface. The APB Bridge transparently converts the AHB access into the slower speed APB accesses. All of the control registers for the APB peripherals are programmed using the AHB - APB bridge interface. The main AHB data and address lines are configured using a multiplexed bus. This removes the need for tri-state buffers and bus holders, and simplifies bus arbitration. Rev. 01 — 16 July 2007 21 LH7A400 32-Bit System-on-Chip NXP Semiconductors AMBA APB BUS The AMBA APB bus is a lower-speed 32-bit-wide peripheral data bus. The speed of this bus is selectable to be a divide-by-2, divide-by-4 or divide-by-8 of the speed of the AHB bus. EXTERNAL BUS INTERFACE The External Bus Interface (EBI) provides a 32-bit wide, high speed gateway to external memory devices. The memory devices supported include: The LH7A400 can boot from either synchronous or asynchronous ROM/Flash. The selection is determined by the value of the MEDCHG pin at Power On Reset as shown in Table 8. When booting from synchronous memory, then synchronous bank 4 (nSCS3) is mapped into memory location zero. When booting from asynchronous memory, asynchronous memory bank 0 (nSCS0) is mapped into memory location zero. Figure 6 shows the memory map of the LH7A400 system for the two boot modes. Once the LH7A400 has booted, the boot code can configure the ARM922T MMU to remap the low memory space to a location in RAM. This allows the user to set the interrupt vector table. • Asynchronous RAM/ROM/Flash • Synchronous DRAM/Flash • PCMCIA interfaces • CompactFlash interfaces. The EBI can be controlled by either the Asynchronous memory controller or Synchronous memory controller. There is an arbiter on the EBI input, with priority given to the Synchronous Memory Controller interface. LCD AHB BUS The LCD controller has its own local memory bus that connects it to the system’s embedded memory and external SDRAM. The function of this local data bus is to allow the LCD controller to perform its video refresh function without congesting the AHB bus. This leads to better system performance and lower power consumption. There is an arbiter on both the embedded memory and the synchronous memory controller. In both cases the LCD bus is given priority. DMA BUSES The LH7A400 has a DMA system that connects the higher speed/higher data volume APB peripherals (MMC, USB and AC97) to the AHB bus. This enables the efficient transfer of data between these peripherals and external memory without the intervention of the ARM922T core. The DMA engine does not support memory to memory transfers. Memory Map The LH7A400 system has a 32-bit-wide address bus. This allows it to address up to 4GB of memory. This memory space is subdivided into a number of memory banks; see Figure 6. Four of these banks (each of 256MB) are allocated to the Synchronous memory controller. Eight of the banks (again, each 256MB) are allocated to the Asynchronous memory controller. Two of these eight banks are designed for PCMCIA systems. Part of the remaining memory space is allocated to the embedded SRAM, and to the control registers of the AHB and APB. The rest is unused. 22 Table 8. Boot Modes LATCHED BOOTWIDTH1 LATCHED BOOTWIDTH0 LATCHED MEDCHG 8-bit ROM 0 0 0 16-bit ROM 0 1 0 32-bit ROM 1 0 0 32-bit ROM 1 1 0 16-bit SFlash (Initializes Mode Register) 0 0 1 16-bit SROM (Initializes Mode Register) 0 1 1 32-bit SFlash (Initializes Mode Register) 1 0 1 32-bit SROM (Initializes Mode Register) 1 1 1 BOOT MODE Interrupt Controller The LH7A400 interrupt controller is designed to control the interrupts from 28 different sources. Four interrupt sources are mapped to the FIQ input of the ARM922T and 24 are mapped to the IRQ input. FIQs have a higher priority than the IRQs. If two interrupts with the same priority become active at the same time, the priority must be resolved in software. When an interrupt becomes active, the interrupt controller generates an FIQ or IRQ if the corresponding mask bit is set. No latching of interrupts takes place in the controller. After a Power On Reset all mask register bits are cleared, therefore masking all interrupts. Hence, enabling of the mask register must be done by software after a power-on-reset. Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors F000.0000 ASYNCHRONOUS MEMORY (nCS0) SYNCHRONOUS MEMORY (nSCS3) 256MB E000.0000 SYNCHRONOUS MEMORY (nSCS2) SYNCHRONOUS MEMORY (nSCS2) 256MB D000.0000 SYNCHRONOUS MEMORY (nSCS1) SYNCHRONOUS MEMORY (nSCS1) 256MB C000.0000 SYNCHRONOUS MEMORY (nSCS0) SYNCHRONOUS MEMORY (nSCS0) 256MB B001.4000 RESERVED RESERVED B000.0000 EMBEDDED SRAM EMBEDDED SRAM 8000.3800 RESERVED RESERVED 8000.2000 AHB INTERNAL REGISTERS AHB INTERNAL REGISTERS 8000.0000 APB INTERNAL REGISTERS APB INTERNAL REGISTERS 7000.0000 ASYNCHRONOUS MEMORY (CS7) ASYNCHRONOUS MEMORY (CS7) 256MB 6000.0000 ASYNCHRONOUS MEMORY (CS6) ASYNCHRONOUS MEMORY (CS6) 256MB 5000.0000 PCMCIA/CompactFlash (nPCSLOTE2) PCMCIA/CompactFlash (nPCSLOTE2) 256MB 4000.0000 PCMCIA/CompactFlash (nPCSLOTE1) PCMCIA/CompactFlash (nPCSLOTE1) 256MB 3000.0000 ASYNCHRONOUS MEMORY (nCS3) ASYNCHRONOUS MEMORY (nCS3) 256MB 2000.0000 ASYNCHRONOUS MEMORY (nCS2) ASYNCHRONOUS MEMORY (nCS2) 256MB 1000.0000 ASYNCHRONOUS MEMORY (nCS1) ASYNCHRONOUS MEMORY (nCS1) 256MB 0000.0000 SYNCHRONOUS ROM (nSCS3) ASYNCHRONOUS ROM (nCS0) 256MB SYNCHRONOUS MEMORY BOOT 80KB ASYNCHRONOUS MEMORY BOOT LH7A400-6 Figure 6. Memory Mapping for Each Boot Mode External Bus Interface The external bus interface allows the ARM922T, LCD controller and DMA engine access to an external memory system. The LCD controller has access to an internal frame buffer in embedded SRAM and an extension buffer in Synchronous Memory for large displays. The processor and DMA engine share the main system bus, providing access to all external memory devices and the embedded SRAM frame buffer. An arbitration unit ensures that control over the External Bus Interface (EBI) is only granted when an existing access has been completed. See Figure 7. Embedded SRAM The amount of Embedded SRAM contained in the LH7A400 is 80 kB. This Embedded memory is designed to be used for storing code, data, or LCD frame data and to be contiguous with external SDRAM. The 80 kB is large enough to store a QVGA panel (320 × 240) at 8 bits per pixel, equivalent to 70 kB of information. Containing the frame buffer on chip reduces the overall power consumed in any application that uses the LH7A400. Normally, the system has to perform external accesses to acquire this data. The LCD controller is designed to automatically use an overflow frame buffer in SDRAM if a larger screen size is required. This overflow buffer can be located on any Preliminary data sheet 4 kB page boundary in SDRAM, allowing software to set the MMU (in the LCD controller) page tables such that the two memory areas appear contiguous. Byte, Half-Word and Word accesses are permissible. Asynchronous Memory Controller The Asynchronous memory controller is incorporated as part of the memory controller to provide an interface between the AMBA AHB system bus and external (off-chip) memory devices. The Asynchronous Memory Controller provides support for up to eight independently configurable memory banks simultaneously. Each memory bank is capable of supporting: • SRAM • ROM • Flash EPROM • Burst ROM memory. Each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. The memory controller supports only little-endian operation. The memory banks can be configured to support: • Non-burst read and write accesses only to highspeed CMOS static RAM. • Non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. Rev. 01 — 16 July 2007 23 LH7A400 32-Bit System-on-Chip NXP Semiconductors EXTERNAL TO THE LH7A400 INTERNAL TO THE LH7A400 SDRAM ROM PCMCIA/CF SUPPORT SYNCHRONOUS DYNAMIC MEMORY CONTROLLER (SDMC) 80KB EMBEDDED SRAM ARBITER EXTERNAL BUS INTERFACE ADDRESS (EBI) and CONTROL DATA ARBITER SRAM ARBITER SDRAM ASYNCHRONOUS STATIC MEMORY CONTROLLER (SMC) ARBITER ARM922T LCD AHB LCD MEMORY MANAGEMENT UNIT (MMU) COLOR LCD CONTROLLER (CLCDC) DMA CONTROLLER AD-TFT LCD TIMING CONTROLLER ADVANCED HIGH-PERFORMANCE BUS (AHB) LH7A400-8 Figure 7. External Bus Interface Block Diagram 24 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors The Asynchronous Memory Controller has six main functions: • • • • • • Memory bank select Access sequencing Wait states generation Byte lane write control External bus interface CompactFlash or PCMCIA interfacing. LH7A400 MMC bus lines can be divided into three groups: • Power supply: VDD and VSS • Data Transfer: MMCCMD, MMCDATA • Clock: MMCLK. Synchronous Memory Controller The Synchronous memory controller provides a high speed memory interface to a wide variety of Synchronous memory devices, including SDRAM, Synchronous Flash and Synchronous ROMs. The key features of the controller are: • LCD DMA port for high bandwidth • Up to four Synchronous Memory banks that can be independently set up • Special configuration bits for Synchronous ROM operation • Ability to program Synchronous Flash devices using write and erase commands MULTIMEDIACARD ADAPTER The MultiMediaCard Adapter implements MultiMediaCard specific functions, serves as the bus master for the MultiMediacard Bus and implements the standard interface to the MultiMediaCard Cards (card initialization, CRC generation and validation, command/response transactions, etc.). Smart Card Interface (SCI) The SCI (ISO7816) interfaces to an external Smart Card reader. The SCI can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. SCI FEATURES • Supports asynchronous T0 and T1 transmission protocols • On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset • Supports clock rate conversion factor F = 372, with bit rate adjustment factors D = 1, 2, or 4 supported • Data is transferred between the controller and the SDRAM in quad-word bursts. Longer transfers within the same page are concatenated, forming a seamless burst • Direct interrupts for Tx and Rx FIFO level monitoring • Programmable for 16- or 32-bit data bus size • Software-initiated card deactivation sequence on transaction complete • Two reset domains are provided to enable SDRAM contents to be preserved over a ‘soft’ reset • Power saving Synchronous Memory SCKE and external clock modes provided. • Eight-character-deep buffered Tx and Rx paths • Interrupt status register • Hardware-initiated card deactivation sequence on detection of card removal • Limited support for synchronous Smart Cards via registered input/output. PROGRAMMABLE PARAMETERS • Smart Card clock frequency MultiMediaCard (MMC) The MMC adapter combines all of the requirements and functions of an MMC host. The adapter supports the full MMC bus protocol, defined by the MMC Definition Group’s specification v.2.11. The controller can also implement the SPI interface to the cards. • Communication baud rate INTERFACE DESCRIPTION AND MMC OVERVIEW The MMC controller uses the three-wire serial data bus (clock, command, and data) to transfer data to and from the MMC card, and to configure and acquire status information from the card’s registers. • Check for maximum duration of ATR character stream • Protocol convention • Card activation/deactivation time • Check for maximum time for first character of Answer to Reset - ATR reception • Check for maximum time of receipt of first character of data stream • Check for maximum time allowed between characters • Character guard time • Block guard time • Transmit/receive character retry. Preliminary data sheet Rev. 01 — 16 July 2007 25 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Direct Memory Access Controller (DMA) Color LCD Controller The DMA Controller interfaces streams from the following three peripherals to the system memory: The LH7A400’s LCD Controller is programmable to support up to 1,024 × 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A400’s LCD Controller incorporates the timing conversion logic from TFT to HR- and AD-TFT, allowing a direct interface to these panels and minimizing external chip count. • USB (1 Tx and 1 Rx DMA Channel) • MMC (1 Tx and 1 Rx DMA Channel) • AC97 (3 Tx and 3 Rx DMA Channels). Each has its own bi-directional peripheral DMA bus capable of transferring data in both directions simultaneously. All memory transfers take place via the main system AHB bus. DMA Specific features are: The Color LCD Controller features support for: • Up to 1,024 × 768 Resolution • 16-bit Video Bus • Independent DMA channels for Tx and Rx • Two Buffer Descriptors per channel to avoid potential data under/over-flows due to software introduced latency • STN, Color STN, AD-TFT, HR-TFT, TFT panels • Single and Dual Scan STN panels • Up to 15 Gray Shades • No Buffer wrapping • Up to 64,000 Colors • Buffer size may be equal to, greater than, or less than the packet size. Transfers can automatically switch between buffers. AC97 Advanced Audio Codec Interface • Maskable interrupt generation • Internal arbitration between DMA Channels and external bus arbiter. • For DMA Data transfer sizes, byte, word and quadword data transfers are supported. A set of control and status registers are available to the system processor for setting up DMA operations and monitoring their status. A system interrupt is generated when any or all of the DMA channels wish to inform the processor that a new buffer needs to be allocated. The DMA controller services three peripherals using ten DMA channels, each with its own peripheral DMA bus capable of transferring data in both directions simultaneously. The MMC and USB peripherals each use two DMA channels, one for transmit and one for receive. The AC97 peripheral uses six DMA channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overheads. The DMA Controller does not support memory to memory transfers. USB Device The features of the USB are: The AC97 Advanced Audio Codec controller includes a 5-pin serial interface to an external audio codec. The AC97 LINK is a bi-directional, fixed rate, serial Pulse Code Modulation (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AC97 controller contains logic that controls the AC97 link to the Audio Codec and an interface to the AMBA APB. Its main features include: • Serial-to-parallel conversion for data received from the external codec • Parallel-to-serial conversion for data transmitted to the external codec • Reception/Transmission of control and status information via the AMBA APB interface • Supports up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored independently in both transmit and receive modes. The outgoing data for the FIFOs can be written via either the APB interface or with DMA channels 1 - 3. • Fully compliant to USB 1.1 specification • Provides a high level interface that shields the firmware from USB protocol details • Compatible with both OpenHCI and Intel’s UHCI standards • Supports full-speed (12 Mbps) functions • Supports Suspend and Resume signalling. 26 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors Audio Codec Interface (ACI) The ACI provides: • A digital serial interface to an off-chip 8-bit CODEC • All the necessary clocks and timing pulses to perform serialization or de-serialization of the data stream to or from the CODEC device. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACICLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchronization output signal that is synchronous with the bit clock. LH7A400 The transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate: • Four individually maskable interrupts from the receive, transmit and modem status logic blocks • A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is prevented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. Synchronous Serial Port (SSP) Timers The LH7A400 SSP is a master-only interface for synchronous serial communication with device peripheral devices that has either Motorola SPI, National Semiconductor MICROWIRE or Texas Instruments Synchronous Serial Interfaces. Two identical timers are integrated in the LH7A400. Each of these timers has an associated 16-bit read/write data register and a control register. Each timer is loaded with the value written to the data register immediately, this value will then be decremented on the next active clock edge to arrive after the write. When the timer underflows, it will immediately assert its appropriate interrupt. The timers can be read at any time. The clock source and mode is selectable by writing to various bits in the system control register. Clock sources are 508 kHz and 2 kHz. The LH7A400 SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A400 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usually be determined by peripheral devices. UART/IrDA The LH7A400 contains three UARTs, UART1, UART2, and UART3. The UART performs: • Serial-to-Parallel conversion on data received from the peripheral device • Parallel-to-Serial conversion on data transmitted to the peripheral device. Preliminary data sheet Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. It has the same register arrangement as Timer 1 and Timer 2, providing a load, value, control and clear register. Once the timer has been enabled and is written to, unlike the Timer 1 and Timer 2, will decrement the timer on the next rising edge of the 7.3728 MHz clock after the data register has been updated. All the timers can operate in two modes, free running mode or pre-scale mode. FREE-RUNNING MODE In free-running mode, the timer will wrap around to 0xFFFF when it underflows and continue counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a programmable frequency to drive an external buzzer or generate a periodic interrupt. Rev. 01 — 16 July 2007 27 LH7A400 NXP Semiconductors Real Time Clock (RTC) 32-Bit System-on-Chip DC-to-DC Converter The RTC can be used to provide a basic alarm function or long time-base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. Counting in one second intervals is achieved by use of a 1 Hz clock input to the RTC. Battery Monitor Interface (BMI) The LH7A400 BMI is a serial communication interface specified for two types of Battery Monitors/Gas Gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface will have priority. A brief overview of these two interface types are given here. The features of the DC-DC Converter interface are: • Dual drive PWM outputs, with independent closed loop feedback • Software programmable configuration of one of 8 output frequencies (each being a fixed divide of the input clock). • Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. • Output polarity (for positive or negative voltage generation) is hardware-configured during power-on reset via the polarity select inputs • Each PWM output can be dynamically switched to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. Watchdog Timer (WDT) SINGLE WIRE INTERFACE The Single Wire Interface performs: • Serial-to-parallel conversion on data received from the peripheral device • Parallel-to-serial conversion on data transmitted to the peripheral device • Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) The Single Wire interface uses a command-based protocol, in which the host initiates a data transfer by sending a WriteData/Command word to the Battery Monitor. This word will always contain the Command section, which tells the Single Wire Interface device the location for the current transaction. The most significant bit of the Command determines if the transaction is Read or Write. In the case of a Write transaction, then the word will also contain a WriteData section with the data to be written to the peripheral. SMART BATTERY INTERFACE The SMBus Interface performs: • Driven by the system clock • 16 programmable time-out periods: 216 through 231 clock cycles • Generates a system reset (resets LH7A400) or a FIQ Interrupt whenever a time-out period is reached • Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes • Protection mechanism guards against interrupt-service-failure: – The first WDT time-out triggers FIQ and asserts nWDFIQ status flag – If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a System Reset. General Purpose I/O (GPIO) • Serial-to-Parallel conversion on data received from the peripheral device • Parallel-to-Serial conversion of data transmitted to the peripheral device. The Smart Battery Interface uses a two-wire multimaster bus (the SMBus), meaning that more than one device capable of controlling the bus can be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data provided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism, by relying on the wired-AND connection of all SMBus interfaces to the SMBus. 28 The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause a FIQ interrupt. Failure to service the FIQ interrupt will then generate a System Reset. The WDT features are: The LH7A400 GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI, and PGHCON. The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE1/2, and GPIOFEOI registers are used to control edge-triggered Interrupts on Port F. The PINMUX register controls what signals are output of Port D and Port E when they are set as outputs, while the PGHCON controls the operations of Port G and H. Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER MINIMUM MAXIMUM DC Core Supply Voltage (VDDC) −0.3 V 2.4 V DC I/O Supply Voltage (VDD) −0.3 V 4.6 V DC Analog Supply Voltage (VDDA) −0.3 V 2.4 V 5 V Tolerant Digital Input Pin Voltage −0.5 V 5.5 V ESD, Human Body Model (Analog pins AN0 - AN9 rated at 500 V) 2 kV ESD, Charged Device Model 1 kV −55°C Storage Temperature 125°C NOTE: Except for Storage Temperature, these ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Recommended Operating Conditions PARAMETER MINIMUM TYPICAL MAXIMUM NOTES DC Core Supply Voltage (VDDC) 1.71 V 1.8 V 1.89 V 1, 4 DC Core Supply Voltage (VDDC) 2.0 V 2.1 V 2.2 V 1, 5 DC I/O Supply Voltage (VDD) 3.0 V 3.3 V 3.6 V 2, 6 DC I/O Supply Voltage (VDD) 3.14 V 3.3 V 3.6 V 2, 7 DC Analog Supply Voltage for PLLs (VDDA) 1.71 V 1.8 V 1.89 V Clock Frequency (0°C to +70°C) 10 MHz 200 MHz 3, 4, 6 Clock Frequency (−40°C to +85°C) 10 MHz 195 MHz 3, 4, 6 100 MHz 3, 4, 6 Bus Clock Frequency (−40°C to +85°C) Clock Frequency (0°C to +70°C) 10 MHz 250 MHz 3, 5, 7 Clock Frequency (−40°C to +85°C) 10 MHz 245 MHz 3, 5, 7 125 MHz 3, 5, 7 8 Bus Clock Frequency (−40°C to +85°C) 14 MHz 14.7456 MHz 20 MHz External Clock Input (XTALIN) Voltage External Clock Input (XTALIN) 1.71 V 1.8 V 1.89 V Operating Temperature −40°C 25°C +85°C NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See “Power Supply Sequencing” on page 33 2. USB is not functional below 3.0 V 3. Using 14.7456 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal 4. VDDC = 1.71 V to 1.89 V (LH7A400N0G000xx) 5. VDDC = 2.1 V ± 5 % (LH7A400N0G076xx only) 6. VDD = 3.0 V to 3.6 V (LH7A400N0G000xx) 7. VDD = 3.14V to 3.60 V (LH7A400N0G076xx only) 8. IMPORTANT: Most peripherals will NOT function with crystals other than 14.7456 MHz. Preliminary data sheet Rev. 01 — 16 July 2007 29 LH7A400 32-Bit System-on-Chip NXP Semiconductors 245 240 FREQUENCY (MHz) 235 230 225 1.89 V (+5%) 220 215 210 1.80 V 205 200 195 25 35 45 55 65 75 1.71 V (-5%) 85 TEMP (°C) LH7A400-206 Figure 8. Temperature/Voltage/Speed Chart (For LH7A400N0G000xx) Table 9. Clock Frequency vs. Voltages (VDDC) vs. Temperature PARAMETER 25°C 70°C 85°C Clock Frequency (FCLK) Clock Period (FCLK) Clock Frequency (FCLK) Clock Period (FCLK) Clock Frequency (FCLK) Clock Period (FCLK) 1.71 V 1.8 V 1.89 V 211 MHz 225 MHz 240 MHz 4.74 ns 4.44 ns 4.17 ns 200 MHz 212 MHz 227 MHz 5.00 ns 4.72 ns 4.41 ns 195 MHz 208 MHz 222 MHz 5.13 ns 4.81 ns 4.50 ns NOTES: 1. Table 9 is representative of a typical wafer process. Guaranteed values are in the Recommended Operating Conditions table. 2. LH7A400N0G000xx 30 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors DC/AC SPECIFICATIONS Unless otherwise noted, all data provided in these specifications are based on −40°C to +85°C, VDDC = 1.71 V to 1.89 V, VDD = 3.0 V to 3.6 V, VDDA = 1.71 V to 1.89 V. DC Specifications SYMBOL PARAMETER MIN. TYP. MAX. UNIT VIH CMOS and Schmitt Trigger Input HIGH Voltage 2.0 5.5 V VIL CMOS and Schmitt Trigger Input LOW Voltage −0.2 0.8 V VHST Schmitt Trigger Hysteresis 0.25 V VIL to VIH Output Drive 2 2.6 V IOH = −4 mA VOH VOL CONDITIONS Output Drive 3 2.6 V IOH = −8 mA Output Drive 4 and 5 2.6 V IOH = −12 mA Output Drive 2 0.4 V IOL = 4 mA Output Drive 3 0.4 V IOL = 8 mA Output Drive 4 0.4 V IOL = 12 mA Output Drive 5 0.4 V IOL = 20 mA Input Leakage Current −10 10 µA VIN = VDD or GND IIN Input Leakage Current (with pull-up resistors installed) −200 −20 µA VIN = VDD or GND IOZ Output Tri-state Leakage Current −10 10 µA VOUT = VDD or GND ISTARTUP Startup Current 50 µA IACTIVE Active Current 125 180 mA IHALT Halt Current 25 41 mA ISTANDBY Standby Current NOTES 1 1 2 µA 42 CIN Input Capacitance 4 pF COUT Output Capacitance 4 pF NOTES: 1. Output Drive 5 can sink 20 mA of current, but sources 12 mA of current. 2. Current consumption until oscillators are stabilized. AC Test Conditions PARAMETER DC I/O Supply Voltage (VDD) DC Core Supply Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Preliminary data sheet RATING UNIT 3.0 to 3.6 V 1.71 to 1.89 V VSS to 3 V 2 ns VDD/2 V Rev. 01 — 16 July 2007 31 32-Bit System-on-Chip NXP Semiconductors SYMBOL LH7A400N0G076xx (FCLK = 250 MHz) Table 10. Current Consumption by Mode CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 10 were derived under the conditions presented here. LH7A400N0G000xx (FCLK = 200 MHz) LH7A400 TYP. MAX. TYP. UNITS 250 mA PARAMETER Maximum Specified Value The values specified in the MAXIMUM column were determined using these operating characteristics: • All IP blocks either operating or enabled at maximum frequency and size configuration • Core operating at maximum power configuration • All voltages at maximum specified values • Maximum specified ambient temperature (tAMB). ACTIVE MODE ICORE Core Current 110 135 IIO I/ O Current 15 45 mA HALT MODE (ALL PERIPHERALS DISABLED) ICORE Core Current 24 39 50 mA Typical IIO I/ O Current 1 2 The values in the TYPICAL column were determined using a ‘typical’ application under ‘typical’ environmental conditions and the following operating characteristics: STANDBY MODE (TYPICAL CONDITIONS ONLY) mA ICORE Core Current 40 125 µA IIO I/ O Current 2 4 µA • LINUX operating system running from SDRAM • UART and AC97 peripherals operating; all other peripherals as needed by the OS • LCD enabled with 320 × 240 × 16-bit color, 60 Hz refresh rate, data in SDRAM • I/O loads at nominal • Cache enabled • FCLK = 200 MHz or 250 MHz; HCLK = 100 MHz or 125 MHz; PCLK = 50 MHz or 62.5 MHz PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 11 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the CPU clock running at 200 MHz, typical conditions, and no I/O loads. This current is supplied by the 1.8 VDDC power supply. Table 11. Peripheral Current Consumption • All voltages at typical values • Nominal case temperature (tAMB). PERIPHERAL TYPICAL UNITS AC97 1.3 mA UART (Each) 1.0 mA 0.005 mA 0.1 mA 5.4 (1.0) mA MMC 0.6 mA SCI 23 mA < 0.1 mA BMI-SWI 1.0 mA BMI-SBus 1.0 mA SDRAM (+I/O) 1.5 (14.8) mA USB (+PLL) 5.6 (3.3) mA 0.8 mA RTC Timers (Each) LCD (+I/O) PWM (each) ACI 32 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors Power Supply Sequencing • ACBITCLK, AC97 clock NXP recommends that the 1.8 V power supply be energized before the 3.3 V supply. If this is not possible, the 1.8 V supply may not lag the 3.3 V supply by more than 100 µs. If longer delay time is needed, it is recommended that the voltage difference between the two power supplies be within 1.5 V during power supply ramp up. • SCLK, Synchronous Memory clock. To avoid a potential latchup condition, voltage should be applied to input pins only after the device is powered-on as described above. AC Specifications All signals described in Table 12 relate to transitions after a reference clock signal. The illustration in Figure 9 represents all cases of these sets of measurement parameters. The reference clock signals in this design are: • HCLK, internal System Bus clock (‘C’ in timing data) • PCLK, Peripheral Bus clock • SSPCLK, Synchronous Serial Port clock • UARTCLK, UART Interface clock LH7A400 All signal transitions are measured at the 50 % point. For outputs from the LH7A400, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from a valid address bus, or rising edge of the peripheral clock. Maximum requirements for tOVXXX are shown in Table 12. The signal tOHXXX (e.g. tOHA) represents the amount of time the output will be held valid from the valid address bus, or rising edge of the peripheral clock. Minimum requirements for tOHXXX are listed in Table 12. For Inputs, tISXXX (e.g. tISD) represents the amount of time the input signal must be valid before a valid address bus, or rising edge of the peripheral clock (except SSP and ACI). Maximum requirements for tISXXX are shown in Table 12. The signal tIHXXX (e.g. tIHD) represents the amount of time the output must be held valid from the valid address bus, or rising edge of the peripheral clock (except SSP and ACI). Minimum requirements are shown in Table 12. • LCDDCLK, LCD Data clock from the LCD Controller REFERENCE CLOCK tOVXXX tOHXXX OUTPUT SIGNAL (O) tISXXX tIHXXX INPUT SIGNAL (I) 7A400-28 Figure 9. LH7A400 Signal Timing Preliminary data sheet Rev. 01 — 16 July 2007 33 LH7A400 32-Bit System-on-Chip NXP Semiconductors Table 12. AC Signal Characteristics SIGNAL TYPE LOAD SYMBOL MIN. MAX. DESCRIPTION ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ [wait states × HCLK period])1 A[27:0] Output 50 pF tRC 4 × tHCLK – 7.0 ns 4 × tHCLK + 7.5 ns Output 50 pF tWC 4 × tHCLK – 7.0 ns 4 × tHCLK + 7.5 ns Write Cycle Time — — tWS tHCLK ns tHCLK ns Wait State Width Output 50 pF D[31:0] Input nCS[7:0] Output — 30 pF Read Cycle Time tDVWE tHCLK – 6.0 ns tHCLK – 2.0 ns Data Valid to Write Edge (nWE invalid) tDHWE tHCLK – 7.0 ns tHCLK + 2.0 ns Data Hold after Write Edge (nWE invalid) tDVBE tHCLK – 5.0 ns tHCLK – 1.0 ns Data Valid to nBLE Invalid tDHBE tHCLK – 7.0 ns tHCLK + 3.0 ns Data Hold after nBLE Invalid tDSCS 15 ns — tDHCS 0 ns — Data Setup to nCSx Invalid Data Hold to nCSx Invalid tDSOE 15 ns — Data Setup to nOE Invalid tDHOE 0 ns — Data Hold to nOE Invalid tDSBE 15 ns — Data Setup to nBLE Invalid tDHBE 0 ns — Data Hold to nBLE Invalid tCS 2 × tHCLK – 3.0 ns 2 × tHCLK + 3.0 ns tAVCS tHCLK – 4.0 ns tHCLK tAHCS tHCLK tHCLK + 4.5 ns nCSx Width Address Valid to nCSx Valid Address Hold after nCSx Invalid SYNCHRONOUS MEMORY INTERFACE SIGNALS SA[13:0] Output 50 pF SA[17:16]/SB[1:0] Output 50 pF Output 50 pF D[31:0] Input nCAS Output 30 pF nRAS Output 30 pF nSWE Output 30 pF SCKE[1:0] Output DQM[3:0] nSCS[3:0] tOVA tOHA 3 5.53/7.54 ns Address Valid 5.53/7.54 ns Bank Select Valid 4 1.5 /1.5 ns tOVB tOHD 1.5ns tOVD 2 ns 3 Address Hold Data Hold 5.53/7.54 ns 4 Data Valid tISD 1.5 /2.5 ns Data Setup tIHD 1.03/1.54 ns Data Hold tOVCA 2 ns tOHCA 1.53/24 ns tOVRA 2 ns tOHRA 3/24 1.5 5.53/7.54 ns CAS Valid CAS Hold 5.53/7.54 ns ns RAS Valid RAS Hold 5.53/7.54 ns Write Enable Valid tOVSDW 2 ns tOHSDW 1.53/24 ns 30 pF tOVC 2 ns 5.53/7.54 ns Clock Enable Valid Output 30 pF tOVDQ 2 ns 5.53/7.54 ns Data Mask Valid Output 30 pF tOVSC 2 ns 5.53/7.54 ns tOHSC 1.53/24 ns Write Enable Hold Synchronous Chip Select Valid Synchronous Chip Select Hold PCMCIA INTERFACE SIGNALS (+ wait states × HCLK period) nPCREG Output Output 30 pF 50 pF D[31:0] nPCCE2 nPCOE Output Output Output tIHD 30 pF 30 pF 30 pF nPCWE Output 30 pF PCDIR Output 30 pF 34 tOVD tOHD Data Hold Data Setup Time Data Hold Time tHCLK Chip Enable 1 Valid tHCLK Chip Enable 2 Valid tHCLK + 1 ns Output Enable Valid Chip Enable 1 Hold 4 × tHCLK – 5 ns Chip Enable 2 Hold 3 × tHCLK – 5 ns Output Enable Hold tHCLK + 1 ns 3 × tHCLK – 5 ns tOVPCD tOHPCD nREG Hold 4 × tHCLK – 5 ns tOVWE tOHWE Data Valid 4 × tHCLK – 5 ns tOVOE tOHOE tHCLK tHCLK - 10 ns tOVCE2 tOHCE2 nREG Valid 4 × tHCLK – 5 ns tOVCE1 tOHCE1 tHCLK 4 × tHCLK – 5 ns tISD Input nPCCE1 tOVDREG tOHDREG Write Enable Valid Write Enable Hold tHCLK 4 × tHCLK – 5 ns Rev. 01 — 16 July 2007 Card Direction Valid Card Direction Hold Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors Table 12. AC Signal Characteristics (Cont’d) SIGNAL TYPE LOAD SYMBOL MIN. MAX. DESCRIPTION MMC INTERFACE SIGNALS MMCCMD MMCDATA MMCDATA MMCCMD Output Output 100 pF 100 pF Input Input tOS 5 ns tOH 5 ns MMC Command Hold tOS 5 ns MMC Data Setup tOH 5 ns MMC Data Hold tIS 3 ns MMC Data Setup tIH 3 ns MMC Data Hold tIS 3 ns MMC Command Setup 3 ns MMC Command Hold tIH MMC Command Setup AC97 INTERFACE SIGNALS ACOUT/ACSYNC Output ACIN Input ACBITCLK Input 30 pF tOVAC97 15 ns AC97 Output Valid/Sync Valid tOHAC97 10 ns AC97 Output Hold/Sync Hold tISAC97 10 ns AC97 Input Setup tIHAC97 2.5 ns tACBITCLK 72 ns AC97 Input Hold 90 ns AC97 Clock Period SYNCHRONOUS SERIAL PORT (SSP) SSPFRM Output SSPTX Output tOVSSPFRM 10 ns tOHSSPFRM 50 pF 5 ns tOVSSPOUT 10 ns tOHSSPOUT 5 ns SSPRX Input tISSSPIN 14 ns SSPCLK Output tSSPCLK 8.819 ms SSPFRM Valid SSPFRM Hold SSP Transmit Valid SSP Transmit Hold SSP Receive Setup 271 ns SSP Clock Period AUDIO CODEC INTERFACE (ACI) ACOUT ACIN Output 30 pF Input tOVD 15 ns tOHD 10 ns ACOUT delay from rising clock edge ACOUT Hold tIS 10 ns ACIN Setup tIH 2.5 ns ACIN Hold COLOR LCD CONTROLLER LCDVD [17:0] Output 30 pF tOV — 3 ns LCD Data Clock to Data Valid NOTES: 1. Register BCRx:WST1 = 0b000 2. For Output Drive strength specifications, refer to Table 3 3. LH7A400N0G076xx only 4. LH7A400N0G000xx only Preliminary data sheet Rev. 01 — 16 July 2007 35 LH7A400 32-Bit System-on-Chip NXP Semiconductors SMC Waveforms deassertion of nCS by a maximum of one HCLK, or at minimum, can coincide (see Table 12). Figure 12 and Figure 13 show the waveform and timing for an External Asynchronous Memory Read. Figure 10 and Figure 11 show the waveform and timing for an External Asynchronous Memory Write. Note that the deassertion of nWE can precede the 0 1 2 3 4 HCLK tWC A[27:0] VALID ADDRESS tDVWE, tDVBE D[31:0] tDHWE, tDHBE VALID DATA tCS tAVCS nCSx tAHCS nCS Valid tAVWE tWE tCSHWE nWE Valid nWE WRITE EDGE tAVBE nBLE tBEW tCSHBE nBLE Valid LH7A400-201 Figure 10. External Asynchronous Memory Write with 0 Wait States (BCRx:WST1 = 0b000) 36 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors 0 1 2 3 4 5 6 7 8 HCLK VALID ADDRESS A[27:0] VALID DATA D[31:0] nCSx nCSx Valid WRITE EDGE nWE nWE Valid nBLE nBLE Valid WAIT WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 STATE 4 0 WAIT STATE tWS tWS tWS tWS LH7A400-203 Figure 11. External Asynchronous Memory Write with 4 Wait States (BCRx:WST1 = 0b100) Preliminary data sheet Rev. 01 — 16 July 2007 37 LH7A400 32-Bit System-on-Chip NXP Semiconductors 0 1 2 3 4 HCLK tRC tAHCS, tAHOE, tAHBE A[27:0] VALID ADDRESS VALID DATA D[31:0] tDSCS tAVCS tCS DATA LATCHED HERE tDHCS nCSx nCS Valid tDSOE tAVOE tOE tDHOE nOE nOE Valid tDSBE tAVBE tBER tDHBE nBLE nBLE Valid LH7A400-200 Figure 12. External Asynchronous Memory Read with 0 Wait States (BCRx:WST1 = 0b000) 38 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip 0 LH7A400 NXP Semiconductors 1 2 3 4 5 6 7 8 9 10 HCLK A[27:0] VALID ADDRESS nCS[3:0, CS[7:6] nCSx Valid nOE nOE Valid nBLE nBLE Valid D[31:0] VALID DATA 0 WAIT STATE, DATA WOULD BE LATCHED HERE WAIT WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 STATE 4 tWS tWS tWS tWS 4 WAIT STATES, DATA LATCHED HERE LH7A400-202 Figure 13. External Asynchronous Memory Read with 4 Wait States (BCRx:WST1 = 0b100) Synchronous Memory Controller Waveforms Figure 14 shows the timing for a Synchronous Burst Read (page already open). Figure 15 shows the timing for Activate a Bank and Write. SSP Waveforms The Synchronous Serial Port (SSP) supports three data frame formats: • Texas Instruments SSI • Motorola SPI • National Semiconductor MICROWIRE Figure 16 and Figure 17 show Texas Instruments synchronous serial frame format, Figure 18 through Figure 25 show the Motorola SPI format, and Figure 26 and Figure 27 show National Semiconductor’s MICROWIRE data frame format. For Texas Instruments SSI format, the SSPFRM pin is pulsed prior to each frame’s transmission for one serial clock period beginning at its rising edge. For this frame format, both the SSP and the external slave device drive their output data on the rising edge of the clock and latch data from the other device on the falling edge. See Figure 16 and Figure 17. Each frame format is between 4 and 16 bits in length, depending upon the programmed data size. Each data frame is transmitted beginning with the Most Significant Bit (MSB) i.e. ‘big endian’. For all three formats, the SSP serial clock is held LOW (inactive) while the SSP is idle. The SSP serial clock transitions only during active transmission of data. The SSPFRM signal marks the beginning and end of a frame. The SSPEN signal controls an off-chip line driver’s output enable pin. Preliminary data sheet Rev. 01 — 16 July 2007 39 LH7A400 NXP Semiconductors 32-Bit System-on-Chip tSCLK SCLK tOHXXX SDRAMcmd READ tOHA, tOHB tOVXXX nDQM SA[13:0], SB[1:0] BANK, COLUMN tISD tIHD tOVA, tOVB D[31:0] NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. 3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC. 4. DQM[3:0] is static LOW. 5. SCKE is static HIGH. DATA n DATA n + 2 DATA n + 1 DATA n + 3 LH7A400-23 Figure 14. Synchronous Burst Read SCLK tOVC SCKE tOVXXX tOHXXX ACTIVE SDRAMcmd WRITE tOHA SA[13:0], SB[1:0] BANK, ROW BANK, COLUMN tOVA DATA D[31:0] tOVD tOHD NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. Refer to the AC timing table. 3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC. LH7A400-24 Figure 15. Synchronous Bank Activate and Write 40 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors SSPCLK SSPFRM SSPTXD/ SSPRXD MSB LSB 4 to 16 BITS LH7A400-97 Figure 16. Texas Instruments Synchronous Serial Frame Format (Single Transfer) SSPCLK SSPFRM SSPTXD/ SSPRXD MSB LSB 4 to 16 BITS LH7A400-98 Figure 17. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer) SSPCLK nSSPFRM SSPRXD LSB MSB Q 4 to 16 BITS SSPTXD MSB LSB NOTE: Q is undefined. LH7A400-99 Figure 18. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0 Preliminary data sheet Rev. 01 — 16 July 2007 41 LH7A400 32-Bit System-on-Chip NXP Semiconductors SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB LSB MSB MSB 4 to 16 BITS LH7A400-100 Figure 19. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q LSB MSB Q 4 to 16 BITS SSPTXD LSB MSB NOTE: Q is undefined. LH7A400-101 Figure 20. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 1 SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB LSB MSB 4 to 16 BITS LH7A400-102 Figure 21. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 1 SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB LSB MSB 4 to 16 BITS LH7A400-103 Figure 22. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 1 42 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors SSPCLK nSSPFRM LSB MSB SSPRXD Q 4 to 16 BITS SSPTXD LSB MSB NOTE: Q is undefined. LH7A400-104 Figure 23. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPTXD/ SSPRXD LSB MSB LSB MSB 4 to 16 BITS LH7A400-105 Figure 24. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB LSB Q 4 to 16 BITS SSPTXD MSB LSB NOTE: Q is undefined. LH7A400-106 Figure 25. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 1 Preliminary data sheet Rev. 01 — 16 July 2007 43 LH7A400 32-Bit System-on-Chip NXP Semiconductors an 8-bit control message is transmitted to the off-chip slave. During this transmission no incoming data is received by the SSP. After the message has been sent, the external slave device decodes the message. After waiting one serial clock period after the last bit of the 8bit control message was received it responds by returning the requested data. The returned data can be 4 to 16 bits in length, making the total frame length between 13 to 25 bits. See Figure 26 and Figure 27. For National Semiconductor MICROWIRE format, the serial frame pin (SSPFRM) is active LOW. Both the SSP and external slave device drive their output data on the falling edge of the clock, and latch data from the other device on the rising edge of the clock. Unlike the full-duplex transmission of the other two frame formats, the National Semiconductor MICROWIRE format utilizes a master-slave messaging technique that operates in half-duplex. When a frame begins in this mode, SSPCLK nSSPFRM SSPTXD MSB LSB 8-BIT CONTROL SSPRXD 0 LSB MSB 4 to 16 BITS OUTPUT DATA LH7A400-107 Figure 26. MICROWIRE Frame Format (Single Transfer) SSPCLK nSSPFRM SSPTXD LSB MSB LSB 8-BIT CONTROL SSPRXD 0 MSB LSB MSB 4 to 16 BITS OUTPUT DATA LH7A400-108 Figure 27. MICROWIRE Frame Format (Continuous Transfers) 44 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 PC Card (PCMCIA) Waveforms Figure 28 shows the waveforms and timing for a PCMCIA Read Transfer, Figure 29 shows the waveforms and timing for a PCMCIA Write Transfer. PRECHARGE ACCESS HOLD TIME TIME TIME (See Note 1) (See Note 1) (See Note 1) HCLK A[25:0] ADDRESS nPCREG tOVDREG tOHDREG nPCCEx (See Note 2) tOVCEx tOHCEx PCDIR tOVPCD tOHPCD DATA D[15:0] tISD tIHD nPCOE tOVOE tOHOE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 0 0 0 1 1 0 1 1 TRANSFER TYPE Common Memory Attribute Memory I/O None LH7A400-11 Figure 28. PCMCIA Read Transfer Preliminary data sheet Rev. 01 — 16 July 2007 45 LH7A400 32-Bit System-on-Chip NXP Semiconductors PRECHARGE ACCESS HOLD TIME TIME TIME (See Note 1) (See Note 1) (See Note 1) HCLK A[25:0] ADDRESS nPCREG tOVDREG tOHDREG nPCCEx (See Note 2) tOVCEx tOHCEx PCDIR tOVPCD DATA D[15:0] tOVD tOHD nPCWE tOVWE tOHWE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 0 0 0 1 1 0 1 1 TRANSFER TYPE Common Memory Attribute Memory I/O None LH7A400-12 Figure 29. PCMCIA Write Transfer ACCESS nPCWE, nPCOE PRECHARGE HOLD nCSx LH7A400-209 Figure 30. PCMCIA Precharge, Access, and Hold Waveform 46 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors MMC Interface Waveform AC97 Interface Waveform Figure 31 shows the waveforms and timing for an MMC command or data Read and Write. Figure 32 shows the waveforms and timing for the AC97 interface Data Setup and Hold. MMC CLOCK tIS tIH SOC INPUT DATA/CMD DATA tOS SOC OUTPUT DATA /CMD INVALID tOH DATA INVALID LH7A400-14 Figure 31. MMC Command/Data Read and Write Timing tACBITCLK ACBITCLK tOVAC97 tOHAC97 ACOUT/ACSYNC tISAC97 tIHAC97 ACIN LH7A400-16 Figure 32. AC97 Data Setup and Hold Preliminary data sheet Rev. 01 — 16 July 2007 47 LH7A400 32-Bit System-on-Chip NXP Semiconductors Audio Codec Interface Waveforms Color LCD Controller Waveforms Figure 33 and Figure 34 show the timing for the ACI. Transmit data is clocked on the rising edge of ACBITCLK (whether transmitted by the LH7A400 ACI or by the external codec chip); receive data is clocked on the falling edge. This allows full-speed, full duplex operation. Figure 35 shows the Valid Output Setup Time for LCD data. Timing diagrams for each CLCDC mode appear in Figure 36 through Figure 41. ACBITCLK ACSYNC/ACOUT tOS tOH ACIN tIS tIH LH7A400-169 Figure 33. ACI Signal Timing ACBITCLK ACSYNC BIT ACIN/ACOUT 7 6 5 4 3 2 1 0 7 6 ACIN/ACOUT SAMPLED ON FALLING EDGE LH7A400-181 Figure 34. ACI Data stream LCDDCLK tOV LCDVD (SoC Output) DATA VALID LH7A400-211 Figure 35. CLCDC Valid Output Data Time 48 Rev. 01 — 16 July 2007 Preliminary data sheet Preliminary data sheet Rev. 01 — 16 July 2007 NOTE: LCDDCLK IS SUPPRESSED DURING LCDLLP TIMING0:HSW Circled numbers are LH7A400 pin numbers. LCDVD[17:0] (LCD DATA) THE ACTIVE DATA LINES WILL VARY WITH THE TYPE OF STN PANEL: 4-BIT, 8-BIT, COLOR, OR MONO N9 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL R8 LCDLP (LINE SYNC PULSE) TIMING2:IHS CLCDC CLOCK (INTERNAL) ENUMERATED IN 'LCDDCLKS' HORIZONTAL BACK PORCH TIMING0:HBP D001 D002 ONE 'LINE' OF LCD DATA D.... TIMING0:PPL 1 STN HORIZONTAL LINE DNNN ENUMERATED IN 'LCDDCLKS' HORIZONTAL FRONT PORCH TIMING0:HFP LH7A400-113 32-Bit System-on-Chip NXP Semiconductors LH7A400 Figure 36. STN Horizontal Timing Diagram 49 50 LCDVDDEN (DISPLAY ENABLE) Rev. 01 — 16 July 2007 LCDENAB (AC BIAS) TIMING2:ACB TIMING1:VSW = 0 3. Circled numbers are LH7A400 pin numbers. ENUMERATED IN HORIZONTAL 'LINES' BACK PORCH TIMING1: VBP TIMING1:LPP SEE 'STN HORIZONTAL TIMING DIAGRAM' ALL 'LINES' FOR ONE FRAME AC BIAS ACTIVE PANEL DATA CLOCK ACTIVE PANEL LOGIC ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE 1 STN FRAME ENUMERATED IN HORIZONTAL 'LINES' FRONT PORCH TIMING1:VFP LH7A400-112 DISPLAY-DEPENDENT TURN-OFF DELAY NXP Semiconductors NOTES: 1. Signal polarties may vary for some displays. 2. LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period. PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME R6 LCDFP (FRAME PULSE) TIMING1:IVS (See Note 2) P9 N9 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDMux:PIN133 R1 VSS VDD DISPLAY-DEPENDENT TURN-ON DELAY LH7A400 32-Bit System-on-Chip Figure 37. STN Vertical Timing Diagram Preliminary data sheet Preliminary data sheet Rev. 01 — 16 July 2007 NOTE: TIMING0:HSW Circled numbers are LH7A400 pin numbers. LCDVD[17:0] (LCD DATA) N9 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL R8 LCDLLP (HORIZ. SYNC PULSE) TIMING2:IHS CLCDC CLOCK (INTERNAL) ENUMERATED IN 'LCDDCLKS' HORIZONTAL BACK PORCH TIMING0:HBP D001 D002 ONE 'LINE' OF LCD DATA D.... 16 × (TIMING0:PPL+1) 1 TFT HORIZONTAL LINE DNNN ENUMERATED IN 'LCDDCLKS' HORIZONTAL FRONT PORCH TIMING0:HFP LH7A400-192 32-Bit System-on-Chip NXP Semiconductors LH7A400 Figure 38. TFT Horizontal Timing Diagram 51 52 R1 LCDVDDEN (ENABLE FOR LOW-VOLTAGE DIGITAL LOGIC AND ANALOG SUPPLIES) Rev. 01 — 16 July 2007 LCDENAB (DATA ENABLE) TIMING2:IOE TIMING1: VSW ENUMERATED IN HORIZONTAL 'LINES' BACK PORCH TIMING1:VBP 3. Circled numbers are LH7A400 pin numbers. TIMING1:LPP SEE 'TFT HORIZONTAL TIMING DIAGRAM' ALL 'LINES' FOR ONE FRAME DATA ENABLE ENUMERATED IN HORIZONTAL 'LINES' FRONT PORCH TIMING1: VFP LH7A400-109 DISPLAY DEPENDENT TURN-OFF DELAY NXP Semiconductors NOTES: 1. Signal polarties may vary for some displays. 2. The use of LCDVDDEN for high-voltage power control is optional on some TFT panels. PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME R6 LCDFP (VERTICAL SYNC PULSE) TIMING1:IVS P9 PANEL DATA CLOCK ACTIVE PANEL LOGIC ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE VSS N9 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC See Note 2 PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE 1 TFT FRAME VDD DISPLAY-DEPENDENT TURN-ON DELAY LH7A400 32-Bit System-on-Chip Figure 39. TFT Vertical Timing Diagram Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors 1 AD-TFT or HR-TFT HORIZONTAL LINE CLCDC CLOCK (INTERNAL) TIMING0:HSW R8 LCDLP INPUTS TO THE ALI FROM THE CLCDC (HORIZONTAL SYNC PULSE) LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDVD[17:0] 16 × (TIMING0:PPL+1) 001 002 003 004 005 006 007 008 320 PIXEL DATA TIMING0:HSW + TIMING0:HBP LCDENAB (INTERNAL DATA ENABLE) N9 LCDDCLK (DELAYED FOR HR-TFT) LCDVD[17:0] (DELAYED FOR HR-TFT) 001 002 003 004 005 006 317 318 319 320 1 LCDDCLK OUTPUTS FROM THE ALI TO THE PANEL ALITIMING2:SPLDEL R2 LCDSPL (LINE START PULSE LEFT) 1 LCDDCLK ALITIMING1:LPDEL R8 LCDLP (HORIZONTAL SYNC PULSE) ALITIMING1:PSCLS ALITIMING2:PS2CLS2 T1 LCDCLS P2 LCDPS ALITIMING1:REVDEL K6 LCDREV NOTE: Circled numbers are LHA400 pin numbers. LH7A400-111 Figure 40. AD-TFT and HR-TFT Horizontal Timing Diagram Preliminary data sheet Rev. 01 — 16 July 2007 53 LH7A400 32-Bit System-on-Chip NXP Semiconductors TIMING1:VSW L8 LCDSPS (Vertical Sync) 1.5 µs - 4 µs T2 LCDHRLP (Horizontal Sync) LCDVD (LCD Data) 2x H-LINE R2 LCDSPL LH7A400-66 Figure 41. AD-TFT and HR-TFT Vertical Timing Diagram CLOCK AND STATE CONTROLLER (CSC) WAVEFORMS Figure 42 shows the behavior of the LH7A400 when coming out of Reset or Power On. Figure 43 shows external reset timing, and Table 13 gives the timing parameters. Figure 44 depicts signal timing following a Reset. At Power-On, nPOR must be held LOW at least until the 32.768 kHz oscillator is stable, and must be deasserted at least two 32.768 kHz clock periods before the WAKEUP signal is asserted. Once the 14.7456 MHz oscillator is stable, the PLLs require 250 µs to lock. On transition from Standby to Run (including a Cold Boot), the Wakeup pin must not be asserted for 2 seconds after assertion of nPOR to allow time for sampling BATOK and nEXTPWR. The delay prevents a false ‘battery good’ indication caused by alkaline battery recovery that can immediately follow a battery-low switch off. The battery sampling takes place on the rising edge of the 1 Hz clock. This clock is derived from the 32.768 kHz oscillator. The WAKEUP pin can be pulsed, but at least one edge must follow the 2 second delay to be recognized. For more information, see the application note “Implementing Auto-Wakeup on the LH7A4xx Series Devices” at www.nxp.com. Figure 45 shows the recommended components for the NXP LH7A400 32.768 kHz external oscillator circuit. Figure 46 shows the same for the 14.7456 MHz external oscillator circuit. In both figures, the NAND gate represents the internal logic of the chip. Table 13. Reset AC Timing PARAMETER DESCRIPTION MIN. MAX. UNIT tOSC32 32.768 kHz Oscillator Stabilization Time after Power On* 550 ms tOSC14 14.7456 MHz Oscillator Stabilization Time after Wake UP 4 ms tURESET/tPWRFL nURESET/nPWRFL Pulse Width 4 32.768 kHz clock periods NOTE: *VDDC = VDDCmin 54 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors VDDCmin VDDC XTAL32 tOSC32 WAKEUP tOSC14 XTAL14 nPOR LH7A400-25 Figure 42. Oscillator Start-up tURESET tPWRFL nURESET nPWRFL LH7A400-26 Figure 43. External Reset nPOR 2 sec. WAKEUP (asynchronous) ≤ 7.8125 ms CLKEN 7.8125 ms HCLK START UP STABLE CLOCK LH7A400-175 Figure 44. Signal Timing After Reset Preliminary data sheet Rev. 01 — 16 July 2007 55 LH7A400 32-Bit System-on-Chip NXP Semiconductors ENABLE INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 XTALIN Y1 XTALOUT 32.768 kHz R1 18 MΩ NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 12.5 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is ≤ 5%. C1 15 pF C2 18 pF GND GND RECOMMENDED CRYSTAL SPECIFICATIONS PARAMETER DESCRIPTION 32.768 kHz Crystal Tolerance Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part Parallel Mode ±30 ppm ±3 ppm 12.5 pF 50 kΩ 1.0 µW (MAX.) MTRON SX1555 or equivalent LH7A400-187 Figure 45. 32.768 kHz External Oscillator Components and Schematic 56 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors ENABLE INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 XTALIN Y1 XTALOUT 14.7456 MHz R1 1 MΩ C1 18 pF C2 22 pF GND GND RECOMMENDED CRYSTAL SPECIFICATIONS NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 18 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is ≤ 5%. PARAMETER DESCRIPTION 14.7456 MHz Crystal Tolerance Stability Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part (AT-Cut) Parallel Mode ±50 ppm ±100 ppm ±5 ppm 18 pF 40 Ω 100 µW (MAX.) MTRON SX2050 or equivalent LH7A400-188 Figure 46. 14.7456 MHz External Oscillator Components and Schematic Preliminary data sheet Rev. 01 — 16 July 2007 57 LH7A400 32-Bit System-on-Chip NXP Semiconductors Operating Temperature and Noise Immunity The junction temperature, Tj, is the operating temperature of the transistors in the integrated circuit. The switching speed of the CMOS circuitry within the SoC depends partly on Tj, and the lower the operating temperature, the faster the CMOS circuits will switch. Increased switching noise generated by faster switching circuits could affect the overall system stability. The amount of switching noise is directly affected by the application executed on the SoC. NXP recommends that users implementing a system to meet industrial temperature standards should use an external oscillator rather than a crystal to drive the system clock input of the System-on-Chip. This change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the SoC). Printed Circuit Board Layout Practices LH7A400 POWER SUPPLY DECOUPLING The LH7A400 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power to the core logic, and VDDA/VSSA supply analog power to the PLLs. Each of the VDD and VDDC pins must be provided with a low impedance path to the corresponding board power supply. Likewise, the VSS, VSSA, and VSSC pins must be provided with a low impedance path to the board ground. Each power supply must be decoupled to ground using at least one 0.1 µF high frequency capacitor located as close as possible to a VDDx, VSSx pin pair on each of the four sides of the chip. If room on the circuit board allows, add one 0.01 µF high frequency capacitor near each VDDx, VSSx pair on the chip. To be effective, the capacitor leads and associated circuit board traces connecting to the chip VDDx, VSSx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. There must be one bulk 10 µF capacitor for each power supply placed near one side of the chip. RECOMMENDED PLL, VDDA, VSSA FILTER The VDDA pins supply power to the chip PLL circuitry. VSSA is the ground return path for the PLL circuit. NXP recommends a low-pass filter attached as shown in Figure 47. The values of the inductor and capacitors are not critical. The low-pass filter prevents high frequency noise from adversely affecting the PLL circuits. The distance from the IC pin to the high frequency capacitor should be as short as possible. 58 VDDC (SOURCE) VDDC LH7A400 10 µH VDDA + 22 µF 0.1 µF VSSA LH7A400-189 Figure 47. VDDA, VSSA Filter Circuit UNUSED INPUT SIGNAL CONDITIONING Floating input signals can cause excessive power consumption. Unused inputs without internal pull-up or pull-down resistors should be pulled up or down externally (NXP recommends tying HIGH), to tie the signal to its inactive state. 33 KΩ or less is recommended. Some GPIO signals default to inputs. If the pins that carry these signals are unused, software can program these signals as outputs, eliminating the need for pullups or pull-downs. Power consumption may be higher than expected until software completes programming the GPIO. Some LH7A400 inputs have internal pullups or pull-downs. If unused, these inputs do not require external conditioning. OTHER CIRCUIT BOARD LAYOUT PRACTICES All outputs have fast rise and fall times. Printed circuit trace interconnection length must therefore be reduced to minimize overshoot, undershoot and reflections caused by transmission line effects of these fast output switching times. This recommendation particularly applies to the address and data buses. When considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. Capacitance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. Attention to power supply decoupling and printed circuit board layout becomes more critical in systems with higher capacitive loads. As these capacitive loads increase, transient currents in the power supply and ground return paths also increase. Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip LH7A400 NXP Semiconductors PACKAGE SPECIFICATIONS BGA256: plastic ball grid array package; 256 balls SOT1018-1 B D A D1 ball A1 index area E1 E A A2 A1 detail X e1 e ∅v ∅w b 1/2 e M M C C A B C y y1 C T R P N M e L K J e2 H G 1/2 e F E D C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 X 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D D1 E E1 e e1 e2 v w y y1 mm 1.95 0.5 0.3 1.45 1.25 0.55 0.45 17.2 16.8 15.75 14.75 17.2 16.8 15.75 14.75 1 15 15 0.25 0.1 0.15 0.35 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 07-07-07 07-07-07 SOT1018-1 Figure 48. Package outline SOT1018-1 (BGA256) Preliminary data sheet Rev. 01 — 16 July 2007 59 LH7A400 32-Bit System-on-Chip NXP Semiconductors LFBGA256: plastic low profile fine-pitch ball grid array package; 256 balls B D SOT1020-1 A ball A1 index area E A A2 A1 detail X e1 e ∅v ∅w b 1/2 e M M C C A B C y y1 C T R P N M L K J H G F E D C B A ball A1 index area e e2 1/2 e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 X 16 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.7 0.4 0.3 1.35 1.15 0.5 0.4 14.1 13.9 14.1 13.9 0.8 12 12 0.15 0.08 0.12 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 07-07-07 07-07-07 SOT1020-1 Figure 49. Package outline SOT1020-1 (LFBGA256) 60 Rev. 01 — 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 REVISION HISTORY Table 14. Revision history Document ID LH7A400_N_1 Release date Data sheet status 20070716 Preliminary data sheet Change notice - Supersedes FAST LH7A400 v1-5 5-9-07 Modifications: • First NXP version based on the LH7A400 data sheet of 20070509 Preliminary data sheet Rev. 01 — 16 July 2007 61 LH7A400 NXP Semiconductors 32-Bit System-on-Chip 1. Legal information 1.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 1.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 1.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 1.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] © NXP B.V. 2007. All rights reserved. IMPORTANT NOTICE Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use [email protected] (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Copyright © (year) by SHARP Corporation. is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via [email protected]). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document. NXP Semiconductors ANNEX A: Disclaimers (11) 1. t001dis100.fm: General (DS, AN, UM) General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: Right to make changes (DS, AN, UM) Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: Suitability for use (DS, AN, UM) Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 4. t001dis103.fm: Applications (DS, AN, UM) Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 5. t001dis104.fm: Limiting values (DS) Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 7. t001dis106.fm: No offer to sell or license (DS) No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable) Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. 9. t001dis108.2.fm: Bare die (DS; if applicable) Bare die (if applicable) — Products indicated as Bare Die are subject to separate specifications and are not tested in accordance with standard testing procedures. Product warranties and guarantees as stated in this document are not applicable to Bare Die Products unless such warranties and guarantees are explicitly stated in a valid separate agreement entered into by NXP Semiconductors and customer. 10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable) AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. 11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if applicable) Suitability for use in automotive applications only — This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.