IRF IR3527MTRPBF

IR3527
DATA SHEET
XPHASE3TM DUAL PHASE IC
DESCRIPTION
TM
The IR3527 Dual Phase IC combined with an IR XPhase3 Control IC provides a full featured and flexible
way to implement multiphase power solutions. The Control IC provides overall system control and interfaces
with any number of IR3527 Phase ICs which each drive and monitor 2 phases of a Synchronous Buck
converter.
The IR3527 implement an independent power savings function for each power stage and sequential phase
timing for use in single output multiphase converters. When power saving mode is enabled, the power stage
will disable its output thus eliminating its switching loss while proper converter operation is maintained by the
single power stage or in conjunction with other converter power stages. The IR3527 current sense amplifiers
remain active when in power savings to support adaptive voltage positioning.
FEATURES
x
x
x
x
x
x
x
x
x
x
x
x
7V/1.3A gate drivers (2.6A GATEL sink current)
Converter output voltage up to 5.1 V (Limited to VCCL-1.4V)
Loss-less inductor current sensing
Feed-forward voltage mode control
Integrated boot-strap synchronous PFET
Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
Single-wire bidirectional average current sharing
Only three external components per phase, plus common decoupling capacitors
Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads.
Debugging function isolates phase from the converter
Small thermally enhanced 24L 4 x 4mm MLPQ package
RoHS compliant
IC Bias
(7V)
PGND
RCS1
CCS2
RCS2
VCCL1
18
CBST2
12
L2
VOUT+
17
16
COUT
VOUT-
15
14
13
BOOST1
PSI2
GATEH1
GATEL1
SW1
CCS1
19
20
SW2
22
23
21
VCC
CSIN2+
GATEH2
GATEL2
PSI1
11
3 Wire
Digital
Phase
Timing
6
DACIN
CLKIN
Power
Savings
Control
IR3527 DUAL
PHASE IC
ISHARE
10
5
VCCL2
PHSOUT
4
EAIN
9
3
8
2
BOOST2
PHSIN
3 Wire
Analog
Bus
CSIN1+
7
1
CSIN2-
25
LGND
CSIN1-
24
VIN (12V)
L1
CBST1
CVCCL
CIN
‘
Figure 1 – IR3527 Application Circuit
Page 1 of 20
V3.0
IR3527
ORDERING INFORMATION
Part Number
IR3527MTRPBF
* IR3527MPBF
Package
24 Lead MLPQ
(4 x 4 mm body)
24 Lead MLPQ
(4 x 4 mm body)
Order Quantity
3000 per reel
100 piece strips
* Samples only
PIN DESCRIPTION
PIN#
1
2
PIN
SYMBOL
CSIN1+
EAIN
3
ISHARE
4
DACIN
5
PSI1
6
PSI2
7
PHSIN
8
9
10
PHSOUT
CLKIN
SW1
11
12
GATEH1
BOOST1
13
VCCL1
14
15
16
17
GATEL1
PGND
GATEL2
VCCL2
18
BOOST2
Page 2 of 20
PIN DESCRIPTION
Phase1 current sense amplifier non-inverting input and input to debug comparator
PWM comparator input from the error amplifier output of Control IC. Body Braking
mode is initiated if the voltage on this pin is less than V(DACIN) threshold.
Output of the Current Sense Amplifiers are connected to this pin through 3kŸ
resistors. Voltage on this pin is equal to approximately V(DACIN) + 16 [(VCSIN1+ –
VCSIN1-) + (VCSIN2+ – VCSIN2-)]. Connecting all Phase IC ISHARE pins together creates
a share bus which provides an indication of the average current being supplied by all
the phases. The signal is used by the Control IC for voltage positioning, over-current
protection, and in some cases current reporting. OVP mode is initiated if the voltage
on this pin rises above V(VCCL)- 0.8V.
Reference voltage input from the Control IC. The Current Sense signal and PWM
ramps are referenced to the voltage on this pin.
Input to Phase 1 PSI comparator. Logic low stops the phase from switching (low =
low power state)
Input to Phase 2 PSI comparator. Logic low stops the phase from switching (low =
low power state)
Phase timing clock input.
Phase timing clock output.
Clock input.
Return for Phase1 high-side driver and reference for GATEL1 non-overlap
comparator.
Phase1 High-side driver output and input to GATEL1 non-overlap comparator.
Supply for Phase1 high-side driver. Internal bootstrap synchronous PFET is
connected between this pin and the VCCL1 pin.
Supply for Phase1 low-side driver. Internal bootstrap synchronous PFET is
connected from this pin to the BOOST1 pin.
Phase1 Low-side driver output and input to GATEH1 non-overlap comparator.
Return for low side drivers and reference for GATEH non-overlap comparators.
Phase2 Low-side driver output and input to GATEH2 non-overlap comparator.
Supply for Phase2 low-side driver. Internal bootstrap synchronous PFET is
connected from this pin to the BOOST pin.
Supply for Phase2 high-side driver. Internal bootstrap synchronous PFET is
connected between this pin and the VCCL1 pin.
V3.0
IR3527
19
20
GATEH2
SW2
21
22
23
24
25
VCC
CSIN2+
CSIN2CSIN1LGND
Phase2 High-side driver output and input to GATEL2 non-overlap comparator.
Return for Phase2 high-side driver and reference for GATEL2 non-overlap
comparator.
Supply for internal IC circuits. Input to PWM feed-forward.
Phase2 current sense amplifier non-inverting input and input to debug comparator
Phase2 current sense amplifier inverting input
Phase1 current sense amplifier inverting input
Ground for internal IC circuits. IC substrate is connected to this pin.
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications are not implied. All voltages are absolute voltages referenced to the LGND pin.
o
Operating Junction Temperature…………….. 0 to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
PIN #
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1
2
3
4
5
6
7
8
9
10
CSIN1+
EAIN
ISHARE
DACIN
PSI1
PSI2
PHSIN
PHSOUT
CLKIN
SW1
8V
8V
8V
3.3V
8V
8V
8V
8V
8V
34V
GATEH1
40V
12
BOOST1
40V
13
VCCL1
8V
-0.3V
1mA
1mA
1mA
1mA
1mA
1mA
1mA
2mA
1mA
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
1A for 100ns,
100mA DC
n/a
1mA
1mA
1mA
1mA
1mA
1mA
1mA
2mA
1mA
n/a
11
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V DC, -5V for
100ns
-0.3V DC, -5V for
100ns
-0.3V
14
GATEL1
8V
15
PGND
0.3V
-0.3V DC, -5V for
100ns
-0.3V
16
GATEL2
8V
17
VCCL2
8V
-0.3V DC, -5V for
100ns
-0.3V
18
BOOST2
40V
-0.3V
Page 3 of 20
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
n/a
1A for 100ns,
100mA DC
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
n/a
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
3A for 100ns,
100mA DC
V3.0
IR3527
19
GATEH2
40V
20
SW2
34V
21
22
23
24
25
VCC
CSIN2+
CSIN2CSIN1LGND
34V
8V
8V
8V
n/a
-0.3V DC, -5V for
100ns
-0.3V DC, -5V for
100ns
-0.3V
-0.3V
-0.3V
-0.3V
n/a
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
n/a
1mA
1mA
1mA
n/a
3A for 100ns,
100mA DC
n/a
20mA
1mA
1mA
1mA
n/a
Note:
1. Maximum GATEHx – SWx = 8V
2. Maximum BOOSTx – GATEHx = 8V
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH
MARGIN
8.0V ” VCC ” 28V, 4.75V ” VCCL ” 7.5V, 0 C ” TJ ” 125 C
o
o
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25°C. 0.5V ”9'$&,1”9, 500kHz ”&/.,1”
9MHz, 250kHz ”3+6,1”0+]CGATEH = 3.3nF, CGATEL = 6.8nF (unless otherwise specified).
PARAMETER
Gate Drivers
GATEHx Source
Resistance
GATEHx Sink Resistance
GATELx Source Resistance
GATELx Sink Resistance
GATEHx Source Current
GATEHx Sink Current
GATELx Source Current
GATELx Sink Current
GATEHx Rise Time
GATEHx Fall Time
GATELx Rise Time
GATELx Fall Time
Page 4 of 20
TEST CONDITION
MIN
TYP
MAX
UNIT
BOOSTx – SWx = 7V. Note 1
1.3
3.3
Ÿ
BOOSTx – SWx = 7V. Note 1
VCCLx – PGND = 7V. Note 1
VCCLx – PGND = 7V. Note 1
BOOSTx=7V, GATEHx=2.5V, SW=0V.
Note 1
BOOSTx=7V, GATEHx=2.5V, SWx=0V.
Note 1
VCCLx=7V, GATELx=2.5V, PGND=0V.
Note 1
VCCLx=7V, GATELx=2.5V, PGND=0V.
Note 1
BOOSTx – SWx = 7V, measure 1V to 4V
transition time
BOOSTx - SWx = 7V, measure 4V to 1V
transition time
VCCLx – PGND = 7V, Measure 1V to 4V
transition time
VCCLx – PGND = 7V, Measure 4V to 1V
transition time
1.3
1.3
0.5
1.3
3.3
3.3
1.3
Ÿ
Ÿ
Ÿ
A
1.3
A
1.3
A
2.6
A
6
13
ns
6
13
ns
12
26
ns
6
13
ns
V3.0
IR3527
PARAMETER
GATELx low to GATEHx
high delay
GATEHx low to GATELx
high delay
Disable Pull-Down
Resistance
Clock & Daisy Chain
CLKIN Threshold
CLKIN Bias Current
CLKIN Phase Delay
PHSIN Threshold
PHSOUT Propagation
Delay
PHSIN Pull-Down
Resistance
PHSOUT High Voltage
PHSOUT Low Voltage
TEST CONDITION
BOOSTx = VCCLx = 7V, SWx = PGND = 0V,
measure time from GATELx falling to 1V to
GATEHx rising to 1V
BOOSTx = VCCLx = 7V, SWx = PGND =
0V, measure time from GATEHx falling to 1V
to GATELx rising to 1V
Note 1
MIN
10
TYP
20
MAX
40
UNIT
ns
10
20
40
ns
30
80
130
N
Compare to V(VCCLx)
CLKIN = V(VCCLx)
Measure time from CLKIN<1V to
GATEHx>1V
Compare to V(VCCLx)
Measure time from CLKIN > (VCCLx*50%)
o
to PHSOUT>(VCCLx*50%). [email protected] C
40
-0.5
40
45
0.0
75
57
0.5
125
PA
ns
35
4
50
15
55
35
%
ns
30
100
170
N
2
0.6
I(PHSOUT) = -5mA, measure VCCLx –
PHSOUT
I(PHSOUT) = 5mA
%
V
0.4
2
V
52.5
-0.3
57
5
65
75
mV/
%DC
PA
ns
20
80
160
ns
-1.0
-0.8
-0.4
V
15
40
70
ns
-340
-235
-130
-240
70
-135
105
-30
130
40
65
90
PWM Comparators
PWM Ramp Slope
Vin=12V
EAIN Bias Current
0 ”EAIN ” 3V
Minimum Pulse Width
Minimum GATEHx Turn-off
Time
OVP Comparator
Note 1
OVP Threshold
Step V(ISHARE) up until GATELx drives
high. Compare to V(VCCLx)
V(VCCLx)=5V, Step V(ISHARE) up from
V(DACIN) to V(VCCLx). Measure time to
V(GATELx)>4V.
Propagation Delay
42
-5
Body Brake Comparator
Threshold Voltage with
EAIN falling.
Threshold Voltage with
EAIN rising.
Hysteresis
Propagation Delay
Page 5 of 20
Measured relative to PWM Ramp Floor
Voltage
Measured relative to PWM Ramp Floor
Voltage
VCCLx = 5V. Measure time from EAIN <
V(DACIN) (200mV overdrive) to GATELx
transition to < 4V.
V3.0
mV
mV
mV
ns
IR3527
Current Sense Amplifiers
CSINx+/- Bias Current
CSINx+/- Bias Current
Mismatch
Input Offset Voltage
Gain
-200
0
200
nA
Note 1
-50
0
50
nA
CSINx+ = CSINx- = DACIN. Measure input
referred offset from DACIN
0.5V ”9'$&,19
-1
1
mV
30
32.5
35
V/V
4.8
6.8
8.8
MHz
-10
50
V/Ps
mV
-5
50
mV
Note 1
0
Note2
V
Note 1
2.3
3.0
3.7
kŸ
Rout at TJ = 125 C
3.6
4.7
5.4
kŸ
ISHARE Source Current
.5
1.7
2.9
mA
ISHARE Sink Current
.5
1.7
2.9
mA
Unity Gain Bandwidth
Slew Rate
Differential Input Range
Differential Input Range
Common Mode Input
Range
o
Rout at TJ = 25 C
C(ISHARE)=10pF. Measure at ISHARE.
Note 1
Note 1
0.8V ”9'$&,1”91RWH
0.5V ”9'$&,1 0.8V, Note 1
o
6
Share Adjust Amplifiers
Input Offset Voltage
Note 1
-3
0
3
mV
Gain
CSINx+ = CSINx- = DACIN.
3.6
4.7
5.8
V/V
Unity Gain Bandwidth
Note 1
4
8.5
17
kHz
-116
0
+116
mV
120
180
240
-220
-160
-100
mV
The ratio of V(CSINx-) / V(DACIN), below
which V(GATELx) is always low.
Negative Current Comparators
66
75
86
%
Input Offset Voltage
Note 1
-16
0
16
mV
Propagation Delay Time
Apply step voltage to V(CSINx+) – V(CSINx-).
Measure time to V(GATELx)< 1V.
100
200
400
ns
I(BOOSTx) = 30mA, VCCL=6.5V
360
520
960
mV
Compare to V(VCCLx)
-250
-150
-50
mV
PWM Ramp Floor Voltage
ISHARE unconnected
Measured Relative to DACIN
Maximum PWM Ramp
ISHARE = DACIN - 200mV
Floor Voltage
Measured relative to FLOOR with ISHARE
unconnected
Minimum PWM Ramp Floor ISHARE = DACIN + 200mV
Voltage
Measured relative to FLOOR with ISHARE
unconnected
Synchronous Rectification Disable Comparators
Threshold Voltage
mV
Bootstrap Diodes
Forward Voltage
Debug Comparators
Threshold Voltage
Page 6 of 20
V3.0
IR3527
PARAMETER
PSI Comparator
Rising Threshold Voltage
Falling Threshold Voltage
Hysteresis
Resistance
Floating Voltage
General
VCC Supply Current
VCC Supply Current
VCCLx Supply Current
MIN
TYP
MAX
UNIT
520
400
50
200
800
620
550
70
500
700
650
120
850
1150
mV
mV
mV
N
mV
2.2
2.2
3.1
8.0
4.0
8.0
12.2
8.0
12.1
mA
mA
mA
0.5
1.5
3
mA
DACIN Bias Current
-3.0
-1.5
1
PA
SW Floating Voltage
0.1
0.3
0.4
V
BOOSTx Supply Current
TEST CONDITION
8V”99&&”9
10V”99&&”9
4.75V ”9(BOOSTx)-V(SWX) ” 8V
Note 1: Guaranteed by design, but not tested in production
Note 2: VCCL-0.5V or VCC – 2.5V, whichever is lower
SYSTEM THEORY OF OPERATION
PWM Control Method
TM
The PWM block diagram of the XPhase3 architecture is shown in Figure 2. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain and wide-bandwidth voltage type error amplifier is used for the
voltage control loop. Input voltage is sensed by phase to monitor any changes in amplitude. The PWM ramp slope
will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage
can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related
to changes in load current.
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250 kHz to 9 MHZ
by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs.
The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output
(PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is
connected to PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of
the control IC.
The switching frequency is set by the Control IC. The clock frequency equals the total number of phases multiplied
by the switching frequency. During power up, the control IC sends out clock signals from both CLKOUT and
PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the
daisy chain loop.
The IR3527 combines 2 Phase ICs in a single package. IR3527 internally connect the PHSOUT1 pin to the PHSIN2
so the firing order is always sequential. Figure 3 shows the phase timing for a four phase converter implemented by
two IR3527 Phase ICs. The dotted lines indicate the PHSOUT1 to PHSIN2 waveform that would be internal to the
IR3527.
Page 7 of 20
V3.0
IR3527
GATE DRIVE
VOLTAGE
CONTROL IC
VIN
DUAL PHASE IC
PHSIN1
PHSOUT1
CLOCK GENERATOR
PWM LATCH1
CLKOUT
CLKIN
BOOST1
RESET
DOMINANT
CLK Q
D
PHSOUT
D
GATEH1
Q
CLK Q
PWM
COMPARATOR
EAIN
VCC
REMOTE SENSE
AMPLIFIER
VOUT
COUT
-
VCCL1
+
GND
GATEL1
ENABLE
+
+
VID6
BODY
BRAKING
COMPARATOR
PGND
VOSNS-
-
+
-
-
RAMP
DISCHARGE
CLAMP
VO
VOSNS+
CBST
SW1
R
PHSIN
VDAC
-
-
VDAC
EAOUT
-
CURRENT
SENSE
AMPLIFIER
VID6
VID6
+
3K
VID6
VID6 +
+
-
RCOMP
CCOMP1
RFB1
CCOMP
FB
RVSETPT
IVSETPT
IROSC
VDRP
AMP
CCS
RCS
CSIN1-
PHSIN2
CFB
PHSOUT2
PWM LATCH2
RDRP1
VSETPT
VDRP
+
DACIN
RFB
CSIN1+
-
+
SHARE ADJUST
ERROR AMPLIFIER
+
ISHARE
+
LGND
ERROR
AMPLIFIER
BOOST2
RESET
DOMINANT
CLK Q
RDRP
D
CDRP
D
GATEH2
Q
+
-
CLK Q
IIN
CBST
SW2
R
PWM
COMPARATOR
-
VCCL2
+
GATEL2
ENABLE
+
VID6
BODY
BRAKING
COMPARATOR
-
+
-
RAMP
DISCHARGE
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
SENSE
AMPLIFIER
VID6
VID6
+
-
VID6
VID6 +
+
CONTROL BUS TO
ADDITIONAL PHASES
CSIN2+
CCS
RCS
-
-
+
+
3K
CSIN2POWER BUS TO
ADDITIONAL PHASES
Figure 2 - PWM Block Diagram
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT &
IR3527 IC #1 PHSIN1
IR3527 IC #1 Phase 1
PWM Latch SET
IR3527 IC #1
PHSOUT1 & PHSIN2
IR3527 IC #1
PHSOUT2 & IC #2 PHSIN1
IR3527 IC #2
PHSOUT1 & PHSIN2
IR3527 IC #2 PHSOUT2
& Control IC PHSIN
Figure 3 - Four Phase Oscillator Waveforms implemented with two IR3527
Page 8 of 20
V3.0
IR3527
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is sets
and the PWM ramp voltage begins to increase. In conjunction, the low side driver is turned off and the high side driver is
turned on after the non-overlap time expires. When the PWM ramp voltage exceeds the error amplifier’s output voltage,
the PWM latch is reset. This turns off the high side driver, turns on the low side driver after the non-overlap time, and
activates the ramp discharge clamp. The clamp drives the PWM ramp voltage to the level set by the share adjust
amplifier until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to a 100% duty cycle in response to a load step increase
with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of
the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement
guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors
response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The
inductor current will increase much more rapidly than decrease in response to load transients. An additional advantage
of this PWM modulator is that differences in ground or input voltage at the phases have no effect on operation since the
PWM ramps are referenced to VDAC.
Figure 4 depicts PWM operating waveforms under various conditions.
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCCLUV, OCP, VID=11111X)
STEADY-STATE
OPERATION
Figure 4 - PWM Operating Waveforms
Body Braking
TM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
L * ( I MAX I MIN )
TSLEW
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
TSLEW
Page 9 of 20
L * ( I MAX I MIN )
VO VBODYDIODE
V3.0
IR3527
Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate
can be increased significantly. This patented technique is referred to as “body braking” and is accomplished through
the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output
voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor, as shown in Figure 5. The equation of the sensing network is,
vC ( s )
vL ( s )
1
1 sRCS CCS
iL ( s )
RL sL
1 sRCS CCS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
vL
iL
Current
Sense Amp
L
RL
RCS
CCS
VO
CO
c
vCS
CSOUT
Figure 5 - Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 5. Its gain is
nominally 32.5 and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback
path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and
other phases through an on-chip 3KŸUHVLVWRUFRQQHFWHGWRWKH,6+$5(SLQ7KH,6+$5(SLQVRIDOOWKHSKDVHVDUH
tied together and the voltage on the share bus represents the average current through all the inductors and is used
Page 10 of 20
V3.0
IR3527
by the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to
+/- 1mV in order to reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on ISHARE bus with a frequency of fsw/(32*28) in a multiphase architecture.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC.
The output of the current sense amplifier is compared with the average current at the share bus. If current in a
phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of
the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average
current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing
its duty cycle and output current. The current share amplifier is internally compensated so that the crossover
frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact.
IR3527 THEORY OF OPERATION
Block Diagram
A detailed IR3527 block diagram is enclosed (Figure 6) to help clearly illustrate the following theory of operation.
Tri-State Gate Drivers
The gate drivers can deliver up to 1.3A peak current (2.6A sink current for bottom driver). An adaptive non-overlap
circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while
minimizing body diode conduction. The non-overlap latch is added to eliminate the error triggering caused by the
switching noise. An enable signal is provided by the control IC to the phase IC without the addition of a dedicated
signal line. The error amplifier output of the control IC drives low in response to any fault condition such as VCCL
TM
under voltage or output overload. The IR3527 Body Braking comparator detects this and drives both gate outputs
low. This tri-state operation prevents negative inductor current and negative output voltage during power-down.
A synchronous rectification disable comparator is used to detect converter CSIN- pin voltage, which represents
local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL drives
low, which disables synchronous rectification and eliminates negative current during power-up.
The gate drivers pull low if the supply voltages are below the normal operating range. An 80kŸUHVLVWRULVFRQQHFWHG
across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to leakage or
other causes under these conditions.
Page 11 of 20
V3.0
IR3527
RMPOUT
-
D
200mV
+
100% DUTY
PWM_CLK1LATCH
S
Q1_100%DUT Y
D
D
PWM_CLK1
EAIN
3
+
4
VCCL
PWM COMPARATOR RMPOUT
PHSIN
PWM RAMP
GENERATOR
VCC
VCC
Q
PWM RESET
CALIBRATION
CLK
+
1V
GATEL NONOVERLAP
COMPARATOR
R
DACIN-SHARE_ADJ
-
S
GATEL NONOVERLAP
LATCH
D
Q
ANTI-BIAS
LATCH
BODY BRAKING
COMPARATOR
1V
S
SET R
DOMINANT
EAIN
100mV
200mV
-
SHARE_ADJ
VCCL
GATEL1
PGND
Q
+
R
RESET
DOMINANT
0.15V
SYNCHRONOUS RECTIFICATION
DISABLE COMPARATOR
S
-
NEGATIVE CURRENT
COMPARATOR
SHARE
ADJUST
AMPLIFIER
3K
CURRENT SENSE
AMPLIFIER
+
-
+
CSAOUT
+
+
DACIN
IROSC
DEBUG
COMPARATOR
CSIN1-
X32.5
+
+
-
CALIBRATION
VCCL1
-
DEBUG OFF
(LOW=OPEN)
DACIN
NEGATIVE
CURRENT
LATCH
OVP
COMPARATOR
0.8V
ISHARE
GATEL
DRIVER
+
+
DACIN +
SW
GATEH NONOVERLAP
COMPARATOR
SET R
DOMINANT
Q
GATEH1
-
2
GATEH NONOVERLAP
LATCH
RESET
DOMINANT
R
1
EAIN
Q
CLK Q
BOOST1
GATEH
DRIVER
PWMQ1
-
PWMQ1
CLK Q
PWM LATCH
+
PHSIN
Q1_100%DUTY
CLK Q
CLKIN
CSIN1+
X
0.75
CALIBRATION
1V
PSI
COMPARATOR
IROSC
VCCL
8CLK
Q
CLK
CLK
610mV
510mV
+
S
D
PWM_CLK2
-
2
+
3
PWM COMPARATOR
RMPOUT
PHSIN
D
Q
GATEH NONOVERLAP
LATCH
CLK Q
4
RESET
DOMINANT
VCCL
Q
PWM RAMP
GENERATOR
Q
CALIBRATION
D
+
1V
R
GATEL NONOVERLAP
COMPARATOR
1V
S
+
Q
SET R
DOMINANT
-
EAIN
100mV
GATEL
DRIVER
+
NEGATIVE
CURRENT
LATCH
200mV
SW2
-
S
GATEL NONOVERLAP
LATCH
ANTI-BIAS
LATCH
BODY BRAKING
COMPARATOR
GATEH2
GATEH NONOVERLAP
COMPARATOR
SET R
DOMINANT
CLK
DACIN-SHARE_ADJ
BOOST2
GATEH
DRIVER
PWM RESET
VCC
DACIN +
200mV
PWMQ2
R
1
EAIN
RMPOUT
PWM LATCH
CLK Q
PWMQ2
PHSOUT
Q2_100%DUTY
D
PWM_CLK2
PSI1
+
CLK Q
100% DUTY
LATCH
Q2_100%DUT Y
500K
-
VCCL
D
R
D
R
Q
VCCL2
GATEL2
-
SHARE_ADJ
Q
R
RESET
DOMINANT
DEBUG OFF
(LOW=OPEN)
0.15V
S
+
+
3K
CSAOUT
+
+
-
CALIBRATION
CURRENT SENSE
AMPLIFIER
-
+
IROSC
-
NEGATIVE CURRENT
COMPARATOR
SHARE
ADJUST
AMPLIFIER
DEBUG
COMPARATOR
CSIN2-
X32.5
+
CSIN2+
CALIBRATION
1V
IROSC
Q
D
CLK
CLK
R
D
8CLK
R
Q
VCCL
VCCL
PSI
COMPARATOR
500K
PSI2
+
610mV
510mV
LGND
Figure 6 – IR3527 Block diagram
Page 12 of 20
V3.0
IR3527
Over Voltage Protection (OVP)
The IR3527 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a
shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an excessive
output voltage. As shown in Figure 7, if ISHARE pin voltage is above V(VCCL) – 0.8V, which represents overvoltage condition detected by control IC, the over-voltage latch is set. GATEL drives high and GATEH drives low.
The OVP circuit overrides the normal PWM operation and within approximately 150ns will fully turn-on the low side
MOSFET, which remains ON until ISHARE drops below V(VCCL) – 0.8V when over voltage ends. The over voltage
fault is latched in control IC and can only be reset by cycling the power to control IC. The error amplifier output
(EAIN) is pulled down by control IC and will remain low. The lower MOSFETs alone can not clamp the output
voltage however an SCR or N-MOSFET could be triggered with the OVP output to prevent load damage.
OVP
THRESHOLD
OUTPUT
VOLTAGE
(VO)
VCCL-800 mV
ISHARE(IIN)
GATEH
GATEL
FAULT LATCH
(CONTROL IC)
ERROR
AMPLIFIER
INPUT
(EAIN)
VDAC
NORMAL OPERATION
OVP CONDITION
AFTER
OVP
Figure 7 - Over-voltage protection waveforms
PWM Ramp
Every time the phase IC is powered up PWM ramp magnitude is calibrated to generate a 52.5 mV/%DC (typical)
ramp for a VCC=12V. For example, for a 15% duty ratio the ramp amplitude is 787.5mV for VCC=12V. Feedforward control is achieved because the PWM ramp varies with VCC voltage proportionally after calibration.
Debugging Mode
If CSIN+ pin is pulled up to VCCL voltage, IR3527 enters into debugging mode. Both drivers are pulled low and
ISHARE output is disconnected from the current share bus, which isolates this phase IC from other phases.
However, the phase timing from PHSIN to PHSOUT does not change.
Page 13 of 20
V3.0
IR3527
Emulated Bootstrap Diode
IR3527 integrates a PFET to emulate the bootstrap diode. An external bootstrap diode connected from VCCL
pin to BOOST pin can be added to reduce the drop across the PFET but is not needed in most applications.
PSI Mode
In order to increases the efficiency under light load condition, the IR3527 employs a power state indicator (PSI)
signal to switch off the phase IC at light load. An active low on the PSI indicates the low power state and can be
used to switch off the phase IC. Once the PSI signal is asserted, the IR3527 waits for 8 PHSIN cycles to disable
the gate drives. When the PSI signal is de-asserted again the anti-bias latch circuit ensures that the topFET is
switched on first. The maximum de-assert delay is determined by the CLKIN period.
Operation at Higher Output Voltage
The proper operation of the phase IC is ensured for output voltage up to 5.1V. Similarly, the minimum VCC for
proper operation of the phase IC is 8 V. If the condition [VCCL •9DACIN + 35(VCSIN+x -VCSIN-x) + 1.4V] is violated,
the current sharing performance of the phase IC is affected.
APPLICATIONS INFORMATION
IR3527 EXTERNAL COMPONENTS
Inductor Current Sensing Capacitor CCS and Resistor RCS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and
capacitor CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore
the voltage across the capacitor CCS represents the inductor current. If the two time constants are not the
same, the AC component of the capacitor voltage is different from that of the real inductor current. The time
constant mismatch does not affect the average current sharing among the multiple phases, but does affect the
current signal ISHARE as well as the output voltage during the load current transient if adaptive voltage
positioning is adopted.
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS
as follows.
L RL
(1)
RCS
C CS
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
A 0.1uF-1uF decoupling capacitor is required at the VCCL pin.
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is
at least one decade lower than that of the voltage loop so that the interaction between the two loops is
eliminated. The crossover frequency of current share loop is approximately 8 kHz.
Page 14 of 20
V3.0
IR3527
IC Die Temperature
To ensure proper operation, the IC die should never operate at or above 150°C. For the vast majority of
applications, the IR3527 dual phase IC will not require any type of heat sink to achieve temperatures well
below 150°C. The IR3527 die is housed in a 24 lead MLPQ with exposed pad (Epad) which will provide
excellent thermal conduction. By soldering the Epad to a minimal copper area of 1”x 1”, the internal die
temperature will rise at a rate of approximately 30.5ƒ&: JA).
The die temperature can be derived by first calculating the power dissipation of the phase IC. The IC has two
types of conduction losses: quiescent current and driver losses. The quiescent losses are made up of VCC,
VCCL, and boost (VBST) supplies, while driving the top and bottom FETs contribute to the second loss.
The IC quiescent power losses can be calculated by the following equations:
Pvccl 2Vccl u Ivccl , Pvcc Vcc u Ivcc, and Pbst 2(Vbst u Ibst ) . Ivccl, Ivcc, and Ibst are the input
supplies quiescent currents which are listed in the Electrical Specifications Table. Driver power losses (PTOP
and PBOT) are equal to QG x VG x Fo, where QG is the FET’s gate charge, VG is the gate voltage, and Fo is the
operational frequency. Both top and bottom FET power losses needs to be calculated and doubled to account
for both internal drivers. Hence, the total phase IC power loss (PTOTAL) is: PVCCL + PVCC + PBST + 2(PTOP) +
2(PBOT).
The die temperature can now be calculated with the following formula:
TDIE
Where, TA is the ambient temperature and
package.
Page 15 of 20
JA
T JA u PTOTAL TA ,
is the junction to air thermal impedance of the 24 pin MLPQ
V3.0
IR3527
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the
PCB layout; therefore, minimizing the noise coupled to the IC.
x Separate analog bus (EAIN, DACIN, and IOUT) from digital bus (CLKIN, PSI, PHSIN, and PHSOUT) to
reduce the noise coupling.
x Place current sense resistors and capacitors (RCS and CCS) close to phase IC. Use Kelvin connection for
the inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor
terminal to CSIN- should not cross over the fast transition nodes, i.e., switching nodes, gate drive outputs,
and bootstrap nodes.
x Place the decoupling capacitors CVCC and CVCCL as close as possible to VCC and VCCL pins of the
phase IC respectively.
x Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and
inductance of the gate drive paths.
x Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET.
Use combination of different packages of ceramic capacitors.
x There are four switching power loops. Two loops include the input capacitors, top MOSFET, inductor,
output capacitors and the load; two other loops consist of bottom MOSFET, inductor, output capacitors and
the load. Route the switching power paths using wide and short traces or polygons; use multiple vias for
connections between layers.
Figure 8 - Layout Guidelines for IR3527
Page 16 of 20
V3.0
IR3527
PCB Metal and Component Placement
x Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be
•PPWRSUHYHQW shorting.
x Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
x Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be •PPIRUR]&RSSHU•PPIRUR]&RSSHUDQG•
0.23mm for 3 oz. Copper)
x Nine 0.3mm diameter vias shall be placed in the pad land spaced at 0.94 mm center to center, and
connected to ground to minimize the noise effect on the IC and to transfer heat to the PCB.
x No pcb traces should be routed nor Vias placed under any of the 4 corners of the IC package. Doing so
can cause the IC to raise up from the pcb resulting in poor solder joints to the IC leads.
Page 17 of 20
V3.0
IR3527
Solder Resist
x The solder resist should be pulled away from the metal lead lands and center pad by a minimum of
0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead
lands are all Non Solder Mask Defined (NSMD). Therefore, pulling the S/R 0.06mm will always ensure
NSMD pads.
x The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where the lead land
groups meet, it is recommended to provide a fillet so a solder resist width of •PPUHPDLQV
x Ensure that the solder resist in-between the lead lands and the pad land is • Pm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
x The 9 vias in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the
diameter of the via.
Page 18 of 20
V3.0
IR3527
Stencil Design
x The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm
pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.
x The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
x The land pad aperture should be 4 square openings of 1.1 mm sides and spaced at 0.2 mm to deposit
approximately 76% area of solder on the center pad. If too much solder is deposited on the center pad the
part will float and the lead lands will be open.
x The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the
lead lands when the part is pushed into the solder paste.
Page 19 of 20
V3.0
IR3527
PACKAGE INFORMATION
24L MLPQ (4 x 4 mm Body) –
JA
= 30.5oC/w
JC
= 1.8oC/W
Data and specifications subject to change without notice.
This product will be designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Page 20 of 20
V3.0