INTEGRATED CIRCUITS SA56600-42 System reset for lithium battery backup Product data Supersedes data of 2001 Apr 24 File under Integrated Circuits, Standard Analog 2001 Jun 19 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 GENERAL DESCRIPTION The SA56600-42 is designed to protect SRAM data in computer systems during periods of sagging power supply voltages and power outages. When the power supply voltage drops to typically 4.2 V, the CS output goes to a logic LOW state pulling CE to a LOW state, disabling the SRAM device. In addition, a reset logic LOW is asserted for system use. If the supply voltage drops further, to 3.3 V typically or lower, the SA56600-42 switches the system’s operation from the main power supply source to the Lithium back-up battery. As the main supply is restored and the voltage rises to 3.3 V or higher, the SRAM support voltage transfers from the Lithium back-up battery to the main supply. When the main supply voltage rises to greater than typically 4.2 V, the CS output goes to a logic HIGH state for SRAM CE control. Reset assertion is released and normal operation is resumed. This sequence ensures reliable preservation of SRAM data during periods of supply deficiency and interruptions. The SA56600-42 is offered in the SO8 surface mount package. FEATURES APPLICATIONS • Supply switching at 4.2 VDC threshold (falling supply) • RESET output • Both CS and CS outputs available for SRAM control • During battery back-up operation: • • Memory cards (SRAM) • PCs, word processors • FAX machines, photocopiers, office equipment • Sequence controllers • Video games and other equipment with SRAM – Low supply current (0.3 µA typical) – Low input/output voltage drop (0.3 V typical at 100 µA) – Low reverse current leakage (0.1 µA max.) During normal operation: – Low input/output voltage drop (0.2 V typical at 50 mA) – 4.8 V typical output voltage at 50 mA with VCC = 5.0 V – Restoration of main supply operation at 3.3 V SIMPLIFIED SYSTEM DIAGRAM 6 SA56600-42 VCC 8 4 VOUT VBATT VCC 3.3 V DETECTION CITCUIT 2 3 4.2 V DETECTION CITCUIT GND RESET CS VDD R RPU LITHIUM BATTERY SRAM CE GND 5 CS 1 7 SL01277 Y Figure 1. Simplified system diagram. ORDERING INFORMATION TYPE NUMBER SA56600-42D 2001 Jun 19 PACKAGE NAME DESCRIPTION TEMPERATURE RANGE SO8 plastic small outline package; 8 leads; body width 3.9 mm –40 to +85 °C 2 853–2249 26559 Philips Semiconductors Product data System reset for lithium battery back-up Part number marking SA56600-42 PIN CONFIGURATION TOP VIEW GND 1 RESET 2 8 VCC 7 Y SO8 CS 3 6 VOUT VBATT 4 5 CS 5 6 7 8 The package is marked with a four letter code in the first line to the right of the logo. The first three letters designate the product. The fourth letter, represented by ‘x’, is a date tracking code. The remaining two or three lines of characters are internal manufacturing codes. SL01278 4 3 2 1 Figure 2. Pin configuration. Part number Marking SA56600-42 AAA x PIN DESCRIPTION PIN SYMBOL DESCRIPTION 1 GND Circuit ground for the device. 2 RESET Asserted open collector output LOW whenever the VCC input source voltage falls below VS (4.2 V typical). The open collector topology requires an external pull-up resistor. 3 CS Chip select HIGH output signal, asserted whenever the VCC input source voltage is above VS (4.2 V typical). Can be used as a chip enable HIGH (CE) signal for system SRAM. 4 VBATT Positive polarity connection for lithium back-up battery. 5 CS Asserted chip select LOW output signal whenever the VCC input source voltage is above VS (4.2 V typical) and Y is grounded. Can be used as a chip enable LOW (CE) signal for system SRAM. 6 VOUT Primary power with lithium battery back-up power for the protected system. Switch over to lithium battery back-up operation occurs when VCC falls below VS. 7 Y Open Emitter input to microcontroller used to enable CS output (microcontroller controls CS function). 8 VCC Primary input power source for device. MAXIMUM RATINGS RATING UNIT VCC(max) SYMBOL Power supply voltage –0.3 to +7.0 V VCC(op) Operating voltage –0.3 to +7.0 V IO (VCC) Output current 80 mA IO (VBATT) Output current 200 µA Toper Operating temperature –40 to +85 °C Tstg Storage temperature –40 to +125 °C P Power dissipation 250 mW 2001 Jun 19 PARAMETER 3 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 ELECTRICAL CHARACTERISTICS Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC = 5.0 V; VBATT = 3.0 V; IO = 0 mA – 1.4 2.2 mA ICC Supply current VSAT1 I/O voltage difference 1 VCC = 5.0 V; VBATT = 3.0 V; IO = 1.0 mA – 0.03 0.05 V VO1 Output voltage 1 VCC = 5.0 V; VBATT = 3.0 V; IO = 1.0 mA 4.95 4.97 – V VO2 Output voltage 2 VCC = 5.0 V; VBATT = 3.0 V; IO = 15 mA 4.75 4.90 – V VS Detection threshold VCC falling 4.00 4.20 4.40 V ∆VS Detection hysteresis ∆VS = VSH (rising VCC) – VSL (falling VCC) – 100 – mA VRSL Reset output LOW VCC = 3.7 V – 0.2 0.4 V IRSH Reset leakage current HIGH VCC = 5.0 V; VRS = 7.0 V – ±0.01 ±0.1 µA VOPL Reset assertion (minimum operating voltage) VRSL ≤ 0.4 V; VCC falling; RPU = 10 kΩ – 0.8 1.2 V VCSL CS output voltage LOW VCC = 3.7 V; VBATT = 3.0 V; ICS = 1.0 µA – – 0.1 V VCSH CS output voltage HIGH VCC = 5.0 V; VBATT = 3.0 V; ICS = –1.0 µA 4.90 – – V VCSL CS output voltage LOW VCC = 5.0 V; VBATT = 3.0 V; ICS = 1.0 µA – – 0.2 V VCSH CS output voltage HIGH VCC = 3.7 V; VBATT = 3.0 V; ICS = –1.0 µA VO – 0.1 – – V ∆VS/∆T Detection voltage temperature characteristic –40 ≤ Tamb ≤ +85 – – ±0.05 %/°C VBT Battery back-up threshold VCC falling 3.15 3.30 3.45 V VBT(HYS) Battery back-up hysteresis VBT(HYS) = VBTH (VCC rising) – VBTL (VCC falling) – 100 1.0 mV VBT/∆T Switching voltage temperature characteristic –40 ≤ Tamb ≤ +85 – – ±0.05 %/°C IL Loss current VCC = 0 V; VBATT = 3.0 V; IO = 0 µA – 0.3 0.5 µA VSAT2 I/O voltage difference 2 VCC = 0 V; VBATT = 3.0 V; IO = 1.0 µA – 0.2 0.3 V VO3 Output voltage 3 VCC = 0 V; VBATT = 3.0 V; IO = 1.0 µA 2.7 2.8 – V VO4 Output voltage 4 VCC = 0 V; VBATT = 3.0 V; ICS = 100 µA 2.6 2.7 – V VREF Reference voltage (typical) – 1.25 – V IBL VBATT leakage current VCC = 5.0 V; VBATT = 0 V – – 0.1 µA IYLO Y current VCC = 5.0 V; VBATT = 3.0 V; VY = 0 V – 150 400 µA tPLH Y propagation delay time (Note 1) VY = logic LOW to logic HIGH – 8.0 20 ns tPHL Y propagation delay time (Note 1) VY = logic HIGH to logic LOW – 8.0 20 ns NOTE: 1. Y input rise and fall time less than 6.0 ns. 15 pF capacitance load on CS (Pin 5 to GND). 2001 Jun 19 4 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 TYPICAL PERFORMANCE CURVES 5.3 5.0 VCC = 5.0 V VBATT = 3.0 V 4.9 4.8 Tamb = 25 °C 4.7 VCC = 5.0 V VBATT = 3.0 V RESET, RESET, CS, CS = OPEN Y = GND 5.2 VOUT , OUTPUT VOLTAGE (V) VOUT , OUTPUT VOLTAGE (V) Tamb = –40 °C Tamb = 85 °C Tamb = 125 °C 4.6 5.1 IOUT = 0 mA 5.0 4.9 20 mA 40 mA 4.8 60 mA 4.7 80 mA 4.6 4.5 0 10 20 30 40 50 60 70 4.5 –50 80 –25 0 IOUT, OUTPUT CURRENT (mA) 25 50 75 100 SL01330 SL01332 Figure 3. Output voltage versus output current. Figure 4. Output voltage versus temperature. 3.0 VCC = 0 V VBATT = 3.0 V RESET, RESET, CS, CS = OPEN Y = GND 2.9 2.8 VO, OUTPUT VOLTAGE (V) VO, OUTPUT VOLTAGE (V) 3.0 VCC = 0 V VBATT = 3.0 V 2.9 Tamb = 125 °C 2.7 Tamb = 85 °C 2.6 2.5 Tamb = 25 °C 2.4 IOUT = 1.0 µA 2.8 200 µA 2.7 400 µA 2.6 600 µA 2.5 800 µA 2.4 1000 µA Tamb = –40 °C 2.3 0 200 400 600 800 2.3 –50 1000 –25 0 IO, OUTPUT CURRENT (mA) 25 50 75 100 SL01333 Figure 5. Output voltage versus current. 15 4.0 IBATT , BATTERY CURRENT (nA) ICC , SUPPLY CURRENT (mA) Figure 6. Output voltage versus temperature. VOUT = OPEN VBATT = 3.0 V Tamb = 25 °C 4.5 125 Tamb, TEMPERATURE (°C) SL01331 5.0 125 Tamb, TEMPERATURE (°C) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 IO = 0 mA VBATT = 3.0 V Tamb = 25 °C 10 5.0 0 –5.0 –10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 VCC, SUPPLY VOLTAGE (V) 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VCC, SUPPLY VOLTAGE (V) SL01334 SL01335 Figure 7. Supply current versus supply voltage. 2001 Jun 19 1.0 Figure 8. Battery current versus supply voltage. 5 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 150 4.25 VCC = FALLING VBATT = 3.0 V RESET, CS = OPEN Y = GND ∆ VS , DETECTION THRESHOLD (mV) VS , DETECTION THRESHOLD (V) 4.30 4.20 4.15 4.10 –50 –25 0 25 50 75 100 ∆VS = VSH – VSL (VCC = Rising then Falling) VBATT = 3.0 V RESET, CS, VOUT = OPEN Y = GND 125 100 75 50 –50 125 –25 0 Tamb, TEMPERATURE 〈°C) 25 50 75 100 SL01336 SL01337 Figure 9. Detection threshold versus temperature. Figure 10. Detection hysteresis versus temperature. 104 VBATT = 3.0 V VOUT = OPEN I OR, OUTPUT REVERSE CURRENT (nA) I CC , POWER SUPPLY CURRENT (mA) 3.00 2.75 2.00 1.75 1.50 1.25 1.00 –50 –25 0 25 50 75 100 125 Tamb, TEMPERATURE (°C) I BL, BATTERY LOSS CURRENT (nA) 103 102 101 0 25 50 75 100 125 Tamb, TEMPERATURE (°C) SL01334 Figure 13. Battery loss current versus temperature. 2001 Jun 19 102 101 100 –50 –25 0 25 50 75 100 125 Figure 12. Output reverse current versus temperature. VCC = 0 V VBATT = 3.0 V IOUT = 0 µA –25 103 SL01339 Figure 11. Power supply current versus temperature. 100 –50 VCC = 5.0 V VBATT = 0 V Tamb, TEMPERATURE (°C) SL01338 104 125 Tamb, TEMPERATURE (°C) 6 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 CS goes to a LOW logic state only when VCC is above 4.2 V plus hysteresis, and Y is simultaneously at a LOW logic state. If Y is not a LOW logic state (is open or at a HIGH logic state) CS will be at a HIGH logic state. Essentially, Y functions as a control switch for CS and is normally used as an input gating signal from the computer’s microprocessor. TECHNICAL DESCRIPTION The SA56600-42 provides battery back-up functions to protect SRAM data in computer memory systems. In addition, it provides RESET, Chip Select HIGH (CS), and Chip Select LOW (CS) outputs. The device incorporates a 3.3 V detection circuit, 4.2 V detection circuit, PNP switching transistor, and Schottky diode for low drop lithium battery connection to the output. Caution should be exercised in the application to keep the voltage on Y to less than 5.0 V when the VCC voltage is less than 4.2 V to avoid breaking down the Emitter-Base junction of the internal NPN transistor associated with Y. Breakdown of the junction may produce excessive current flow causing damage to the device. When the VCC voltage is less than 4.2 V, the base of the NPN transistor associated with the Y is at a LOW logic state and most susceptible to an overvoltage on Y. During power-up, RESET is actively asserted (LOW logic state) at VCC voltages as low as 0.8 V and does not output a release (HIGH logic state) until VCC attains 4.2 V plus hysteresis. CS, in a similar manner, only transitions to a HIGH logic state when VCC attains 4.2 V plus hysteresis. This ensures adequate voltage being present at the output of the SA56600 for proper operation of the associated computer system. Recovering primary VCC power is sensed by the 3.3 V detection circuit. The PNP switching transistor is activated when the applied VCC voltage reaches 3.3 V plus hysteresis. When this event occurs, the Schottky diode becomes back-biased, automatically disconnecting the lithium battery from the output and the SRAM is once again supported by the primary VCC power source. Full operation is restored when the applied primary VCC voltage reaches the required 4.2 V plus hysteresis value. This level is sensed by the 4.2 V detection circuit. RESET and CS are then caused to go to a HIGH logic state, and the computer memory is back in full operation without any loss of SRAM data. If the VCC voltage falls below 4.2 V, CS and RESET both go to a LOW logic state. During this time, with CS in a LOW logic state, no data ca be read from, or written to, the SRAM device. If the primary voltage (VCC) continues to fall to 3.3 V and below, the PNP switching transistor disconnects the primary input source power (VCC) from the output and the Schottky diode automatically couples the lithium battery power to the output of the SA56600 to supply sustaining power to the SRAM memory. The SA56600 provides complementary CS and CS outputs. The outputs differ in ways other than being simple complements of each other. The logic state of CS is strictly a function of VCC voltage. When VCC is above 4.2 V plus hysteresis, CS is in a HIGH logic state. When VCC is below 4.2 V, CS is in a LOW logic state. SA56600–42 VCC 6 4 8 R R 47 kΩ R R VOUT VOLTAGE TO SRAM VBATT PNP SWITCHING TRANSISTOR R R R R R R1 C1 R C2 R R LITHIUM BATTERY R GND R 47 kΩ R R R R 1 R 1 7 5 3 2 Y CS CS RESET GND R1 = OVERVOLTAGE CURRENT LIMITING RESISTOR C1, C2 = POWER SUPPLY BYPASS CAPACITOR SL01342 Figure 14. Functional diagram. 2001 Jun 19 7 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 Timing diagram The Timing Diagram shown in Figure 15 depicts the operation of the SA56600-42 in its intended application, with a 3.0 V Lithium battery serving as a backup power source for external SRAM circuitry (see the Simplified system diagram, Figure 1). Letters indicate events along the Time axis. F: As VCC continues to rise, RESET, CS, and VOUT also continue to rise. Just before ‘F’, Y is asserted HIGH by the microprocessing circuitry. This causes CS to change from a LOW state to a HIGH state. Following ‘F’ the microprocessing circuitry is signaling Y through repetitive cycles. This causes CS to also cycle, but has no effect on the battery circuit. A: At ‘A’, the VCC primary power source is off. As a result of the backup battery, the CS and VOUT outputs are almost up to the Lithium battery potential (VB). All other outputs (Y, RESET, and CS) are at or very near ground potential. G: At ‘G’, the VCC voltage begins to fall. As a result RESET, CS, and VCC fall. H: When the VCC voltage falls to VS (4.2 V) it is detected by the internal 4.2 V detector circuit. The detector circuit forces RESET and CS LOW, deselecting the SRAM and stopping data storage and retrieval. The PNP series pass switching transistor disconnects the primary input source voltage from the output, transferring the SRAM to the backup battery. In addition, because Y is already at a LOW state, CS rises abruptly close to VS followed by a continued fall to VB (Lithium battery potential), following VCC. B - C: At ‘B’, the VCC voltage begins to rise. Also the RESET voltage initially rises but then abruptly returns to a LOW state at ‘C’. when the VCC voltage reaches the level which activates the internal bias circuitry and asserts RESET to a logic LOW. This occurs at approximately 0.8 volts. D - E: At ‘D’ the internal 3.3 V detection circuit is activated when VCC voltage rises to 3.3 V. The circuit causes the PNP series pass switching transistor in the output to activate, connecting the main power supply voltage (VCC) to the output. This causes the Lithium battery to be automatically disconnected from VOUT by back-biasing the Schottky diode. As a result, CS and VOUT begin to rise with VCC. J: At ‘J’, VOUT has also fallen with VCC to a level that is now dictated by the Lithium battery potential. The Lithium battery is now maintaining the VOUT voltage to preserve the SRAM data. K - L: As the VCC voltage falls to a level which no longer allows the internal bias circuitry to remain active, the assertion of RESET can no longer be maintained. RESET rises slightly, then falls to ground as VCC falls to ground. E: At ‘E’, VCC has risen to the upper detection threshold (VS plus hysteresis) as sensed by the device’s internal 4.2 V detection circuit. This event signals that the output voltage is adequate to support full operation of the associated external computer circuitry. RESET goes HIGH, allowing the microprocessor circuitry to operate. Simultaneously, CS also goes HIGH, signaling the SRAM to start receiving data. CS goes LOW as a result of Y simultaneously being at a LOW state. M: Y is asserted HIGH again by the microprocessor, but because VCC is below VS, CS remains HIGH and CS remains LOW, preventing the SRAM from being selected. Y controls the CS output. As long as Y is LOW, the CS output is enabled. 5.0 VS VB VCC 0 VOPL Y 0 RESET VRSH VRSL 0 CS VCSL ≤VB VCSH 0 CS VCSH VCSL 0 VOUT VO1, O2 VO3, O4 0 A B C D E F G H J TIME Figure 15. Timing diagram. 2001 Jun 19 8 K L SL01341 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 PACKING METHOD GUARD BAND TAPE REEL ASSEMBLY TAPE DETAIL COVER TAPE CARRIER TAPE BARCODE LABEL BOX SL01305 Figure 16. Tape and reel packing method. 2001 Jun 19 9 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 SO8: plastic small outline package; 8 leads; body width 3.9 mm pin 1 index B2 1.73 4.95 4.80 0.51 0.33 0.068 0.189 0.195 0.013 0.020 4.95 4.80 SO8 2001 Jun 19 10 1.27 0.38 0.076 0.050 0.015 0.003 Philips Semiconductors Product data System reset for lithium battery back-up NOTES 2001 Jun 19 11 SA56600-42 Philips Semiconductors Product data System reset for lithium battery back-up SA56600-42 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 06-01 Document order number: 2001 Jun 19 12 9397 750 08448