INTEGRATED CIRCUITS 74LV4040 12-stage binary ripple counter Product specification IC24 Data Handbook 1998 Jun 23 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 FEATURES DESCRIPTION • Optimized for Low Voltage applications: 1.0 to 5.5V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, The 74LV4040 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT4040. The 74LV4040 is a 12-stage binary ripple counter with a click input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0 to Q11). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Tamb = 25°C • Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C • Frequency dividing circuits • Time delay circuits • Control counters • Output capability: standard • ICC category: MSI Each counter stage is a static toggle flip-flop. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns PARAMETER SYMBOL tPHL/tPLH Propagation delay CP to Q0 Qn to Qn+1 MR to Qn fmax Maximum clock frequency CI Input capacitance CPD CONDITIONS CL = 15pF VCC = 3.3V Power dissipation capacitance per gate Notes 1 and 2 TYPICAL UNIT 12 7 16 ns 100 MHz 3.5 pF 30 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40°C to +125°C 74LV4040 N 74LV4040 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV4040 D 74LV4040 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV4040 DB 74LV4040 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV4040 PW 74LV4040PW DH SOT403-1 1998 Jun 23 2 853-2075 19619 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 PIN CONFIGURATION LOGIC SYMBOL 9 Q0 Q11 Q5 2 15 Q10 Q4 3 14 Q9 Q6 4 13 Q7 Q3 5 12 Q8 Q2 6 11 MR Q1 7 10 CP GND 8 9 7 Q1 16 VCC 1 6 Q2 5 Q3 10 CP 11 MR Q4 3 Q5 2 Q6 4 Q7 13 Q8 12 Q9 14 Q10 15 Q0 1 Q11 SV00317 SV00316 Figure 1. Pin configuration Figure 3. Logic symbol PIN DESCRIPTION FUNCTIONAL DIAGRAM PIN NUMBER SYMBOL 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 Q0 to Q11 8 GND 10 CP FUNCTION Parallel outputs Ground (0V) Clock input (HIGH-to-LOW, edgetriggered) 11 MR Master reset input (active HIGH) 16 VCC Positive supply voltage 10 CP 11 MR T 12-STAGE COUNTER CD Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 9 5 3 2 4 13 12 14 15 7 5 1 LOGIC SYMBOL (IEEE/IEC) SV00319 CTR12 0 Figure 4. Functional diagram 9 7 10 + 11 CT=0 LOGIC DIAGRAM 5 5 3 2 CT 4 FF0 Q 13 CP 12 FF3 T T Q 14 FF11 Q Q T Q Q RD RD RD 15 11 1 MR SV00318 Figure 2. IEC Logic symbol Q0 Q1 Q11 SV00320 Figure 5. Logic diagram 1998 Jun 23 3 Philips Semiconductors Product specification 12-stage binary ripple counter 1 2 74LV4040 4 8 16 32 64 128 256 512 1.024 2.048 4.096 CP INPUT MR INPUT Q0 OUTPUT Q1 OUTPUT Q2 OUTPUT Q3 OUTPUT Q4 OUTPUT Q5 OUTPUT Q6 OUTPUT Q7 OUTPUT Q8 OUTPUT Q9 OUTPUT Q10 OUTPUT Q11 OUTPUT SV00310 Figure 6. Timing diagram FUNCTION TABLE INPUTS OUTPUTS CP MR Q0, Q3 to Q13 L no change L count X H L NOTES: H = HIGH voltage level L = LOW voltage level X = Don’t care = LOW -to-HIGH clock transition = HIGH-to-LOW clock transition 1998 Jun 23 4 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC DC supply voltage ±IIK DC input diode current ±IOK ±IO ±IGND, ±ICC Tstg PTOT CONDITIONS RATING UNIT –0.5 to +7.0 V VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 DC VCC or GND current for types with –standard outputs 50 Storage temperature range Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) –65 to +150 for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mA mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER VI Input voltage VO Output voltage Tamb tr, tf CONDITIONS MIN TYP. MAX UNIT See Note1 1.0 3.3 5.5 V 0 – VCC V 0 – VCC V +85 +125 °C 500 200 100 50 ns/V DC supply voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V –40 –40 – – – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 Jun 23 5 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 VOH VOL VOL HIGH level output voltage; g STANDARD outputs LOW level output voltage all outputs out uts voltage; LOW level output voltage; g STANDARD outputs MIN 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC UNIT MAX V 0.7*VCC VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage out uts voltage; all outputs MAX VCC = 1.2V VCC = 4.5 to 5.5 VOH -40°C to +125°C V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5V; VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 VCC = 4.5V; VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50 V V VCC = 1.2V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V; VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 VCC = 4.5V; VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65 V V Input leakage current VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; MSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 Jun 23 6 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 500W SYMBOL tPHL/tPLH tPHL/tPLH tPHL tW tW trem fmax PARAMETER Propagation delay CP to Q0 Propagation delay Qn to Qn+1 Propagation delay MR to Qn Clock pulse width HIGH to LOW Master reset pulse width HIGH Removal time MR to CP Maximum clock pulse frequency WAVEFORM TYP1 1.2 – 2.0 – MIN 60 – – – 27 43 – 54 19 31 – 38 162 26 – 32 4.5 to 5.5 – 13 17 – 22 1.2 – 40 – – – 2.0 – 18 29 – 54 2.7 – 13 21 – 38 3.0 to 3.6 – 112 18 – 32 4.5 to 5.5 – 73 12 – 22 1.2 – 55 – – – 2.0 – 27 44 – 54 2.7 – 19 31 – 38 3.0 to 3.6 – 162 26 – 32 4.5 to 5.5 – 113 17 – 22 2.0 35 7 – 41 54 2.7 25 5 – 30 – 3.0 to 3.6 20 42 – 24 – 4.5 to 5.5 15 33 – 18 – 2.0 35 11 – 41 – 2.7 25 9 – 30 – 3.0 to 3.6 20 82 – 24 – 4.5 to 5.5 15 73 – 18 – 1.2 – 10 – – – 2.0 22 5 – 26 – 2.7 16 4 – 19 – 3.0 to 3.6 13 32 – 15 – 4.5 to 5.5 10 23 – 12 – 2.0 14 60 – 12 – 2.7 19 76 – 16 – 3.0 to 3.6 24 942 – 20 – 4.5 to 5.5 36 1123 – 30 – Figure 8 7 UNIT MAX – NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. 1998 Jun 23 MAX – Figure 8, 9 Figure 7 MIN 2.7 Figure 7, 9 Figure 8 VCC(V) LIMITS –40 to +125 °C 3.0 to 3.6 Figure 7, 9 Figure 7 LIMITS –40 to +85 °C CONDITION ns ns ns ns ns ns MHz Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 AC WAVEFORMS VM = 1.5V at VCC 2.7V 3.6V VM = 0.5V * VCC at VCC 2.7V and 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. TEST CIRCUIT VCC VO VI PULSE GENERATOR 1/fmax D.U.T. VI 50pF RT CP INPUT CL VM RL = 1k GND tW Test Circuit for switching times tPLH tPHL DEFINITIONS VOH RL = Load resistor VM Qn OUTPUT CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VOL TEST VCC VI SV00322 tPLH/tPHL Figure 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency < 2.7V 2.7–3.6V VCC 2.7V SV00901 Figure 9.Load circuitry for switching times VI MR INPUT GND tW trem VI CP INPUT GND tPHL VOH Qn OUTPUT GND SV00908 Figure 8. Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time 1998 Jun 23 8 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 DIP16: plastic dual in-line package; 16 leads (300 mil) 1998 Jun 23 9 SOT38-4 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 Jun 23 10 SOT109-1 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 Jun 23 11 SOT338-1 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 Jun 23 12 SOT403-1 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 NOTES 1998 Jun 23 13 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 14 Date of release: 05-96 9397-750-04458