INTEGRATED CIRCUITS 74LV164 8-bit serial-in/parallel-out shift register Product specification Supersedes data of 1997 Mar 28 IC24 Data Handbook 1998 May 07 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register FEATURES 74LV164 DESCRIPTION • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, The 74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT164. The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Tamb = 25°C • Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (Dsa, Dsb) that existed one set-up time prior to the rising clock edge. • Gated serial data inputs • Asynchronous master reset • Output capability: standard • ICC category: MSI A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT 12 12 ns tPHL/tPLH Propagation delay CP to Qn MR to Qn fmax Maximum clock frequency 78 MHz CI Input capacitance 3.5 pF CPD Power dissipation capacitance per gate 40 pF CL = 15pF VCC = 3.3V VCC = 3.3V Notes 1 and 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL –40°C to +125°C 74LV164 N 74LV164 N SOT27-1 14-Pin Plastic SO –40°C to +125°C 74LV164 D 74LV164 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +125°C 74LV164 DB 74LV164 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +125°C 74LV164 PW 74LV164PW DH SOT402-1 1998 May 07 2 853–1961 19349 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL 1,2 Dsa, Dsb Data inputs 3, 4, 5, 6, 10, 11, 12, 13 Q0 to Q7 Outputs 7 GND FUNCTION Dsa 1 14 VCC Dsb 2 13 Q7 Q0 3 12 Q6 Q1 4 11 Q5 8 CP Clock input (LOW-to-HIGH, edge-triggered) Q2 5 10 Q4 9 MR Master reset input (active LOW) Q3 6 9 MR 14 VCC Positive supply voltage GND 7 8 CP Ground (0V) LOGIC SYMBOL (IEEE/IEC) SV00381 SRG8 LOGIC SYMBOL 8 C1/ 9 R 1 Q0 3 Q1 4 Q2 5 Q3 6 Q4 10 Q5 11 Q6 12 Q7 13 2 & 1D 3 1 4 Dsa Dsb 5 2 6 10 8 9 CP 11 12 13 MR SV00383 SV00382 1998 May 07 3 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 FUNCTIONAL DIAGRAM FUNCTION TABLE OPERATING MODES Dsa Dsb Q0 Reset (clear) L X x x L L–L Shift H H H H ↑ ↑ ↑ ↑ l l h h l h l h L L L H q0 – q6 q0 – q6 q0 – q6 q0 – q6 1 2 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER CP 8 H h MR 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L l 3 4 5 6 10 11 12 13 q ↑ SV00384 OUTPUTS CP Dsa Dsb INPUTS MR Q 1 – Q7 = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = Lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition = LOW-to-HIGH clock transition ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +7.0 V ±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA ±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA ±IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 ±IGND, ±ICC Tstg PTOT DC VCC or GND current for types with –standard outputs 50 Storage temperature range Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) –65 to +150 for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mA mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER DC supply voltage CONDITIONS MIN TYP. See Note 1 MAX UNIT 1.0 3.3 5.5 V VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 50 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V – – – – – – – – NOTES: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 May 07 4 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 VOH VOL VOL HIGH level output voltage; g STANDARD outputs LOW level output voltage all outputs out uts voltage; LOW level output voltage; g STANDARD outputs MIN 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC UNIT MAX V 0.7*VCC VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage out uts voltage; all outputs MAX VCC = 1.2V VCC = 4.5 to 5.5 VOH -40°C to +125°C V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5V;VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0V;VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 VCC = 4.5V;VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50 V V VCC = 1.2V; VI = VIH or VIL; IO = 100µA VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 VCC = 4.5V;VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65 V V Input leakage current VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; MSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA II NOTES: 1. All typical values are measured at Tamb = 25°C. 1998 May 07 5 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL tPHL/tPLH tPHL tW tW trem tsu th fmax PARAMETER Propagation delay CP to Qn Propagation delay MR to Qn Clock pulse width HIGH to LOW Master reset pulse width; LOW Removal time MR to CP Set-up Set up time Dsa, Dsb to CP Hold time Dsa, Dsb to CP Maximum clock pulse frequency WAVEFORM TYP1 1.2 – 2.0 – MIN 75 – – – 26 39 – 49 19 29 – 36 142 23 – 29 4.5 to 5.5 – 122 19 – 24 1.2 – 75 – – – 2.0 – 26 39 – 49 2.7 – 19 29 – 36 3.0 to 3.6 – 142 23 – 29 4.5 to 5.5 – 122 19 – 24 2.0 34 9 – 41 – 2.7 25 6 – 30 – 3.0 to 3.6 20 52 – 24 – 4.5 to 5.5 13 42 2.0 34 10 – 41 – 2.7 25 8 – 30 – 20 62 – 24 – 4.5 to 5.5 13 52 1.2 – 30 – – – 2.0 19 10 – 24 – 2.7 14 8 – 18 – 3.0 to 3.6 11 62 – 14 – 4.5 to 5.5 8 52 1.2 – 15 – – – 2.0 22 5 – 26 – 2.7 16 4 – 19 – 3.0 to 3.6 13 32 – 15 – 4.5 to 5.5 9 22 1.2 – –10 – – – 2.0 5 –3 – 5 – 2.7 5 –2 – 5 – 3.0 to 3.6 5 –22 – 5 – 4.5 to 5.5 5 –12 2.0 14 40 – 12 – 2.7 19 58 – 16 – 3.0 to 3.6 24 702 – 20 – 4.5 to 5.5 36 1002 Figure 3 6 ns ns ns 16 3.0 to 3.6 Figure 3 UNIT MAX – NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. 1998 May 07 MAX – Figure 2 Figure 1 MIN 2.7 Figure 2 Figure 2 VCC(V) LIMITS –40 to +125 °C 3.0 to 3.6 Figure 1 Figure 1 LIMITS –40 to +85 °C CONDITION ns 16 ns 10 ns 10 ns 5 30 MHz Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 AC WAVEFORMS VM = 1.5V at VCC 2.7V 3.6V VM = 0.5V * VCC at VCC 2.7V and 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. Vl CP INPUT GND VM ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ t su t su th Vl 1/fmax Dn INPUT VI GND CP INPUT VM th VM VOH GND tw Qn OUTPUT tPLH tPHL VM VOL VOH Qn OUTPUT VM VOL SV00353 Figure 3. Data set-up and hold times for the Dn inputs NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SV00351 Figure 1. The clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency TEST CIRCUIT Vcc MR INPUT VO Vl Vi PULSE GENERATOR D.U.T. VM 50pF RT CL RL= 1k GND tw trem Test Circuit for Outputs Vi DEFINITIONS RL = Load resistor VM CP INPUT CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to ZOUT of pulse generators. GND tPHL TEST VOH tPLH/tPHL Qn OUTPUT VM VOL VCC VI < 2.7V VCC 2.7–3.6V 2.7V ≥ 4.5 V VCC SV00902 Figure 4. Load circuitry for switching times SV00352 Figure 2. The master reset (MR) pulse width, the master reset to output (Qn) propagation delay and the master reset to clock (CP) removal time 1998 May 07 7 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 DIP14: plastic dual in-line package; 14 leads (300 mil) 1998 May 07 8 SOT27-1 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1998 May 07 9 SOT108-1 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1998 May 07 10 SOT337-1 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1998 May 07 11 SOT402-1 Philips Semiconductors Product specification 8-bit serial-in/parallel-out shift register 74LV164 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 May 07 12 Date of release: 05-96 9397-750-04431