Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register FEATURES • Edge triggered output register • ypical access time of 19.5ns • Optimize for register stack operation • 3–state outputs • 18–pin package The 74F410 is fully compatible with all TTL families. TYPE 74F410 TYPICAL ACCESS TIME TYPICAL SUPPLY CURRENT ( TOTAL) 19.5ns 45mA DESCRIPTION FUNCTIONAL DESCRIPTION The 74F410 is a register oriented high speed 64–bit read/write memory organized as 16–words by 4–bits. An edge–triggered 4–bit output register allows new input data to be written while previous data is held. 3–state outputs are provided for maximum versatility. Write operation – When the three control inputs, write enable (WE), chip select (CS), and clock (CP), are low the information on the data inputs (D0–D3) is written into the memory location selected by the address inputs (A0–A3). If the input data changes 74F410 while WE, CS, and CP are low, the contents of the selected memory location follow these changes provided setup and hold time criteria are met. Read operation – When CS is low, WE is high, and CP goes from low–to–high, the contents of the memory location selected by the address inputs (A0–A3) are edge– triggered into the output register. When WE is low, CS is low, CP goes from low–to–high, the data at the data inputs is edge–triggered into the output register. The OE input controls the output buffers. When OE is high the four outputs (Q0–Q3) are in a high impedance or off state; when OE is low, the outputs are determined by the state of the output register. ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 18–pin plastic DIP (300mil) N74F410N INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 – D3 Data inputs 1.0/1.0 20µA/0.6mA A0 – A3 Address inputs 1.0/1.0 20µA/0.6mA CP Clock pulse input (active rising edge) 1.0/2.0 20µA/1.2mA CS Chip select input (active low) 1.0/2.0 20µA/1.2mA OE Output enable input (active low) 1.0/1.0 20µA/0.6mA WE Write enable input (active low) 1.0/1.0 20µA/0.6mA 150/40 3mA/24mA Q0 – Q3 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION LOGIC SYMBOL 17 15 13 11 CS 1 18 V CC WE 2 17 D0 A0 3 16 Q0 A1 4 15 D1 A2 5 14 Q1 A3 6 13 D2 CP 7 12 Q2 OE 8 11 D3 GND 9 10 Q3 D0 D1 D2 D3 3 4 5 6 1 2 7 8 A0 A1 A2 A3 CS WE CP OE 3 4 5 6 2 0 A 7 0 15 1 & 1 G1 1C & G2 8 Q0 Q1 Q2 Q3 17 16 14 12 10 VCC = Pin 18 GND = Pin 9 January 8, 1990 IEC/IEEE SYMBOL 1 EN3 A1,2D A3 16 15 14 13 12 11 10 853-1310 98498 Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 LOGIC DIAGRAM 8 OE A0 A1 A2 A3 D0 D1 D2 D3 3 4 5 Address decoder 16 RAM 6 17 4 16 Q0 15 14 13 Data inputs 11 16 Q1 Register 12 Q2 10 15 Q3 WE 13 CS 11 CP VCC = pin 18 GND = pin 9 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL RATING UNIT VCC Supply voltage PARAMETER –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state 48 mA Tamb Operating free air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C January 8, 1990 2 Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS T UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High–level input voltage 2.0 VIL Low–level input voltage 0.8 IIk Input clamp current –18 IOH High–level output current –3 IOL Low–level output current 24 Tamb Operating free air temperature range 0 A = – V 4 0 V t V o + mA 8 5 mA ° mA C °C +70 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN VOH High-level output voltage TYP2 UNIT MAX ±10%VCC 2.4 V VIH = MIN, IOH = MAX ±5%VCC 2.7 V VCC = MIN, VIL = MAX ±10%VCC VIH = MIN, IOL = MAX ±5%VCC VCC = MIN, VIL = MAX VOL Low-level output voltage VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High–level input current VCC = MAX, VI = 2.7V 20 µA IIL Low–level input current VCC = MAX, VI = 0.5V -0.6 mA -1.2 mA IOZH Offset–output current, high–level voltage applied VCC = MAX, VI = 2.7V 50 µA IOZL Offset–output current, low–level voltage applied VCC = MAX, VI = 0.5V –50 µA IOS Short-circuit output current3 VCC = MAX -150 mA others CP, CS -60 0.35 0.50 V 0.35 0.50 V -0.73 -1.2 V 100 µA ICC Supply current (total) VCC = MAX 45 70 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. January 8, 1990 3 Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V CL = 50pF, RL = 500Ω VCC = +5.0V ± 10% UNIT CL = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation dealy CP to Qn Waveform 1 4.0 4.5 6.5 6.5 8.5 9.0 3.5 4.0 9.5 10.0 ns tPZH tPZL Output enable time OE to Qn Waveform 3, 4 3.0 4.5 4.5 6.0 7.5 9.0 2.5 3.5 8.5 9.5 ns tPHZ tPHL Output disable time OE to Qn Waveform 3, 4 2.0 2.0 3.5 3.5 6.0 6.5 1.5 2.0 6.5 7.0 ns AC SETUP REQUIREMENTS FOR READ MODE LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION CL = 50pF, RL = 500Ω MIN CP1 Tamb = 0°C to +70°C VCC = +5.0V TYP VCC = +5.0V ± 10% UNIT CL = 50pF, RL = 500Ω MAX MIN MAX tsu(L) Setup time, low, CS to Waveform 1 4.0 4.5 ns th(L) Hold time, low, CS to CP1 Waveform 1 3.5 4.5 ns tsu(H) tsu(L) Setup time, high or low An to CP1 Waveform 1 13.0 13.0 15.0 15.0 ns th(H) th(L) Hold time, high or low An to CP1 Waveform 1 0 0 0 0 ns tsu(H) Setup time, high, WE to CP1 Waveform 1 13.0 15.0 ns Waveform 1 0 0 ns Waveform 1 5.0 6.0 ns th(H) Hold time, high, WE to CP1 tw(L) CP pulse width, low NOTE: 1. Low–to–high clock transition. AC SETUP REQUIREMENTS FOR WRITE MODE LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500Ω MIN tsu(H) tsu(L) Setup time, high or low An to WE, CS, CP th(H) th(L) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% UNIT CL = 50pF, RL = 500Ω MIN MAX Waveform 2 0 0 0 0 ns Hold time, high or low An to WE, CS, CP Waveform 2 0 0 0 0 ns tsu(H) tsu(L) Setup time, high or low Dn to WE, CS, CP Waveform 2 6.0 6.0 8.0 8.0 ns th(H) th(L) Hold time, high or low Dn to WE, CS, CP Waveform 2 0 0 0 0 ns tw(L) WE pulse width, low Waveform 2 7.0 8.0 ns tw(L) CS pulse width, low Waveform 2 6.0 7.0 ns tw(L) CP pulse width, low Waveform 2 7.0 8.0 ns January 8, 1990 4 Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 AC WAVEFORMS CS tsu(L) WE VM VM VM th(L) VM VM VM Qn Waveform 3. 3-State output enable time to high level and output disable time from high level th(H) th(L) tsu(H) VM VM tw(H) OE tPZL tPLZ VM Qn VOL +0.3V Waveform 1. Read cycle timing VM Waveform 4. 3-State output enable time to low level and output disable time from low level VM th(L) tsu(L) VM VM VM VM VM VM tPLH Qn CS WE CP VM 0V VM tPHL An, Dn VOH -0.3V tPHZ th(H) tsu(H) tsu(H) CP VM tPZH VM th(H) tsu(L) VM tsu(L) VM VM OE th(L) VM An VM VM tsu(H) th(H) VM VM tw(L) VM VM Waveform 2. Write cycle timing NOTES: 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN NEGATIVE PULSE CL RL AMP (V) VM 10% D.U.T. RT 90% VM RL VOUT PULSE GENERATOR tW 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% Test circuit for 3–state outputs SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value RT = Termination resistance should be equal to ZOUT of pulse generators. January 8, 1990 POSITIVE PULSE VM VM 10% 10% tW 0V Input pulse definition INPUT PULSE REQUIREMENTS family 74F 5 amplitude VM rep. rate 3.0V 1.5V 1MHz tW tTLH 500ns 2.5ns tTHL 2.5ns