Document No. 001-97466 Rev. *B ECN# 4803216 Cypress Semiconductor Automotive Product Qualification Report QTP# 143501 VERSION *B June, 2015 1Mbit and 2-Mbit Serial (Parallel) Automotive F-RAM 130nm Technology, Texas Instruments DMOS5 Fab CY15B101N-ZS60XA 64K x16 Parallel 1Mbit Automotive F-RAM Memory, -40C to + 85C CY15B102N-ZS60XA 128K x16 Parallel 2Mbit Automotive F-RAM Memory, -40C to + 85C FOR ANY QUESTIONS ON THIS REPORT, PLEASE CONTACT [email protected] or via a CYLINK CRM CASE Prepared By: Becky Thomas Reliability Engineer Reviewed By: Zhaomin Ji Reliability Manager Approved By: Don Darling Reliability Director Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 1 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 PRODUCT QUALIFICATION HISTORY QTP Number Description of Qualification Purpose Date 02-60-5112 / 124901 TI Process Qualification 130nm F-RAM Process Aug 2008 / Dec 2012 133705 New Product Qualification, 1Mbit and 2Mbit SPI and Parallel F-RAM Memory (Industrial, -40C to +85C) Aug 2014 133505 143501 New Automotive Product Qualification, 2Mbit SPI F-RAM Memory (-40C to +125C) New Automotive Product Qualification 1Mbit and 2Mbit Parallel F-RAM Memory (-40C to +85C) Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 2 of 16 May 2015 May 2015 Document No. 001-97466 Rev. *B ECN# 4803216 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: New (-40C to +85C) Automotive Product Qualification of the 1Mbit and 2Mbit Parallel F-RAM Memory Automotive Marketing Part #: CY15B101N-ZS60XA and CY15B102N-ZS60XA Device Description: Automotive 1Mbit and 2Mbit Parallel F-RAM Memory, -40C to +85C Cypress Division: Cypress Semiconductor Corporation – Memory Products Division (MPD) TECHNOLOGY/FAB PROCESS DESCRIPTION Number of Metal Layers: Proprietary* Metal Composition: Passivation Type and Thickness: Proprietary* Proprietary* Generic Process Technology/Design Rule (-drawn): CMOS / 130nm Gate Oxide Material/Thickness (MOS): Proprietary* Name/Location of Die Fab (prime) Facility: Texas Instruments / Dallas Die Fab Line ID/Wafer Process ID: DMOS 5 / E035.1 *Texas Instruments’ proprietary information is available with signed NDA. PACKAGE AVAILABILITY PACKAGE 44-LD (400-mil) TSOPII ASSEMBLY FACILITY SITE JCET-JT Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 3 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION (QTP#143501) Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: ZW44B Mold Compound Flammability Rating: 44-LD TSOPII (400-mil) KE G6000 / Kyocera UL-94 V-0 Mold Compound Alpha Emission Rate: <0.1 Oxygen Rating Index: >28% 70 Lead Frame Designation: FMP Lead Frame Material: Copper Substrate Material: N/A Die Backside Preparation Method/Metallization: NiPd/Au / Ni = 20-80microinches, Pd = >0.8 microinches, Au = 0.2-0.5 microinches Backgrind Die Separation Method: Laser Groove / Saw Die Attach Supplier: Henkel Die Attach Material: QMI-509 Bond Diagram Designation 001-92845 Wire Bond Method: Thermosonic Wire Material/Size: Au / 0.8 mil Thermal Resistance Theta JA C/W: 107 C/W Package Cross Section Yes/No: Yes Assembly Process Flow: 001-93367 Name/Location of Assembly (prime) facility: CML-RA MSL LEVEL 3 REFLOW PROFILE 260C Lead Finish, Composition / Thickness: ELECTRICAL TEST / FINISH DESCRIPTION Test Location: CML, Philippines Note: Please contact a Cypress Representative for other package availability. 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Page 4 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS Stress/Test Test Condition (Temp/Bias) Result P/F Electrostatic Discharge Human Body Model (ESD-HBM) Electrostatic Discharge Charge Device Model (ESD-CDM) Latchup Sensitivity Data Retention (Plastic ) High Temperature Operating Life Early Failure Rate AEC-Q100-002, 500V, 1,000V, 2,000V P AEC-Q100-011 250V, 500V, 750V (corner pins) P AEC-Q100-004, +/-140mA, 5.4V Over-Voltage 150 C, non-biased P AEC-Q100-008 and JESD22-A108, 125C Dynamic Operating Condition, Vcc = 3.60V, P High Temperature Operating Life Latent Failure Rate JESD22-A108, 125 C Dynamic Operating Condition, Vcc = 3.60, 125 C P High Accelerated Saturation Test (HAST) JESD22-A110,130 C, 85%RH, 3.60V Precondition: JESD22-A113 Moisture Sensitivity Level (192 Hrs., 30 C, 60% RH) JESD22- A104, -65 C to 150 C Precondition: JESD22-A113 Moisture Sensitivity Level (192 Hrs., 30 C, 60% RH) Mil-Std 883, Method 2011 P P Wire Bond Shear JESD22-A102, 121 C, 100%RH, 15 PSIG Precondition: JESD22-A113 Moisture Sensitivity Level (192 Hrs., 30 C, 60% RH) AEC Q100-001 Wire Bond Pull Mil-Std 883, Method 2011 P Solderability JESD22-B102 P Physical Dimensions JESD22B100 and B108 P Electrical Distributions AEC Q100-009 P Temperature Cycle Post Temperature Cycle Wire Bond Pull Pressure Cooker Test Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 5 of 16 P P P P Document No. 001-97466 Rev. *B ECN# 4803216 RELIABILITY FAILURE RATE SUMMARY Stress/Test Device Tested/ Device Hours # Fails Activation Energy Thermal AF3 Failure Rate High Temperature Operating Life Early Failure Rate 11,967 Devices 0 N/A N/A 0 PPM High Temperature Operating Life1,2 Long Term Failure Rate 547,000 DHRs* 0 0.7 55 21 FITs 231,000 DHRs *Leverage HTOL data from TI 130nm F-RAM Process QTP#124901 (SPEC#001-85093) 1 2 3 Assuming an ambient temperature of 55C and a junction temperature rise of 15C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation E 1 1 AF = exp A - k T 2 T1 where: EA =The Activation Energy of the defect mechanism. K = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 6 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 143501 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: ESD-HUMAN BODY CIRCUIT (500V) FM28V202A-TG 4422645 611425695 CML-RA Room 3 0 FM28V202A-TG 4422645 611425695 CML-RA Hot 3 0 STRESS: ESD-HUMAN BODY CIRCUIT (1000V) FM28V202A-TG 4422645 611425695 CML-RA Room 3 0 FM28V202A-TG 4422645 611425695 CML-RA Hot 3 0 STRESS: ESD-HUMAN BODY CIRCUIT (2000V) FM28V202A-TG 4422645 611425695 CML-RA Room 3 0 FM28V202A-TG 4422645 611425695 CML-RA Hot 3 0 STRESS: ESD- CHARGED DEVICE MODEL (250V) FM28V202A-TG 4422645 611425695 CML-RA Room 3 0 FM28V202A-TG 4422645 611425695 CML-RA Hot 3 0 STRESS: ESD- CHARGED DEVICE MODEL (500V) FM28V202A-TG 4422645 611425695 CML-RA Room 3 0 FM28V202A-TG 4422645 611425695 CML-RA Hot 3 0 STRESS: ESD- CHARGED DEVICE MODEL (750V)- corner pins FM28V202A-TG 4422645 611425695 CML-RA Room 3 0 FM28V202A-TG 4422645 611425695 CML-RA Hot 3 0 STRESS: HIGH TEMPERATURE OPERATING LIFE- EARLY FAILURE RATE (125C, 96 hours, 3.60V) CY15B102N-ZS60XA 4502179 611503332 CML-RA Room 2962 0 CY15B102N-ZS60XA 4502179 611503332 CML-RA Hot 2962 0 CY15B102N-ZS60XA 4502179 611503332N1 CML-RA Room 1000 0 CY15B102N-ZS60XA 4502179 611503332N1 CML-RA Hot 1000 0 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 7 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 143501 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: HIGH TEMPERATURE OPERATING LIFE- EARLY FAILURE RATE (125C, 96 hours, 3.60V) (cont) CY15B102N-ZS60XA 611505901 611503332N1 CML-RA Room 4002 0 CY15B102N-ZS60XA 611505901 611503332N1 CML-RA Hot 4002 0 CY15B102N-ZS60XA 4507661 611505900 CML-RA Room 4003 0 CY15B102N-ZS60XA 4507661 611505900 CML-RA Hot 4003 0 STRESS: STATIC LATCH-UP TESTING (±140mA current injection and 5.4V overvoltage test) CY15B102N-ZS60XA 4502179 611503332 CML-RA 125C 6 0 STRESS: Electrical Distributions CY15B102N-ZS60XA 4422646 611428220 CML-RA Room 30 0 CY15B102N-ZS60XA 4422646 611428220 CML-RA Hot 30 0 CY15B102N-ZS60XA 4422646 611428220 CML-RA Cold 30 0 CY15B102N-ZS60XA 4422645 611428222 CML-RA Room 30 0 CY15B102N-ZS60XA 4422645 611428222 CML-RA Hot 30 0 CY15B102N-ZS60XA 4422645 611428222 CML-RA Cold 30 0 CY15B102N-ZS60XA 4422645 611428223 CML-RA Room 30 0 CY15B102N-ZS60XA 4422645 611428223 CML-RA Hot 30 0 CY15B102N-ZS60XA 4422645 611428223 CML-RA Cold 30 0 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 8 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 133505 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: ESD-HUMAN BODY CIRCUIT (500V) CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 3 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 3 0 STRESS: ESD-HUMAN BODY CIRCUIT (1,000V) CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 3 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 3 0 STRESS: ESD-HUMAN BODY CIRCUIT (1,500V) CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 3 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 3 0 STRESS: ESD-HUMAN BODY CIRCUIT (2,000V) CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 3 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 3 0 STRESS: ESD- CHARGED DEVICE MODEL (250V) CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 3 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 3 0 STRESS: ESD- CHARGED DEVICE MODEL (500V) CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 3 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 3 0 STRESS: ESD- CHARGED DEVICE MODEL (750V)- corner pins CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 3 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 3 0 STRESS: STATIC LATCH-UP TESTING (±140mA, 5.4V) CY15B102Q-SXE 4407065 611415628M UTAC - UT 85C 6 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 125C 3 0 STRESS: DATA RETENTION (150C, 500 and 1,000 hours, non-biased, tested at Hot Temperature = 125C) CY15B102Q-SXE 4351641 611410018 UTAC - UT 500 77 0 CY15B102Q-SXE 4351641 611410018 UTAC - UT 1000 77 0 Company Confidential A printed copy of this document is considered uncontrolled. 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Page 9 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 133505 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: DATA RETENTION (150C, 500 and 1,000 hours, non-biased, tested at Hot Temperature = 125C) CY15B102Q-SXE 4346426 611410540M UTAC - UT 500 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT 1000 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 500 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 1000 77 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 500 77 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 1000 77 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT 500 77 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT 1000 77 0 STRESS: HIGH TEMPERATURE OPERATING LIFE- EARLY FAILURE RATE (125C, 96 hours, 3.60V) CY15B102N-ZS60XA 4502179 611503332 CML-RA Room 2962 0 CY15B102N-ZS60XA 4502179 611503332 CML-RA Hot 2962 0 CY15B102N-ZS60XA 4502179 611503332N1 CML-RA Room 1000 0 CY15B102N-ZS60XA 4502179 611503332N1 CML-RA Hot 1000 0 CY15B102N-ZS60XA 611505901 611503332N1 CML-RA Room 4002 0 CY15B102N-ZS60XA 611505901 611503332N1 CML-RA Hot 4002 0 CY15B102N-ZS60XA 4507661 611505900 CML-RA Room 4003 0 CY15B102N-ZS60XA 4507661 611505900 CML-RA Hot 4003 0 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 10 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 133505 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: HIGH TEMPERATURE OPERATING LIFE- LATENT FAILURE RATE (125C, 1,000 hours, 3.60V) CY15B102Q-SXE 4351641 611410018 UTAC - UT Room 77 0 CY15B102Q-SXE 4351641 611410018 UTAC - UT Hot 77 0 CY15B102Q-SXE 4351641 611410018 UTAC - UT Cold 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT Room 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT Hot 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT Cold 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Cold 77 0 STRESS: Highly Accelerated Saturation Test (HAST) (130C, 85%RH, Biased at 3.60V), with MSL3 Preconditioning – 96 and 168 hours CY15B102Q-SXE 4351641 611410018 UTAC - UT Room 77 0 CY15B102Q-SXE 4351641 611410018 UTAC - UT Hot 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT Room 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT Hot 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Room 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT Hot 77 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT Room 77 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT Hot 77 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT Room 77 0 CY15B102Q-SXE 4407065 611415628M 2 UTAC - UT Hot 77 0 Company Confidential A printed copy of this document is considered uncontrolled. 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Page 11 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 133505 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: TEMPERATURE CYCLE, CONDITION C (-65C TO 150C), with MSL3 Preconditioning CY15B102Q-SXE 4351641 611410018 UTAC - UT 500, Room 77 0 CY15B102Q-SXE 4351641 611410018 UTAC - UT 500, Hot 77 0 CY15B102Q-SXE 4351641 611410018 UTAC - UT 1000, Room 72 0 CY15B102Q-SXE 4351641 611410018 UTAC - UT 1000, Hot 72 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT 500, Room 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT 500, Hot 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT 1000, Room 72 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT 1000, Hot 72 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 500, Room 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 500, Hot 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 1000, Room 72 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 1000, Hot 72 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 500, Room 77 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 500, Hot 77 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 1000, Room 72 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 1000, Hot 72 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT 500, Room 77 0 CY15B102Q-SXE 4407065 611415628M 2 UTAC - UT 500, Hot 77 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT 1000, Room 72 0 CY15B102Q-SXE 4407065 611415628M 2 UTAC - UT 1000, Hot 72 0 Company Confidential A printed copy of this document is considered uncontrolled. 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Page 12 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 133505 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: POST TEMPERATURE CYCLE WIRE BOND PULL CY15B102Q-SXE 4346426 611410540M UTAC - UT 500 5 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 500 5 0 STRESS: PRESSURE COOKER TEST (121C, 100%RH), with MSL3 Preconditioning CY15B102Q-SXE 4351641 611410018 UTAC - UT 96, Room 77 0 CY15B102Q-SXE 4351641 611410018 UTAC - UT 168, Room 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT 96, Room 77 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT 168, Room 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 96, Room 77 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT 168, Room 77 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 96, Room 77 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT 168, Room 77 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT 96, Room 77 0 CY15B102Q-SXE 4407065 611415628M 2 UTAC - UT 168, Room 77 0 STRESS: WIRE BALL SHEAR CY15B102Q-SXE 4351641 611410018 UTAC - UT COMP 30 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT COMP 30 0 Company Confidential A printed copy of this document is considered uncontrolled. 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Page 13 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 133505 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: WIRE BOND PULL CY15B102Q-SXE 4351641 611410018 UTAC - UT COMP 30 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT COMP 30 0 STRESS: SOLDERABILITY CY15B102Q-SXE 4351641 611410018 UTAC - UT COMP 15 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT COMP 15 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT COMP 15 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT COMP 15 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT COMP 15 0 STRESS: PHYSICAL DIMENSIONS CY15B102Q-SXE 4351641 611410018 UTAC - UT COMP 30 0 CY15B102Q-SXE 4346426 611410540M UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M1 UTAC - UT COMP 30 0 CY15B102Q-SXE 4407065 611415628M2 UTAC - UT COMP 30 0 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 14 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Reliability Test Data QTP #: 133505 Device Fab Lot # Assy Lot # Assy Loc Duration/ Test Temp Samp Rej Failure Mechanism STRESS: Electrical Distributions CY15B102Q-SXE 4502179 611504626 UTAC - UT Room 30 0 CY15B102Q-SXE 4502179 611504626 UTAC - UT Hot 30 0 CY15B102Q-SXE 4502179 611504626 UTAC - UT Cold 30 0 CY15B102Q-SXE 4504328 611505284 UTAC - UT Room 30 0 CY15B102Q-SXE 4504328 611505284 UTAC - UT Hot 30 0 CY15B102Q-SXE 4504328 611505284 UTAC - UT Cold 30 0 CY15B102Q-SXE 4507661 611505873 UTAC - UT Room 30 0 CY15B102Q-SXE 4507661 611505873 UTAC - UT Hot 30 0 CY15B102Q-SXE 4507661 611505873 UTAC - UT Cold 30 0 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 15 of 16 Document No. 001-97466 Rev. *B ECN# 4803216 Document History Page Document Title: Document Number: Rev. ECN No. ** 4756329 *A 4763557 *B 4803216 QTP#143501: New Automotive Product Qualification, 1Mb and 2Mb Parallel F-RAM Memory 001-97466 Orig. of Change BECK BECK BECK Description of Change Initial Release Fixed Typos in Assembly Site and standardized Mb to Mbit Indicated “Proprietary” Items on the “TECHNOLOGY/FAB PROCESS DESCRIPTION” Table Distribution: WEB Posting: None Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 16 of 16