CY7S1061G/CY7S1061GE 16-Mbit (1 M words × 16 bit) Static RAM with PowerSnooze™ and ECC 16-Mbit (1 M words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC) Features To access devices with a single-chip enable input, assert the chip enable input (CE) LOW. To access dual chip enable devices, assert both chip enable inputs – CE1 as LOW and CE2 as HIGH. ■ High speed ❐ tAA = 10 ns ■ Ultra-low power PowerSnooze™ [1] device ❐ Deep Sleep (DS) current IDS = 22-µA maximum ■ Low active and standby currents ❐ ICC = 90-mA typical ❐ ISB2 = 20-mA typical ■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V ■ Embedded error-correcting code (ECC) for single-bit error correction ■ 1.0-V data retention ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ Error indication (ERR) pin to indicate 1-bit error detection and correction ■ Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages To perform data writes, assert the Write Enable (WE) input LOW, and provide the data and address on device data pins (I/O0 through I/O15) and address pins (A0 through A19) respectively. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. Functional Description The CY7S1061G/CY7S1061GE is a high-performance CMOS fast static RAM organized as 1,048,576 words by 16 bits. This device features fast access times (10 ns) and a unique ultra-low power Deep Sleep mode. With Sleep mode currents as low as 22 µA, the CY7S1061G device combines the best features of fast and low-power SRAM in industry-standard package options. The device also features embedded ECC[2]. ECC logic can detect and correct single-bit error in the accessed location. The CY7S1061GE device includes an ERR pin that signals an error-detection and correction event during a read cycle. To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). You can perform byte accesses by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH for single chip enable devices and CE1 HIGH and CE2 LOW for dual chip enable devices), or the control signals (OE, BLE, BHE) are de-asserted. The device is placed in a low power Deep Sleep mode when the Deep Sleep pin (DS) is LOW. In this state, the device is disabled for normal operation and is placed in a data retention mode. The device can be activated by de-asserting the Deep Sleep pin (DS HIGH). The CY7S1061G/CY7S1061G is available in 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages. For a complete list of related resources, click here. Product Portfolio Current Consumption Product CY7S1061G18 CY7S1061G(E)30 CY7S1061G Range Industrial VCC Range (V) 1.65 V–2.2 V 2.2 V–3.6 V 4.5–5.5 V Speed (ns) 15 10 10 Operating ICC (mA) f = fmax Typ [3] Max 70 80 90 110 90 110 Standby, ISB2 (mA) Deep-Sleep Current (µA) Typ [3] Max Typ [1] Max 20 30 8 22 Notes 1. Refer to AN89371 for details on PowerSnooze™ feature of this device. 2. This device does not support automatic write-back on error detection. 3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V), VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C. Cypress Semiconductor Corporation Document Number: 001-79707 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 10, 2015 CY7S1061G/CY7S1061GE Logic Block Diagram – CY7S1061G Logic Block Diagram – CY7S1061GE Document Number: 001-79707 Rev. *M Page 2 of 23 CY7S1061G/CY7S1061GE Contents Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 7 Operating Range ............................................................... 7 DC Electrical Characteristics .......................................... 7 Capacitance ...................................................................... 8 Thermal Resistance .......................................................... 8 AC Test Loads and Waveforms ....................................... 8 Data Retention Characteristics ....................................... 9 Data Retention Waveform ................................................ 9 Deep-Sleep Mode Characteristics ................................. 10 AC Switching Characteristics ....................................... 11 Switching Waveforms .................................................... 12 Truth Table ...................................................................... 16 ERR Output – CY7S1061GE ........................................... 16 Document Number: 001-79707 Rev. *M Ordering Information ...................................................... 17 Ordering Code Definitions ......................................... 17 Package Diagrams .......................................................... 18 Acronyms ........................................................................ 21 Document Conventions ................................................. 21 Units of Measure ....................................................... 21 Document History Page ................................................. 22 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC® Solutions ...................................................... 23 Cypress Developer Community ................................. 23 Technical Support ..................................................... 23 Page 3 of 23 CY7S1061G/CY7S1061GE Pin Configurations Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout (Top View) [4] 1 2 3 4 5 6 BLE OE A0 A1 A2 DS A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O12 I/O3 I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout with ERR (Top View) [4] 1 2 3 4 5 6 BLE OE A0 A1 A2 DS A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC ERR A16 I/O4 VSS E I/O12 I/O3 I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Note 4. NC pins are not connected internally to the die. Document Number: 001-79707 Rev. *M Page 4 of 23 CY7S1061G/CY7S1061GE Pin Configurations (continued) Figure 3. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Pinout [5] I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 NC OE VSS DS BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 Note 5. NC pins are not connected internally to the die. Document Number: 001-79707 Rev. *M Page 5 of 23 CY7S1061G/CY7S1061GE Pin Configurations (continued) Figure 4. 48-pin TSOP I (12 × 18.4 × 1 mm) Pinout (Top View) [6] A4 A3 A2 A1 A0 NC CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE DS A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A5 A6 A7 A8 OE BHE BLE I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 Figure 5. 48-pin TSOP I (12 × 18.4 × 1 mm) Pinout, ERR Output at Pin 6 (Top View) Note 6. NC pins are not connected internally to the die. Document Number: 001-79707 Rev. *M Page 6 of 23 CY7S1061G/CY7S1061GE DC input voltage [7] ............................. –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied ................................... –55 C to +125 C Supply voltage on VCC relative to GND [7] ............................... –0.5 V to VCC + 0.5 V DC voltage applied to outputs in High Z State [7] ................................ –0.5 V to VCC + 0.5 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Latch-up current .................................................... > 140 mA Operating Range Range Industrial Ambient Temperature –40 C to +85 C VCC 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V DC Electrical Characteristics Over the operating range of –40 C to +85 C Parameter VOH VOL Description Output HIGH 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA voltage 2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA VIH VIL [7, 10] Input LOW voltage Typ [8] Max 1.4 – – 2.0 – – VCC = Min, IOH = –4.0 mA 2.2 – – 4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – – 4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.4 [9] – – Output LOW 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA voltage 2.2 V to 2.7 V VCC = Min, IOL = 2 mA 2.7 V to 3.6 V VCC = Min, IOL = 8 mA Input HIGH voltage 10 ns / 15 ns Min 2.7 V to 3.6 V 4.5 V to 5.5 V [7, 10] Test Conditions VCC = Min, IOL = 8 mA – – 0.2 – – 0.4 – – 0.4 – – 0.4 1.65 V to 2.2 V – 1.4 – VCC + 0.2 2.2 V to 2.7 V – 2.0 – VCC + 0.3 2.7 V to 3.6 V – 2.0 – VCC + 0.3 4.5 V to 5.5 V – 2.2 – VCC + 0.5 1.65 V to 2.2 V – –0.2 – 0.4 2.2 V to 2.7 V – –0.3 – 0.6 2.7 V to 3.6 V – –0.3 – 0.8 4.5 V to 5.5 V – –0.5 – 0.8 – +1.0 Unit V V V V A IIX Input leakage current GND < VIN < VCC(for all pins except DS) VIN = GND (or) VIN > VIH (for DS pin only) –1.0 IOZ ICC Output leakage current GND < VOUT < VCC, Output disabled –1.0 – +1.0 A – 90.0 110.0 mA ISB1 Standby current – TTL inputs Max VCC, CE[11] > VIH, VIN > VIH or VIN < VIL, f = fMAX ISB2 Standby current – CMOS inputs IDS Deep-Sleep current VCC operating supply current VCC = Max, IOUT = 0 mA, CMOS levels f = 100 MHz f = 66.7 MHz – 70.0 80.0 – – 40.0 mA Max VCC, CE[11] > VCC – 0.2 V, DS > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 – 20.0 30.0 mA Max VCC, CE[11] > VCC – 0.2 V, DS < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 – 8.0 22.0 µA Notes 7. VIL (min) = –2.0 V and VIH (max) = VCC + 2 V for pulse durations of less than 2 ns. 8. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V), VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C. 9. This parameter is guaranteed by design and is not tested. 10. For DS pin, VIH (min) is VCC – 0.2 V and VIL (max) is 0.2 V. 11. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-79707 Rev. *M Page 7 of 23 CY7S1061G/CY7S1061GE Capacitance Parameter [12] Description CIN Input capacitance COUT I/O capacitance Test Conditions All packages Unit 10 pF 10 pF TA = 25 C, f = 1 MHz, VCC(typ) Thermal Resistance Parameter [12] Description Test Conditions JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 48-ball VFBGA 54-pin TSOP II 48-pin TSOP I Unit Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 31.50 93.63 57.99 C/W 15.75 21.58 13.42 C/W AC Test Loads and Waveforms Figure 6. AC Test Loads and Waveforms[13] High-Z Characteristics: VCC 50 Output VTH Z0 = 50 R1 Output 30 pF* * Including JIG and Scope (a) * Capacitive Load Consists of all Components of the Test Environment R2 5 pF* (b) All Input Pulses VHIGH GND 90% 90% 10% Rise Time: > 1 V/ns 10% Fall Time: > 1 V/ns (c) Parameters 1.8 V 3.0 V 5.0 V Unit R1 1667 317 317 R2 1538 351 351 VTH VCC/2 1.5 1.5 V VHIGH 1.8 3.0 3.0 V Notes 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full-device AC operation assumes a 100-s ramp time from 0 to VCC (min) and100-s wait time after VCC stabilizes to its operational value. Document Number: 001-79707 Rev. *M Page 8 of 23 CY7S1061G/CY7S1061GE Data Retention Characteristics Over the Operating Range of –40C to +85 C Parameter Description Conditions VDR VCC for data retention ICCDR Data retention current tCDR [14] Chip deselect to data retention time tR[14] Operation recovery time Min Max Unit 1.0 – V – 30.0 mA 0 – ns 2.2 V < VCC < 5.5 V 10.0 – ns VCC < 2.2 V 15.0 – ns VCC = VDR, CE > VCC – 0.2 V, DS > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Data Retention Waveform Figure 7. Data Retention Waveform[15, 16] VCC VCC(min) DATA RETENTION MODE VDR = 1.0 V tCDR VCC(min) tR CE Notes 14. These parameters are guaranteed by design and are not tested. 15. Full device operation requires linear VCC ramp from VDR to VCC (min) > 100 s or stable at VCC (min) > 100 s. 16. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-79707 Rev. *M Page 9 of 23 CY7S1061G/CY7S1061GE Deep-Sleep Mode Characteristics Over the Operating Range of –40 C to +85 C Parameter Description Conditions [17] Min Max Unit – 22 µA IDS Deep Sleep Mode current tCEDS [17, 18] Time between de-assertion of CE[17] and assertion of DS 100 – ns tDS [17, 18] DS assertion to Deep Sleep mode transition time – 1 ms tDSCE [17, 18] Time between de-assertion of DS and assertion of CE[17] 1 – ms VCC = VCC (max), CE > VCC – 0.2 V, DS < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Figure 8. Active, Standby, and Deep-Sleep Operation Modes [19] CE DS tCEDS Mode Active Mode tDS Standby Mode tDSCE Deep Sleep Mode Notes 17. Address, data, and control lines should not toggle within tDS. They should be fixed to one of the logic levels - VIH or VIL. 18. These parameters are guaranteed by design and are not tested. 19. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-79707 Rev. *M Page 10 of 23 CY7S1061G/CY7S1061GE AC Switching Characteristics Over the operating range of –40 C to +85 C Parameter [20, 21] Description 10 ns 15 ns Min Max Min Max Unit Read Cycle tpower VCC (stable) to the first access [22, 23] 100.0 – 100.0 – µs tRC Read cycle time 10.0 – 15.0 – ns tAA Address to data valid / ERR valid – 10.0 – 15.0 ns tOHA Data / ERR hold from address change 3.0 – 3.0 – ns tACE CE LOW to data valid / ERR valid – 10.0 – 15.0 ns tDOE OE LOW to data valid / ERR valid – 5.0 – 8.0 ns 0 – 1.0 – ns – 5.0 – 8.0 ns 3.0 – 3.0 – ns – 5.0 – 8.0 ns 0 – 0 – ns – 10.0 – 15.0 ns – 5.0 – 8.0 ns 0 – 1.0 – ns – 5.0 – 8.0 ns [24, 25, 26] tLZOE OE LOW to low Z tHZOE OE HIGH to high Z [24, 25, 26] [24, 25, 26, 27] tLZCE CE LOW to low Z tHZCE CE HIGH to high Z [24, 25, 26, 27] tPU CE LOW to power-up [23] tPD CE HIGH to power-down tDBE Byte enable to data valid tLZBE tHZBE Byte enable to low Z [23] [24, 25] Byte disable to high Z [24, 25] Write Cycle [28, 29] tWC Write cycle time 10.0 – 15.0 – ns tSCE CE LOW to write end [27] 7.0 – 12.0 – ns tAW Address setup to write end 7.0 – 12.0 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7.0 – 12.0 – ns tSD Data setup to write end 5.0 – 8.0 – ns tHD Data hold from write end 0 – 0 – ns [24, 25, 26] tLZWE WE HIGH to low Z 3.0 – 3.0 – ns tHZWE WE LOW to high Z [24, 25, 26] – 5.0 – 8.0 ns tBW Byte Enable to End of Write 7.0 – 12.0 – ns Notes 20. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V), and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading shown in part (a) of Figure 6 on page 8, unless specified otherwise 21. DS must be HIGH for chip access. Refer to AN89371 for details. 22. tPOWER gives the minimum amount of time that the power supply is at stable VCC until the first memory access is performed. 23. These parameters are guaranteed by design and are not tested. 24. tHZOE, tHZCE, tHZWE,and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 6 on page 8. Hi-Z, Lo-Z transition is measured 200 mV from steady state voltage. 25. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 26. Tested initially and after any design or process changes that may affect these parameters. 27. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 28. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 29. The minimum write pulse width for Write Cycle No. 2 (WE controlled, OE LOW) should be the sum of tHZWE and tSD. Document Number: 001-79707 Rev. *M Page 11 of 23 CY7S1061G/CY7S1061GE Switching Waveforms Figure 9. Read Cycle No. 1 of CY7S1061G (Address Transition Controlled) [30, 31] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 10. Read Cycle No. 2 of CY7S1061GE (Address Transition Controlled) [30, 31] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID tAA tOHA ERR PREVIOUS ERR VALID ERR VALID Notes 30. The device is continuously selected. OE= VIL, CE = VIL, BHE or BLE or both = VIL. 31. WE is HIGH for read cycle. Document Number: 001-79707 Rev. *M Page 12 of 23 CY7S1061G/CY7S1061GE Switching Waveforms (continued) Figure 11. Read Cycle No. 3 (OE Controlled) [32, 33, 34] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/ BLE tDBE tLZBE tHZBE HIGH IMPEDANCE DATA I/O DATAOUT VALID HIGH IMPEDANCE tLZCE tPU VCC SUPPLY CURRENT ISB Figure 12. Write Cycle No. 1 (CE Controlled) [33, 35, 36] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE/ BLE OE tHZOE DATA I/O Note 37 tSD tHD DATAIN VALID Notes 32. WE is HIGH for read cycle. 33. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 34. Address valid prior to or coincident with CE LOW transition. 35. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 36. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 37. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-79707 Rev. *M Page 13 of 23 CY7S1061G/CY7S1061GE Switching Waveforms (continued) Figure 13. Write Cycle No. 2 (WE Controlled, OE LOW) [38, 39, 40, 41] tW C ADDRESS tS C E CE tB W BHE/ BLE tA W tH A tS A tP W E WE tS D tH Z W E D A T A I/O Note 42 tLZ W E tH D D A T A IN V A L ID Figure 14. Write Cycle No. 3 (WE controlled) [38, 40, 41] tW C ADDRESS tS C E CE tA W tS A tH A tP W E WE tB W B H E /B L E OE tH Z O E D A T A I/O Note 42 tH D tS D D A T A I N V A L ID Notes 38. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 39. The minimum write pulse width for Write Cycle No. 2 (WE controlled, OE LOW) should be sum of tHZWE and tSD. 40. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 41. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 42. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-79707 Rev. *M Page 14 of 23 CY7S1061G/CY7S1061GE Switching Waveforms (continued) Figure 15. Write Cycle No. 3 (BLE or BHE Controlled) [43, 44, 45] tW C ADDRESS t SCE CE t AW t SA t HA t BW BHE/ BLE t PW E WE t HZW E DATA I/O Note 46 t SD t HD t LZW E DATA IN VALID Notes 43. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 44. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 45. Data I/O is in high-impedance state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH. 46. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-79707 Rev. *M Page 15 of 23 CY7S1061G/CY7S1061GE Truth Table DS CE OE [47] X WE BLE BHE [47] [47] [47] High-Z High-Z Standby Standby (ISB) X X X I/O0–I/O7 I/O8–I/O15 Mode Power H H H L L H L L Data out Data out Read all bits Active (ICC) H L L H L H Data out High-Z Read lower bits only Active (ICC) H L L H H L High-Z Data out Read upper bits only Active (ICC) H L X L L L Data in Data in Write all bits Active (ICC) H L X L L H Data in High-Z Write lower bits only Active (ICC) H L X L H L High-Z Data in Write upper bits only Active (ICC) H L H H X X High-Z High-Z Selected, outputs disabled Active (ICC) L[48] H X X X X High-Z High-Z Deep Sleep Deep-Sleep Ultra Low Power (IDS) L L X X X X – – Invalid mode[49] – H L X X H H High-Z High-Z Selected, outputs disabled Active (ICC) ERR Output – CY7S1061GE Output [50] Mode 0 Read operation, no single-bit error in the stored data. 1 Read operation, single-bit error detected and corrected. High-Z Device deselected or outputs disabled or Write operation Notes 47. The input voltage levels on these pins should be either at VIH or VIL. 48. VIL on DS must be < 0.2 V. 49. This mode does not guarantee data retention. Power cycling needs to be performed for the device to return to normal operation. 50. ERR is an Output pin. If not used, this pin should be left floating. Document Number: 001-79707 Rev. *M Page 16 of 23 CY7S1061G/CY7S1061GE Ordering Information Speed (ns) 15 Voltage Range Package Diagram Ordering Code ERR Pin/ Ball 1.65 V–2.2 V CY7S1061G18-15ZSXI 51-85160 54-pin TSOP II No CY7S1061G30-10ZSXI 51-85160 54-pin TSOP II No CY7S1061G30-10BVXI 10 Package Type All (Pb-free) 2.2 V–3.6 V 51-85150 48-ball VFBGA CY7S1061GE30-10BVXI CY7S1061G30-10ZXI 51-85183 48-pin TSOP I CY7S1061GE30-10ZXI 4.5 V–5.5 V CY7S1061GE-10ZXI 51-85183 48-pin TSOP I Operating Range No Yes Industrial No Yes Yes Ordering Code Definitions CY 7 S 1 06 1 G E 30 - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = BV or Z or ZS BV = 48-ball VFBGA; Z = 48-pin TSOP I; ZS = 54-pin TSOP II Speed: 10 ns Voltage Range: 30 = 3-V typ; 18 = 1.8-V typ; no character = 5-V typ ERR output Revision Code “G”: Process Technology – 65 nm Data width: 1 = × 16-bits Density: 06 = 16-Mbit Family Code: 1 = Fast Asynchronous SRAM family S = Deep-Sleep feature Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-79707 Rev. *M Page 17 of 23 CY7S1061G/CY7S1061GE Package Diagrams Figure 16. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline 51-85150 *H Document Number: 001-79707 Rev. *M Page 18 of 23 CY7S1061G/CY7S1061GE Package Diagrams (continued) Figure 17. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline 51-85183 *D Document Number: 001-79707 Rev. *M Page 19 of 23 CY7S1061G/CY7S1061GE Package Diagrams (continued) Figure 18. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline 51-85160 *E Document Number: 001-79707 Rev. *M Page 20 of 23 CY7S1061G/CY7S1061GE Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/output s microsecond OE Output Enable mA milliampere mm millimeter ns nanosecond ohm % percent pF picofarad V volt W watt SRAM Static random access memory TTL Transistor-transistor logic VFBGA Very fine-pitch ball grid array WE Write Enable Document Number: 001-79707 Rev. *M Symbol Unit of Measure Page 21 of 23 CY7S1061G/CY7S1061GE Document History Page Document Title: CY7S1061G/CY7S1061GE, 16-Mbit (1 M words × 16 bit) Static RAM with PowerSnooze™ and ECC Document Number: 001-79707 Rev. ECN No. Orig. of Change Submission Date *M 4791835 NILE 06/10/2015 Document Number: 001-79707 Rev. *M Description of Change Changed datasheet status to Final Page 22 of 23 CY7S1061G/CY7S1061GE Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-79707 Rev. *M Revised June 10, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 23 of 23