ONSEMI CM1216

6 and 8-Channel Low Capacitance
ESD Arrays
CM1216
Features
•
•
•
•
•
•
•
•
•
•
Six and eight channels of ESD protection
Provides +15 kV ESD protection on each channel
per the IEC 61000-4-2 ESD requirements
Channel loading capacitance of 1.6 pF typical
Channel I/O to GND capacitance difference of
0.04pF typical
Mutual capacitance of 0.13pF typical
Minimal capacitance change with temperature
and voltage
Each I/O pin can withstand over 1000 ESD
strikes
SOIC and MSOP packages
RoHs-compliant, lead-free packaging
Applications
•
•
•
•
•
IEEE1394 Firewire ports at 400Mbps / 800Mbps
DVI ports, HDMI ports in notebooks, set top
boxes, digital TVs, LCD displays
Serial ATA ports in desktop PCs and hard disk
drives
PCI Express ports
General purpose high-speed data line ESD
protection
Product Description
The CM1216 family of diode arrays provide sESD
protection for electronic components or sub-systems
requiring minimal capacitive loading. These devices
are ideal for protecting systems with high data and
clock rates or for circuits requiring low capacitive
loading. Each ESD channel consists of a pair of
diodes in series which steer the positive or negative
ESD current pulse to either the positive (VP) or
negative (VN) supply rail. The CM1216 protects
against ESD pulses up to +15kV per the IEC 610004-2 standard.
This device is particularly well-suited for protecting
systems using high-speed ports such as USB2.0,
IEEE1394 (Firewire, iLink), Serial ATA, DVI, HDMI
and corresponding ports in removable storage, digital
camcorders, DVD-RW drives and other applications
where extremely low loading capacitance with ESD
protection are required in a small package footprint.
Block Diagram
©2010 SCILLC. All rights reserved.
April 2010 – Rev. 2
Publication Order Number:
CM1216/D
CM1216
Pin Configurations
Pin Information
PIN DESCRIPTIONS
�PIN
MSOP-8
SOIC-8
MSOP-10
NAME
PIN NO.
PIN NO.
PIN NO.
CH1
1
1
CH2
2
CH3
TYPE
DESCRIPTION
1
I/O
ESD Channel
2
2
I/O
ESD Channel
4
4
3
I/O
ESD Channel
CH4
5
5
4
I/O
ESD Channel
VN
3
3
5
GND
Negative voltage supply rail
CH5
6
6
6
I/O
ESD Channel
CH6
8
8
7
I/O
ESD Channel
VP
7
7
8
PWR
Positive voltage supply rail
CH7
−
−
9
I/O
ESD Channel
CH8
−
−
10
I/O
ESD Channel
Rev. 2 | Page 2 of 13 | www.onsemi.com
CM1216
Ordering Information
PART NUMBERING INFORMATION
Lead-free Finish
Pins
Package
Ordering Part Number
Part Marking
8
SOIC
CM1216-06SM
E166
8
MSOP
CM1216-06MR
E166
10
MSOP
CM1216-08MR
E168
1
Note 1: Parts are shipped in Tape and Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating Supply Voltage (VP-VN)
Diode Forward DC Current (Note 1)
DC Voltage at any Channel Input
Operating Temperature Range
Ambient
Junction
Storage Temperature Range
RATING
6
UNITS
V
20
mA
(VN-0.5) to (VP+0.5)
V
-40 to +85
°C
-40 to +125
°C
-40 to +150
°C
Standard Operating Conditions
STANDARD OPERATING CONDITIONS
PARAMETER
Temperature Range (Ambient)
Package Power Rating
MSOP8 Package (CM1216-06MR)
SOIC8 Package (CM1216-06SM)
MSOP10 Package (CM1216-08MR)
Rev. 2 | Page 3 of 13 | www.onsemi.com
RATING
UNITS
-40 to +85
°C
400
600
400
mW
mW
mW
CM1216
ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL
CONDITIONS
PARAMETER
MIN
NOTE 1
TYP
MA
X
UNIT
3.3
5.5
V
8
µA
0.8
0.8
0.95
0.95
V
V
VP
Operating Supply Voltage
(VP-VN)
IP
Operating Supply Current
(VP-VN) = 3.3V
VF
Diode Forward Voltage
Top Diode
Bottom Diode
IF = 20mA; TA=25°C
ILEAK
Channel Leakage Current
TA = 25°C; VP= 5V, VN = 0V
±0.1
±1.0
µA
CIN
Channel Input Capacitance
At 1 MHz, VP=3.3V, VN =0V,
VIN=1.65V;Note2
1.6
2.0
pF
∆CIN
Channel Input Capacitance
Matching
CMUTUAL
VESD
VCL
RDYN
0.6
0.6
Mutual Capacitance
(VP-VN) = 3.3V
ESD Protection
Peak Discharge Voltage at
any
channel input, in system,
contact
discharge per
IEC 61000-42 standard
Notes 2 and 3; TA = 25°C
Channel Clamp Voltage
Positive Transients
Negative Transients
IPP = 1A, tP = 8/20µS; TA=25°C
Dynamic Resistance
Positive transients
Negative transients
IPP = 1A, tP = 8/20µS; TA=25°C
0.04
pF
0.13
pF
±15
Note 1: All parameters specified at TA = -40°C to +85°C unless otherwise noted.
Note 2: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 3.3V, VN grounded.
Note 3: From I/O pins to VP or VN only. VP bypassed to VN with low ESR 0.2µF ceramic capacitor.
Rev. 2 | Page 4 of 13 | www.onsemi.com
kV
+9.0
-1.5
V
V
0.6
0.4
Ω
Ω
CM1216
Performance Characteristics
Figure 1. Typical Variation of CIN vs. VIN
(f = 1MHz, VP= 3.3V, VN = 0V, 0.1µF chip capacitor between VP and VN, TA = 25 C)
Rev. 2 | Page 5 of 13 | www.onsemi.com
CM1216
Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between
the signal input (typically a connector) and the ESD protection device. Refer to Application of Positive ESD
Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input
channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL
on the line being protected is:
VCL
=
Fwd
+ L2 x d(IESD ) / dt
voltage
drop
of
D1
+
VSUPPLY
+
L1
x
d(IESD
)
/
dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact
discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here
-9
d(IESD)/dt can be approximated by ∆IESD/∆t, or 30/(1x10 ). So just 10nH of series inductance (L1 and L2 combined)
will lead to a 300V increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to
drastically increased negative voltage on the line being protected.
The CM1213 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail
inductance L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest
possible VCL, especially when VP is biased at a voltage significantly below the Zener breakdown voltage, it is
recommended that a 0.22µF ceramic chip capacitor be connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of
expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to
the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground
planes and between the signal input and the ESD device to minimize stray series inductance.
Additional Information
See also California Micro Devices Application Note AP209, “Design Considerations for ESD Protection”, in the
Applications section at www.calmicro.com.
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
Rev. 2 | Page 6 of 13 | www.onsemi.com
CM1216
Mechanical Details
The CM1216 is available in SOIC-8, MSOP-8, and MSOP-10 packages with a lead-free finishing.
SOIC-8 Mechanical Specifications
The CM1216-06SM is supplied in an 8-pin SOIC package. Dimensions are presented below.
*
PACKAGE DIMENSIONS
Package
SOIC
Pins
8
Dimensions
Millimeters
Inches
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.19
0.150
0.165
e
1.27 BSC
0.050 BSC
H
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
# per tape
and reel
2500 pieces
Controlling dimension: inches
Package Dimensions for SOIC-8
Rev. 2 | Page 7 of 13 | www.onsemi.com
CM1216
Tape and Reel Specifications
PART NUMBER
PACKAGE SIZE
(mm)
POCKET SIZE (mm)
B0 X A0 X K0
TAPE WIDTH
W
REEL
DIAMETER
QTY PER
REEL
P0
P1
CM1216-06SM
4.90 X 6.00 X 1.55
5.30 X 6.50 X 2.10
12mm
330mm (13")
2500
4mm
8mm
Rev. 2 | Page 8 of 13 | www.onsemi.com
CM1216
Mechanical Details (Cont’d)
MSOP-8 Mechanical Specifications:
The CM1216-06MR is supplied in an 8-pin MSOP package. Dimensions are presented below.
PACKAGE DIMENSIONS
TOP VIEW
MSOP
Package
D
8
Dimensions
Millimeters
Min
Max
Min
Max
0.75
0.95
0.030
0.037
A1
0.05
0.15
0.002
0.006
B
0.28
0.38
0.011
0.015
C
0.13
0.23
0.005
0.009
D
2.90
3.10
0.114
0.122
2.90
3.10
0.114
0.122
e
0.65 BSC
0.026 BSC
H
4.90 BSC
0.193 BSC
# per tape
and reel
5
Inches
A
L
6
8
Pins
E
7
0.40
0.70
0.016
0.028
E
H
Pin 1
Marking
1
2
3
4
SIDE VIEW
A
A1
SEATING
PLANE
B
e
END VIEW
C
4000 pieces
L
Controlling dimension: millimeters
Package Dimensions for MSOP-8
Rev. 2 | Page 9 of 13 | www.onsemi.com
CM1216
Tape and Reel Specifications
PART NUMBER
PACKAGE SIZE
(mm)
POCKET SIZE (mm)
B0 X A0 X K0
TAPE WIDTH
W
REEL
DIAMETER
QTY PER
REEL
P0
P1
CM1213-06MR
3.00 X 3.00 X 0.85
3.3 X 5.3 X1.3
12mm
330mm (13")
4000
4mm
8mm
Rev. 2 | Page 10 of 13 | www.onsemi.com
CM1216
Mechanical Details (cont’d)
MSOP-10 Mechanical Specifications
The CM1213-08MR is supplied in a 10-pin MSOP package. Dimensions are presented below.
*
PACKAGE DIMENSIONS
TOP VIEW
MSOP
Package
10
Pins
Dimensions
D
10
Millimeters
Max
Min
Max
A
0.75
0.95
0.028
0.038
A1
0.05
0.15
0.002
0.006
B
0.17
0.33
0.007
0.013
C
0.13
0.23
0.005
0.009
D
2.90
3.10
0.114
0.122
E
2.90
3.10
0.114
0.122
H
L
8
6
7
Inches
Min
e
9
E
H
Pin 1
Marking
1
2
3
4
5
SIDE VIEW
A
0.50 BSC
0.0196 BSC
4.90 BSC
0.40
0.70
SEAT ING
PLANE
A1
B
0.193 BSC
0.0137
e
0.029
END VIEW
# per tape
and reel
4000
C
Controlling dimension: inches
L
Package Dimensions for MSOP-10
Rev. 2 | Page 11 of 13 | www.onsemi.com
CM1216
Tape and Reel Specifications
PART NUMBER
PACKAGE SIZE
(mm)
POCKET SIZE (mm)
B0 X A0 X K0
TAPE WIDTH
W
REEL
DIAMETER
QTY PER
REEL
P0
P1
CM1216-08MR
3.00 X 3.00 X 0.85
3.3 X 5.3 X1.3
12mm
330mm (13")
4000
4mm
8mm
Rev. 2 | Page 12 of 13 | www.onsemi.com
CM1216
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
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Rev. 2 | Page 13 of 13 | www.onsemi.com
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