3.3V 1:22 HIGH-PERFORMANCE, LOW VOLTAGE BUS CLOCK DRIVER FEATURES DESCRIPTION ■ 3.3V core supply, 1.8V output supply for reduced ■ ■ ■ ■ ■ ■ ClockWorks™ SY89824L The SY89824L is a High Performance Bus Clock Driver with 22 differential HSTL (High Speed Transceiver Logic) output pairs. The part is designed for use in low voltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89824L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)—performance previously unachievable in a standard product having such a high number of outputs. The SY89824L is available in a single space saving package, enabling a lower overall cost solution. power LVPECL and HSTL inputs 22 differential HSTL (low-voltage swing) output pairs HSTL outputs drive 50Ω to ground with no offset voltage Low part-to-part skew (200ps max.) Low pin-to-pin skew (50ps max.) Available in a 64-Pin EPAD HQFP PIN CONFIGURATION VCCO Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 VCCO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCCO 1 48 VCCO NC 2 47 NC VCCI 3 46 Q7 Q7 4 45 HSTL_CLK 5 44 HSTL_CLK CLK_SEL LVPECL_CLK 6 43 7 42 8 41 LVPECL_CLK 9 GND OE 10 39 11 38 NC NC 12 37 13 36 Q21 Q21 14 35 15 VCCO 16 64-PIN HQFP 40 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NAMES Q8 Q8 Pin Function Q9 Q9 HSTL_CLK, /HSTL_CLK Differential HSTL Inputs Q10 Q10 LVPECL_CLK, /LVPECL_CLK Differential LVPECL Inputs CLK_SEL Input CLK Select (LVTTL) Q11 Q11 OE Output Enable (LVTTL) Q12 Q12 Q0-Q21, /Q0-/Q21 Differential HSTL Outputs 34 Q13 Q13 GND Ground 33 VCCO VCCI VCC Core VCCO VCC Output VCCO Q14 Q14 Q15 Q15 Q16 Q16 Q17 Q17 Q18 Q18 Q19 Q19 Q20 Q20 VCCO LOGIC SYMBOL CLK_SEL APPLICATIONS HSTL_CLK ■ High-performance PCs HSTL_CLK 0 22 ■ Workstations 22 ■ Parallel processor-based systems ■ Other high-performance computing LVPECL_CLK ■ Communications LVPECL_CLK Q0 - Q21 Q0 - Q21 1 LEN Q OE D Rev.: C 1 Amendment: /1 Issue Date: March 2000 ClockWorks™ SY89824L Micrel TRUTH TABLE SIGNAL GROUPS OE(1) CLK_SEL Q0-Q21 /Q0-/Q21 0 0 LOW HIGH HSTL Input 0 1 LOW HIGH HSTL Output 1 0 HSTL_CLK /HSTL_CLK 1 1 LVPECL_CLK /LVPECL_CLK Level Direction Signal HSTL_CLK, /HSTL_CLK Q0-Q21, /Q0-/Q21 LVPECL Input LVPECL_CLK, /LVPECL_CLK LVCMOS/LVTTL Input CLK_SEL, OE NOTE: 1. The OE (output enable) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal. ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit VCCI/VCCO VCC Pin Potential to Ground Pin –0.5 to +4.0 V VIN Input Voltage –0.5 to VCCI V IOUT DC Output Current (Output HIGH) –50 mA Tstore Storage Temperature –65 to +150 °C NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Power Supply TA = 0°C Symbol Parameter TA = +25°C TA = +70°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VCCI VCC Core 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 V VCCO VCC Output 1.6 1.8 2.0 1.6 1.8 2.0 1.6 1.8 2.0 V ICCI ICC Core — 115 140 — 115 140 — 115 140 mA HSTL TA = 0°C Symbol TA = +70°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Output HIGH Voltage(1) 1.0 — 1.2 1.0 — 1.2 1.0 — 1.2 V VOL Output LOW Voltage(1) 0 — 0.4 0 — 0.4 0 — 0.4 V VIH Input HIGH Voltage VX +0.1 — 1.6 VX +0.1 — 1.6 VX +0.1 — 1.6 V VIL Input LOW Voltage –0.3 — VX –0.1 –0.3 — VX –0.1 –0.3 — VX –0.1 V VX Input Crossover Voltage 0.68 — 0.9 0.68 — 0.9 0.68 — 0.9 V IIH Input HIGH Current +20 — –350 +20 — –350 +20 — –350 µA IIL Input LOW Current — — –500 — — –500 — — –500 µA VOH Parameter TA = +25°C NOTE: 1. Outputs loaded with 50Ω to ground. 2 ClockWorks™ SY89824L Micrel DC ELECTRICAL CHARACTERISTICS LVPECL TA = 0°C Symbol Parameter Min. TA = +25°C Max. Min. TA = +70°C Max. Min. Max. Unit VIH Input HIGH Voltage VCCI – 1.165 VCCI – 0.880 VCCI – 1.165 VCCI – 0.880 VCCI – 1.165 VCCI – 0.880 V VIL Input LOW Voltage VCCI – 1.810 VCCI – 1.475 VCCI – 1.810 VCCI – 1.475 VCCI – 1.810 VCCI – 1.475 V IIH Input HIGH Current — +150 — +150 — +150 µA IIL Input LOW Current 0.5 — 0.5 — 0.5 — µA LVCMOS/LVTTL TA = 0°C Symbol Parameter TA = +25°C TA = +70°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 2.0 — — 2.0 — — 2.0 — — V VIH Input HIGH Voltage VIL Input LOW Voltage — — 0.8 — — 0.8 — — 0.8 V IIH Input HIGH Current +20 — –250 +20 — –250 +20 — –250 µA IIL Input LOW Current — — –600 — — –600 — — –600 µA AC ELECTRICAL CHARACTERISTICS(1) TA = 0°C Symbol Parameter Delay(2) tPHL tPLH Propagation tskew Within-Device Skew(3) tskpp Part-to-Part Skew(4) Swing(5) TA = +25°C TA = +70°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit — 1.0 — — 1.0 — — 1.0 — ns — — 50 — — 50 — — 50 ps — — 200 — — 200 — — 200 ps 600 — — 600 — — 600 — — mV VPP Minimum Input LVPECL_CLK VCMR Common Mode Range(6) LVPECL_CLK –1.5 — –0.4 –1.5 — –0.4 –1.5 — –0.4 V tS OE Set-Up Time(7) 1.0 — — 1.0 — — 1.0 — — ns tH OE Hold Time 0.5 — — 0.5 — — 0.5 — — ns tr tf Output Rise/Fall Time (20% – 80%) 300 — 800 300 — 800 300 — 800 ps NOTES: 1. Outputs loaded with 50Ω to ground. Airflow ≥ 300 LFPM. 2. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 4. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 5. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 6. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to PRODUCT ORDERING CODE VPP (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V – |VCMR (min)|. 7. OE set-up time is defined with respect to the rising edge of the clock. Ordering Package Operating OE HIGH to LOW transition ensures outputs remain disabled during Code Type Range the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. SY89824LHC H64-1 Commercial 3 ClockWorks™ SY89824L Micrel 64 LEAD EPAD-TQFP (DIE UP) (H64-1) +0.05 –0.05 +0.002 –0.002 +0.05 –0.05 +0.012 –0.012 +0.03 –0.03 +0.012 –0.012 +0.15 –0.15 +0.006 –0.006 +0.05 –0.05 +0.002 –0.002 MICREL-SYNERGY TEL Rev. 02 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4