SY89809L 3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver General Description The SY89809L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications, which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89809L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)—performance previously unachievable in a standard product having such a high number of outputs. The SY89809L is available in a single space saving package, enabling a lower overall cost solution. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Logic Symbol Precision Edge® Features • • • • • • • • 3.3V core supply, 1.8V output supply for reduced power LVPECL and HSTL inputs 9 differential HSTL (low-voltage swing) output pairs HSTL outputs drive 50Ω-to-ground with no offset voltage 500MHz maximum clock frequency Low part-to-part skew (200ps max.) Low pin-to-pin skew (50ps max.) Available in 32-pin TQFP Applications • • • • • High-performance PCs Workstations Parallel processor-based systems Other high-performance computing Communications Level Direction Signal HSTL Input HSTL_CLK, /HSTL_CLK HSTL Output Q0 – Q8, /Q0 – /Q8 LVPECL Input LVPECL_CLK, /LVPECL_CLK LVCMOS/LVTTL Input CLK_SEL, OE Table 1. Signal Groups (1) OE CLK_SEL Q0 – Q8 /Q0 – /Q8 0 0 LOW HIGH 0 1 LOW HIGH 1 0 HSTL_CLK /HSTL_CLK 1 1 LVPECL_CLK /LVPECL_CLK Table 2. Truth Table Note: 1. The OE (output enable) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal. Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com December 2009 M9999-121409-D [email protected] or (408) 955-1690 Micrel, Inc. SY89809L Ordering Information(1) Package Type Operating Range Package Marking Lead Finish T32-1 Commercial SY89809LTC Sn-Pb SY89809LTCTR T32-1 Commercial SY89809LTC Sn-Pb SY89809LTH(3) T32-1 Commercial SY89809LTH with Pb-Free bar-line indicator NiPdAu Pb-Free SY89809LTHTR(2, 3) T32-1 Commercial SY89809LTH with Pb-Free bar-line indicator NiPdAu Pb-Free Part Number SY89809LTC (2) Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. Pin Configuration 32-Pin TQFP (T32-1) December 2009 2 M9999-121409-D [email protected] or (408) 955-1690 Micrel, Inc. SY89809L Pin Description Pin Number Pin Name Type 2, 3 HSTL_CLK, /HSTL_CLK HSTL Input Differential input: This HSTL input can be selected by CLK_SEL. If it is not used, it can be left floating. This produces a LOW at the output. If driven by an HSTL driver, an external 50Ω to ground termination is required at the input. 5, 6 LVPECL_CLK, /LVPECL_CLK LVPECL Input Differential input: This LVPECL input can be selected by CLK_SEL. If it is not used, it can be left floating. This produces a LOW at the output (internal 75kΩ pull-downs). 4 CLK_SEL LVTTL Input Selected HSTL_CLK input when LOW and LVPECL_CLK output when HIGH. 11kΩ pull-up. 8 OE LVTTL Input Single-ended input: This LVTTL input disables and enables the Q0-Q8 output pairs. It is internally synchronized to prevent glitching of the Q0-Q8 output pairs. It is internally connected to a 11kΩ pull-up resistor and will default to a logic HIGH state if left open. 31, 29, 27, 23, 21, 19, 15, 13, 11 Q0 – Q8 HSTL Output Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50Ω to GND. Q0-Q8 outputs are static LOW when OE = LOW. Unused output pairs may be left floating. 30, 28, 26, 22, 20, 18, 14, 12, 10 /Q0 – /Q8 HSTL Output Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50Ω to GND. /Q0-/Q8 outputs are static HIGH when OE = LOW. Unused output pairs may be left floating. 1 VCCI VCC Core Power Core VCC connected to 3.3V supply. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCCI pin as possible. 9, 16, 17, 24, 25, 32 VCCO VCC Output Power 7 GND Ground December 2009 Pin Function Output Buffer VCC connected to 1.8V supply. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCCO pins as possible. All VCCO pins should be connected together on the PCB. Ground. 3 M9999-121409-D [email protected] or (408) 955-1690 Micrel, Inc. SY89809L Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VIN) ........................................ –0.5V to VCCI VCC Pin Potential to Ground Pin (VCCI, VCCO) ............................................ –0.5V to +4.0V DC Output Current, Output HIGH (IOUT) ....................–50mA Lead Temperature (soldering, 20sec.)....................... 260°C Storage Temperature (Ts) .........................–65°C to +150°C Supply Voltage (VCCI) ...................................................... +3.0V to +3.6V (VCCO)..................................................... +1.6V to +2.0V Ambient Temperature (TA) .............................. 0°C to +85°C Package Thermal Resistance TQFP (θJA) –Still-Air.......................................................50°C/W –500lfpm .....................................................42°C/W TQFP (θJC) .........................................................20°C/W DC Electrical Characteristics TA = 0°C to +85°C, unless noted. Power Supply Symbol Parameter VCCI Condition Min Typ Max Units VCC Core 3.0 3.3 3.6 V VCCO VCC Output 1.6 1.8 2.0 V ICCI ICC Core 115 140 mA Typ Max Units 1.2 V HSTL Symbol VOH Parameter Condition Min (3) Output HIGH Voltage 1.0 (3) VOL Output LOW Voltage 0.2 0.4 V VIH Input HIGH Voltage VX +0.1 1.6 V VIL Input LOW Voltage –0.3 VX –0.1 V VX Input Crossover Voltage 0.68 0.9 V IIH Input HIGH Current +20 –350 µA IIL Input LOW Current –500 µA Max Units LVPECL Symbol Parameter Condition Min Typ VIH Input HIGH Voltage VCCI –1.165 VCCI –0.880 V VIL Input LOW Voltage VCCI –1.810 VCCI –1.475 V IIH Input HIGH Current +150 µA IIL Input LOW Current 0.5 µA LVCMOS/LVTTL Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current Condition Min Typ Max 2.0 +20 Units V 0.8 V –250 µA –600 µA Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Outputs loaded with 50Ω to ground. December 2009 4 M9999-121409-D [email protected] or (408) 955-1690 Micrel, Inc. SY89809L AC Electrical Characteristics(4) TA = 0°C to +85°C, unless noted. Symbol Parameter Condition (5) tPD Propagation Delay (6) fMAX Maximum Operating Frequency tSKEW Within-Device Skew(7) Min Typ Max Units 825 1050 1275 ps 500 MHz (8) tSKPP Part-to-Part Skew tJITTER Phase Noise(RMS) 12kHz-20MHz @ 500MHz 0.241 50 ps 200 ps 1 ps See Figure 3 VPP Minimum Input Swing(9) LVPECL_CLK 600 VCMR Common Mode Range(10) LVPECL_CLK –1.5 tS OE Set-Up Time(11) 1.0 ns tH OE Hold Time 0.5 ns tr, tf Output Rise/Fall Time (20% to 80%) 300 mV –0.4 650 V ps Notes: 4. Outputs loaded with 50Ω to ground. Airflow ≥ 300lfpm. 5. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 6. Output swing greater than 450mV. 7. The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 8. The part-to-part skew is defined as the absolute worst-case difference between any two delay paths on any two devices operating at the same voltage and temperature. 9. The VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 10. VCMR is defined as the range within which the VIH level may vary with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min). 11. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next clock cycle. December 2009 5 M9999-121409-D [email protected] or (408) 955-1690 Micrel, Inc. SY89809L Output Waveforms Figure 1. 100MHz Output Waveform Figure 2. 300MHz Output Waveform Figure 4. Phase Noise Plot December 2009 6 M9999-121409-D [email protected] or (408) 955-1690 Micrel, Inc. December 2009 SY89809L 7 M9999-121409-D [email protected] or (408) 955-1690 Micrel, Inc. SY89809L Package Information 32-Pin TQFP (T32-1) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. December 2009 8 M9999-121409-D [email protected] or (408) 955-1690