Revised August 1999 74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description Features The 74F657 contains eight non-inverting buffers with 3STATE outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA at the A Port and 64 mA at the B Port. ■ 300 Mil 24-pin slimline DIP ■ Combines 74F245 and 74F280A functions in one package ■ 3-STATE outputs ■ B Outputs sink 64 mA ■ 12 mA source current, B side ■ Input diodes for termination effects Ordering Code: Order Number Package Number Package Description 75F657SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009584 www.fairchildsemi.com 74F657 Octal Bidirectional Transceiver with March 1988 74F657 Unit Loading/Fan Out Pin Names A0–A7 U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description Data Inputs/ 3-STATE Outputs 4.5/0.15 90 µA/− 90 µA 150/40 (33.3) −3 mA/24 mA (20 mA) 3.5/0.117 70 µA/−70 µA B0–B7 Data Inputs/ 600/106.6 (80) −12 mA/64 mA (48 mA) T/R Transmit/Receive Input 2.0/0.067 40 µA/−40 µA OE Enable Input 2.0/0.067 40 µA/−40 µA PARITY Parity Input/ 3.5/0.117 70 µA/−70µA 600/106.6 (80) −12 mA/64 mA (48 mA) 3-STATE Outputs 3-STATE Output ODD/EVEN ODD/EVEN Parity Input ERROR Error Output 1.0/0.033 20 µA/−20 µA 600/106.6 (80) −12 mA/64 mA (48 mA) Functional Description select (ODD/EVEN). If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH. The Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from the A Port to the B Port; Receive (active LOW) enables data from the B Port to the A Port. The Output Enable (OE) input disables the parity and ERROR outputs and both the A and B Ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH. When transmitting (T/R HIGH), the parity generator detects whether an even or odd number of bits on the A Port are HIGH and compares these with the condition of the parity In receiving mode (T/R LOW), the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error. Function Table Number of Inputs that are HIGH 0, 2, 4, 6, 8 1, 3, 5, 7 Immaterial Function Table Input/ Inputs OE T/R ODD/ EVEN H H H L H L L L H L L H L L L L L L L Outputs OE Parity ERROR L Inputs Outputs Output Outputs Mode Z Transmit L Z Transmit H H Receive L L Receive H L Receive H Receive L H H L Z Transmit L H L H Z Transmit L L H H L Receive L L H L H Receive L L L H H Receive L L L L L Receive H X X Z Z Z www.fairchildsemi.com L L Bus B Data to Bus A L H Bus A Data to Bus B H X High-Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance 2 T/R 74F657 Functional Block Diagram 3 www.fairchildsemi.com 74F657 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 10% VCC 2.0 5% VCC 2.7 5% VCC 2.7 VOL IIH IBVI 2.0 Units VIH IIL Conditions Recognized as a HIGH Signal Recognized as a LOW Signal Min IIN = −18 mA IOH = −1 mA (An) IOH = −3 mA (An B n, Parity, ERROR) V Min IOH = −15 mA (Bn, Parity, ERROR) IOH = −1 mA (An) IOH = −3 mA (An, B n, Parity, ERROR) Output LOW 10% VCC 0.5 Voltage 10% VCC 0.55 Input HIGH 20 Current 40 Input HIGH Current 100 Breakdown Test IBVIT VCC V Input HIGH Current 1.0 Breakdown Test (I/O) 2.0 Input LOW −20 Current −40 V Min µA Max µA VCC = 0 mA Max µA Max IOL = 24 mA (An) IOL = 64 mA (Bn Parity, ERROR) VIN = 2.7V (ODD/EVEN) VIN 2.7V (T/R, OE) VIN = 7.0V (T/R, OE, ODD/EVEN) VIN = 5.5V (Parity, Bn) VIN = 5.5V (An) VIN = 0.5V (ODD/EVEN) VIN = 0.5V (T/R, OE) IOZH Output Leakage Current 50 µA Max VOUT = 2.7V (ERROR) IOZL Output Leakage Current −50 µA Max VOUT = 0.5V (ERROR) IIH + IOZH Output Leakage 70 Current 90 µA Max Output Leakage −70 IIL + IOZL VI/O = 2.7V (Bn, Parity) VI/O = 2.7V (An) VI/O = 0.5V (Bn, Parity) µA Max −225 mA Max Output HIGH Leakage 250 µA Max VOUT = VCC (ERROR) Current 1.0 mA Max VOUT = VCC (Bn, Parity) 2.0 mA Max VOUT = VCC (An) IZZ Bus Drainage Test 500 µA 0.0V VOUT = 5.25V (An, Bn, Parity, ERROR) ICCH Power Supply Current 101 125 mA Max VO = HIGH ICCL Power Supply Current 112 150 mA Max VO = LOW ICCZ Power Supply Current 109 145 mA Max VO = HIGH Z −90 Current IOS ICEX Output Short-Circuit −60 −150 Current −100 www.fairchildsemi.com 4 VI/O = 0.5V (An) VOUT = 0V (An) VOUT = 0V (Bn, Parity, ERROR) 74F657 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 2.5 4.5 8.0 2.5 9.5 2.5 9.0 tPHL An to Bn, Bn to An 3.0 4.9 7.5 3.0 8.5 3.0 8.0 tPLH Propagation Delay 6.5 10.1 14.0 5.5 18.0 6.0 16.0 tPHL An to Parity 7.0 10.9 15.0 5.5 20.5 6.0 16.5 tPLH Propagation Delay 4.5 7.8 11.0 4.0 14.0 4.0 13.0 tPHL ODD/EVEN to PARITY 4.5 8.8 12.0 4.5 16.5 4.5 13.5 13.0 tPLH Propagation Delay 4.5 7.5 11.0 4.0 14.0 4.0 tPHL ODD/EVEN to ERROR 4.5 8.2 12.0 4.5 16.5 4.5 13.5 tPLH Propagation Delay 8.0 14.0 20.5 7.5 27.0 7.5 23.0 tPHL Bn to ERROR 8.0 15.0 21.5 7.5 28.5 7.5 23.5 tPLH Propagation Delay 7.0 10.8 15.5 6.0 20.0 6.0 17.0 tPHL PARITY to ERROR 7.5 11.8 16.5 6.5 22.0 7.5 18.5 tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 tPZL OE to An/Bn 4.0 6.5 10.0 3.5 13.5 3.5 11.0 tPHZ Output Disable Time 1.0 4.5 8.0 1.0 9.5 1.0 9.0 tPLZ OE to An/Bn 1.0 4.9 7.5 1.0 8.5 1.0 8.0 tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 tPZL OE to ERROR (Note 3) 4.0 7.7 10.0 3.5 13.5 3.5 11.0 tPHZ Output Disable Time 1.0 4.5 8.0 1.0 9.5 1.0 9.0 tPLZ OE to ERROR 1.0 4.9 7.5 1.0 8.5 1.0 8.0 tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 tPZL OE to PARITY 4.0 7.7 10.0 3.5 13.5 3.5 11.0 tPHZ Output Disable Time 1.0 4.6 8.0 1.0 9.5 1.0 9.0 tPLZ OE to PARITY 1.0 5.1 7.5 1.0 8.5 1.0 8.0 Units ns ns ns ns ns ns ns ns ns ns ns ns Note 3: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin ≥ (A to PARITY) + (Output Enable Time). 5 www.fairchildsemi.com 74F657 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 74F657 Octal Bidirectional Transceiver with Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com