STP5NB100 STP5NB100FP N - CHANNEL 1000V - 2.4Ω - 5A - TO-220/TO-220FP PowerMESH MOSFET T YPE V DSS R DS(on) ID STP5NB100 STP5NB100F P 1000 V 1000 V < 2.7 Ω < 2.7 Ω 5 A 5 A ν ν ν ν ν TYPICAL RDS(on) = 2.4 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED 3 1 DESCRIPTION Using the latest high voltage MESH OVERLAY process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. 3 2 1 TO-220 2 TO-220FP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ν HIGH CURRENT, HIGH SPEED SWITCHING ν SWITCH MODE POWER SUPPLIES (SMPS) ν DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ABSOLUTE MAXIMUM RATINGS Symb ol Parameter Value ST P5NB100 V DS V DGR V GS 1000 V Drain- gate Voltage (R GS = 20 kΩ) 1000 V ± 30 G ate-source Voltage o Drain Current (continuous) at T c = 25 C ID o P tot dv/dt(1 ) V ISO T s tg Tj STP5NB100FP Drain-source Voltage (V GS = 0) ID I DM (•) Unit Drain Current (continuous) at T c = 100 C V 5 5(*) A A 3.1 3.1(*) 15.2 15.2 A T otal Dissipation at T c = 25 C 135 40 W Derating Factor 1.08 0.32 W/ o C V/ns Drain Current (pulsed) o Peak Diode Recovery voltage slope 4.5 4.5 Insulation W ithstand Voltage (DC) 2000 Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area (*) Limited only by maximum temperature allowed February 2000 V -65 to 150 o C 150 o C (1) ISD ≤ 5 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/9 STP5NB100/STP5NB100FP THERMAL DATA R thj- ca se R t hj-a mb R thc -sin k Tl Thermal Resistance Junction-case TO-220 TO-220F P 0.93 3.12 Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead T emperature F or Soldering Purpose 62.5 0.5 300 o C/W o C/W C/W o C o AVALANCHE CHARACTERISTICS Symbo l Parameter I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) E AS Single Pulse Avalanche Energy o (starting T j = 25 C, ID = I AR , VDD = 50 V) Max Valu e Unit 5 A 220 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V ( BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond itions ID = 250 µA V GS = 0 VDS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) VDS = Max Rating Gate-body Leakage Current (V DS = 0) Min. Typ . Max. 1000 Un it V o Tc = 125 C VGS = ± 30 V 1 50 µA µA ± 100 nA ON (∗) Symbo l Parameter Test Cond itions V GS(th ) Gate T hreshold Voltage VDS = V GS ID = 250 µA R DS(on ) Static Drain-source On Resistance VGS = 10 V I D = 2.5 A I D(on) Min. Typ . Max. Un it 3 4 5 V 2.4 2.7 Ω 5 On State Drain Current VDS > I D(on ) x R DS(on )max VGS = 10 V A DYNAMIC Symbo l g fs (∗) C is s C os s C rs s 2/9 Parameter Test Cond itions Forward Transconductance VDS > I D(on ) x R DS(on )max Input Capacitance Output Capacitance Reverse Tr ansfer Capacitance VDS = 25 V f = 1 MHz I D = 2.5 A VGS = 0 Min. Typ . 1.5 Max. Un it S 1500 150 17 pF pF pF STP5NB100/STP5NB100FP ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Cond itions t d( on) tr Turn-on T ime Rise Time VDD = 500 V I D = 2.5 A VGS = 10 V R G = 4.7 Ω (see test circuit, figure 3) Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 800 V Min. Typ . Max. 24 11 I D = 5 A V GS = 10 V Un it ns ns 39 9.6 19.2 51 nC nC nC Typ . Max. Un it SWITCHING OFF Symbo l t r(Vof f ) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over T ime Test Cond itions Min. 20 22 26 VDD = 800 V I D = 5 A R G = 4.7 Ω V GS = 10 V (see test circuit, figure 5) ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Cond itions I SD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward O n Voltage ISD = 5 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 5 A di/dt = 100 A/µs Tj = 150 o C VDD = 100 V (see test circuit, figure 5) t rr Q rr IRRM Min. Typ . Max. Un it 5 20 A A 1.6 V VGS = 0 780 ns 5.5 µC 14 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area for TO-220 Safe Operating Area for TO-220FP 3/9 STP5NB100/STP5NB100FP Thermal Impedance for TO-220 Thermal Impedance forTO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 STP5NB100/STP5NB100FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP5NB100/STP5NB100FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP5NB100/STP5NB100FP TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 L2 16.4 L4 0.645 13.0 0.551 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/9 STP5NB100/STP5NB100FP TO-220FP MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L3 L3 L6 F F1 L7 F2 H G G1 ¯ 1 2 3 L2 8/9 L4 STP5NB100/STP5NB100FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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