STMICROELECTRONICS STS4C3F60L

STS4C3F60L
N-CHANNEL 60V - 0.045 Ω - 4A SO-8
P-CHANNEL 60V - 0.100 Ω - 3A SO-8
StripFET™ MOSFET
Table 1: General Features
Figure 1: Package
TYPE
VDSS
RDS(on)
ID
STS4C3F60L (N-Channel)
STS4C3F60L (P-Channel)
60 V
60 V
< 0.055 Ω
< 0.120 Ω
4A
3A
■
■
■
■
TYPICAL RDS(on) (N-Channel) = 0.045 Ω
TYPICAL RDS(on) (P-Channel) = 0.100 Ω
STANDARD OUTLINE FOR EASY
AUTOMATED SURFACE MOUNT ASSEMBLY
LOW THRESHOLD DRIVE
DESCRIPTION
This MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size™”
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a remarkable manufacturing reproducibility.
SO-8
Figure 2: Internal Schematic Diagram
APPLICATIONS
■ DC/DC CONVERTERS
■ BACK LIGHT INVERTER FOR LCD
Table 2: Order Codes
PART NUMBER
MARKING
PACKAGE
PACKAGING
STS4C3F60L
S4C3F60L
SO-8
TAPE & REEL
Rev. 2
September 2004
1/11
STS4C3F60L
Table 3: Absolute Maximum ratings
Symbol
Parameter
Value
N-CHANNEL
VDS
VDGR
VGS
Drain-source Voltage (VGS = 0)
Unit
P-CHANNEL
60
Drain-gate Voltage (RGS = 20 kΩ)
Gate-source Voltage
V
60
V
± 16
V
ID
Drain Current (continuous) at TC = 25°C
Single Operating
4
3
A
ID
Drain Current (continuous) at TC = 100°C
Single Operating
2.5
1.9
A
Drain Current (pulsed)
16
IDM ()
PTOT
Tj
Tstg
12
Total Dissipation at TC = 25°C
Operating Junction Temperature
Storage Temperature
A
2
W
-55 to 150
°C
62.5
°C/W
() Pulse width limited by safe operating area
Note: For the P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed
Table 4: Thermal Data
Rthj-amb (1)
Thermal Resistance Junction-ambient
(1) When mounted on 1 inch² pad of 2 oz. copper, t ≤ 10 s
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 5: On/Off
Symbol
V(BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Conditions
ID = 250 µA, VGS = 0
IDSS
VDS= Max Rating
Zero Gate Voltage
Drain Current (VGS = 0) VDS= Max Rating, TC= 125°C
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS= ± 16V
VGS= ± 16V
Min.
n-ch
p-ch
Max.
Unit
V
V
n-ch
p-ch
1
10
µA
µA
n-ch
p-ch
±100
±100
nA
nA
VGS(th)
Gate Threshold Voltage VDS = VGS, ID= 250 µA
n-ch
p-ch
RDS(on)
Static Drain-source On
Resistance
n-ch
p-ch
n-ch
p-ch
VGS= 10 V, ID= 2 A
VGS= 10 V, ID= 1.5 A
VGS= 4.5 V, ID= 2 A
VGS= 4.5 V, ID= 1.5 A
Typ.
60
60
1
1.5
V
V
0.045
0.100
0.050
0.130
0.055
0.120
0.065
0.160
Ω
Ω
Ω
Ω
Typ.
Max.
Unit
Table 6: Dynamic
Symbol
Parameter
Test Conditions
gfs (1)
Forward
Transconductance
VDS = 30 V, ID= 2 A
VDS = 10 V, ID= 3 A
n-ch
p-ch
7
7.2
S
S
Ciss
Input Capacitance
VDS = 25V, f = 1 MHz, VGS = 0
n-ch
p-ch
1030
630
pF
pF
Coss
Output Capacitance
n-ch
p-ch
140
121
pF
pF
Crss
Reverse Transfer
Capacitance
n-ch
p-ch
40
49
pF
pF
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
2/11
Min.
STS4C3F60L
ELECTRICAL CHARACTERISTICS (CONTINUED)
Table 7: Switching On
Symbol
td(on)
tr
Qg
Parameter
Turn-on Delay Time
Rise Time
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
Test Conditions
Min.
Typ.
Max.
Unit
N-CHANNEL
VDD = 30 V, ID = 2 A,
RG= 4.7 Ω, VGS = 4.5 V
n-ch
p-ch
15
124
ns
ns
P-CHANNEL
VDD = 30 V, ID = 1.5 A,
RG= 4.7 Ω, VGS = 4.5 V
(Resistive Load see, Figure 28)
n-ch
p-ch
28
54
ns
ns
N-CHANNEL
VDD= 48 V, ID= 4 A,
VGS= 4.5 V
n-ch
p-ch
15
11.6
n-ch
p-ch
4
4.5
nC
nC
n-ch
p-ch
4
4.7
nC
nC
P-CHANNEL
VDD = 48 V, ID = 3 A,
VGS = 4.5 V
(see, Figure 31)
20.4
15.7
nC
nC
Table 8: Switching Off
Symbol
td(off)
tf
Parameter
Turn-off Delay Time
Fall Time
Test Conditions
Min.
Typ.
Max.
Unit
N-CHANNEL
VDD = 30 V, ID = 2 A,
RG= 4.7 Ω, VGS = 4.5 V
n-ch
p-ch
45
39
ns
ns
P-CHANNEL
VDD = 30 V, ID = 1.5 A,
RG= 4.7 Ω, VGS = 4.5 V
(Resistive Load see, Figure 28)
n-ch
p-ch
10
14.5
ns
ns
Table 9: Source-Drain Diodef
Symbol
Max.
Unit
Source-drain Current
n-ch
p-ch
4
3
A
A
ISDM (2)
Source-drain Current (pulsed)
n-ch
p-ch
16
12
A
A
VSD (1)
Forward On Voltage
ISD = 4 A, VGS = 0
ISD = 3 A, VGS = 0
n-ch
p-ch
1.2
1.2
V
V
trr
Reverse Recovery Time
n-ch
p-ch
85
44
ns
ns
Qrr
Reverse Recovery Charge
N-CHANNEL
ISD = 4 A, di/dt = 100 A/µs
VDD = 20V, Tj = 150°C
n-ch
p-ch
85
68.2
nC
nC
IRRM
Reverse Recovery Current
n-ch
p-ch
2
3.1
A
A
ISD
Parameter
Test Conditions
P-CHANNEL
ISD = 3 A, di/dt = 100 A/µs
VDD = 20V, Tj = 150°C
(see test circuit, Figure 29)
Min.
Typ.
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
3/11
STS4C3F60L
Figure 3: .Safe Operating n-channel
Figure 6: Thermal Impedance For Complementary Pair
Figure 4: Output Characteristics n-channel
Figure 7: Transfer Characteristics n-channel
Figure 5: Transconductance n-channel
Figure 8: Static Drain-Source On Resistance nchannel
4/11
STS4C3F60L
Figure 9: Gate Charge vs Gate-Source Voltage
n-channel
Figure 12: Capacitance Variations n-channel
Figure 10: Normalized Gate Thereshold Voltage vs Temperature n-channel
Figure 13: Normalized On Resistance vs Temperature n-channel
Figure 11: Source-Drain Forward Characteristics n-channel
Figure 14: Normalized BVdss vs Temperature
n-channel
5/11
STS4C3F60L
Figure 15: Safe Operating p-channel
Figure 18: Thermal Impedance for Complementary Pair
Figure 16: Output Characteristics p-channel
Figure 19: Transfer Characteristics p-channel
Figure 17: Transconductance p-channel
Figure 20: Static Drain-Source On Resistance
p-channel
6/11
STS4C3F60L
Figure 21: Gate Charge vs Gate-Source Voltage p-channel
Figure 24: Capacitances Variations p-channel
Figure 22: Normalized Gate Thereshlod Voltage vs Temperature p-channel
Figure 25: Normalized On Resistance vs Temperature p-channel
Figure 23: Source-Drain Diode Forward Characteristics p-channel
Figure 26: Normalized BVdss vs Temperature
p-channel
7/11
STS4C3F60L
Figure 27: Unclamped Inductive Load Test
Circuit
Figure 30: Unclamped Inductive Wafeform
Figure 28: Switching Times Test Circuit For
Resistive Load
Figure 31: Gate Charge Test Circuit
Figure 29: Test Circuit For Inductive Load
Switching and Diode Recovery Times
8/11
STS4C3F60L
SO-8 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.25
a2
MAX.
0.003
0.009
1.65
0.064
a3
0.65
0.85
0.025
0.033
b
0.35
0.48
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.019
D
4.8
5.0
0.188
0.196
E
5.8
6.2
0.228
c1
45 (typ.)
1.27
e
e3
3.81
0.150
F
3.8
4.0
0.14
L
0.4
1.27
0.015
M
S
0.244
0.050
0.6
0.157
0.050
0.023
8 (max.)
9/11
STS4C3F60L
Table 10: Revision History
Date
Revision
16-Sep-2004
2
10/11
Description of Changes
Complete Version
STS4C3F60L
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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