STS3C2F100 N-CHANNEL 100V - 0.110 Ω - 3A SO-8 P-CHANNEL 100V - 0.320 Ω - 1.5A SO-8 COMPLEMENTARY PAIR STripFET™ POWER MOSFET TYPE VDSS RDS(on) ID STS3C2F100(N-Channel) STS3C2F100(P-Channel) 100 V 100 V < 0.145Ω < 0.380Ω 3.0 A 1.5 A ■ ■ ■ ■ ■ TYPICAL RDS(on) (N-Channel) = 0.110 Ω TYPICAL RDS(on) (P-Channel) = 0.320 Ω STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY ULTRA LOW GATE CHARGE ULTRA LOW ON-RESISTANCE SO-8 DESCRIPTION This MOSFET is the second generation of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ DC MOTOR DRIVES ■ AUDIO AMPLIFIER Ordering Information SALES TYPE STS3C2F100 MARKING S3C2F100 PACKAGE SO-8 PACKAGING TAPE & REEL ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM(•) Ptot Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area. June 2004 . N-CHANNEL P-CHANNEL 100 100 ± 20 3.0 1.9 12 1.5 1.0 6 2 -55 to 150 150 Unit V V V A A A W °C °C Note: P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed Rev.1.0.1 1/11 STS3C2F100 TAB.1 THERMAL DATA Rthj-amb(1) Thermal Resistance Junction-ambient 62.5 °C/W (1) when mounted on 1 in2 pad of 2 oz. copper, t ≤ 10sec. ELECTRICAL CHARACTERISTICS (Tj = 25 °C unless otherwise specified) TAB.2 OFF Symbol Parameter Test Conditions Min. Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating n-ch VDS = Max Rating TC = 125°C p-ch IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20 V V(BR)DSS n-ch p-ch Typ. Max. 100 Unit V n-ch p-ch 1 10 µA µA ±100 nA Max. Unit TAB.3 ON Symbol Parameter Test Conditions Min. VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA n-ch p-ch RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 10 V ID = 1.5 A ID = 1.0 A n-ch p-ch Typ. 2 2 V V 0.110 0.320 0.145 0.380 Ω Ω Typ. Max. Unit TAB.4 DYNAMIC Symbol 2/11 Parameter gfs (*) Forward Transconductance Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Test Conditions VDS = 20 V VDS = 30 V ID= 1.5 A ID= 1.0 A Min. n-ch p-ch 3 4 S S n-ch p-ch 460 705 pF pF VDS = 25V, f = 1 MHz, VGS = 0 n-ch p-ch 70 83 pF pF n-ch p-ch 30 30 pF pF STS3C2F100 ELECTRICAL CHARACTERISTICS (continued) TAB.5 SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions N-CHANNEL VDD = 50 V ID = 1.5 A VGS = 10 V RG = 4.7 Ω P-CHANNEL VDD = 50 V ID = 1.5 A VGS = 10 V RG = 4.7 Ω (Resistive Load, Figure 1) Min. Typ. Max. Unit n-ch p-ch 16 14 ns ns n-ch p-ch 25 20 ns ns n-ch p-ch 15 20 n-ch P-CHANNEL VDD = 80V ID = 1.5A VGS= 10V p-ch n-ch (see test circuit, Figure 2) p-ch 3.7 2.0 4.7 6.0 N-CHANNEL VDD=80V ID=3A VGS=10V 20 27 nC nC nC nC nC nC TAB.6 SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions N-CHANNEL VDD = 50 V ID = 1.5 A VGS = 10 V RG = 4.7 Ω P-CHANNEL VDD = 50 V ID = 1.5 A VGS = 10 V RG = 4.7 Ω (Resistive Load, Figure 1) Min. Typ. Max. Unit n-ch p-ch 32 33 ns ns n-ch p-ch 20 7.5 ns ns TAB.7 SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Source-drain Current ISDM (•) Source-drain Current (pulsed) VSD(∗) Forward On Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge IRRM Reverse Recovery Current ISD = 3 A ISD = 1.5 A VGS = 0 VGS = 0 N-CHANNEL ISD = 3 A di/dt = 100A/µs VDD = 50 V Tj =150 oC P-CHANNEL ISD = 1.5 A di/dt = 100A/µs VDD = 50 V Tj =150 oC (see test circuit, Figure 3) Min. Typ. Max. Unit n-ch p-ch n-ch p-ch 3.0 1.5 12 6.0 A A A A n-ch p-ch 1.2 1.2 V V n-ch p-ch 90 65 ns ns n-ch p-ch n-ch p-ch 230 175 5.0 5.4 nC nC A A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•) Pulse width limited by safe operating area. 3/11 STS3C2F100 Safe Operating Area n-ch Thermal Impedance n-ch Output Characteristics n-ch Transfer Characteristics n-ch Transconductance n-ch Static Drain-source On Resistance n-ch 4/11 STS3C2F100 Gate Charge vs Gate-source Voltage n-ch Normalized Gate Threshold Voltage vs Temperature Capacitance Variations n-ch n-ch Source-drain Diode Forward Characteristics n-ch Normalized on Resistance vs Temperature n-ch Normalized Breakdown Voltage vs Temperature n-ch 5/11 STS3C2F100 Safe Operating Area p-ch Thermal Impedance p-ch Output Characteristics p-ch Transfer Characteristics p-ch Transconductance p-ch 6/11 Static Drain-source On Resistance p-ch STS3C2F100 Gate Charge vs Gate-source Voltage p-ch Normalized Gate Threshold Voltage vs Temperature Capacitance Variations p-ch p-ch Source-drain Diode Forward Characteristics p-ch Normalized on Resistance vs Temperature p-ch Normalized Breakdown Voltage vs Temperature p-ch 7/11 STS3C2F100 Fig. 1: Switching Times Test Circuits For Resistive Load Fig. 3: Test Circuit For Diode Recovery Behaviour 8/11 Fig. 2: Gate Charge test Circuit STS3C2F100 SO-8 MECHANICAL DATA mm DIM. MIN. TYP. A a1 MAX. MIN. TYP. 1.75 0.1 0.003 0.009 1.65 0.65 MAX. 0.068 0.25 a2 a3 inch 0.064 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45 (typ.) D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8 (max.) 0016023 9/11 STS3C2F100 Revision History Date Revision Friday 18 June 2004 1.0.1 10/11 Description of Changes FIRST ISSUE STS3C2F100 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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