TDA7440D TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR 1 ■ ■ ■ ■ ■ ■ 2 FEATURES Figure 1. Package INPUT MULTIPLEXER – 4 STEREO INPUTS – SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: – TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY – INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS SO-28 Table 1. Order Codes Part Number Package TDA7440D SO-28 TDA7440D013TR Tape & Reel Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained DESCRIPTION The TDA7440D is a volume tone (bass and treble) balance (Left/Right) processor for quality audio applications in Hi-Fi systems. Figure 2. Block Diagram MUXOUTL L-IN1 4 INL 8 TREBLE(L) 9 18 14 100K L-IN2 BOUT(L) BIN(L) 15 RB 5 100K L-IN3 G 6 VOLUME TREBLE BASS 27 SPKR ATT LEFT LOUT 100K L-IN4 7 100K R-IN1 21 0/30dB 2dB STEP 3 I2CBUS DECODER + LATCHES 22 20 100K R-IN2 DIG_GND 2 100K R-IN3 SCL SDA VOLUME G TREBLE BASS 26 SPKR ATT RIGHT ROUT 1 VREF 100K R-IN4 24 28 100K SUPPLY INPUT MULTIPLEXER + GAIN RB 10 MUXOUTR April 1999 25 11 INR 19 TREBLE(R) 12 BIN(R) 13 BOUT(R) VS AGND 23 CREF D98AU883 REV. 3 1/17 TDA7440D Figure 3. Pin Connection (Top view) R_IN3 1 28 R_IN4 R_IN2 2 27 LOUT R_IN1 3 26 ROUT L_IN1 4 25 AGND L_IN2 5 24 VS L_IN3 6 23 CREF L_IN4 7 22 SDA MUXOUTL 8 21 SCL IN(L) 9 20 DIG-GND MUXOUT(R) 10 19 TREBLE(R) IN(R) 11 18 TREBLE(L) BIN(R) 12 17 N.C. BOUT(R) 13 16 N.C. BIN(L) 14 15 BOUT(L) D98AU884 Table 2. Absolute Maximum Ratings Symbol VS Parameter Operating Supply Voltage Tamb Operating Ambient Temperature Tstg Storage Temperature Range Value Unit 10.5 V 0 to 70 °C -55 to 150 °C Value Unit 85 °C/W Table 3. Thermal Data Symbol Rth j-pin Parameter Thermal Resistance Junction-pins Table 4. Quick Reference Data Symbol Parameter Min. Typ. Max. 9 10.2 Unit VS Supply Voltage 6 VCL Max. input signal handling 2 THD Total Harmonic Distortion V = 1Vrms f = 1KHz S/N Signal to Noise Ratio Vout = 1Vrms (mode = OFF) 106 dB SC Channel Separation f = 1KHz 90 dB Input Gain in (2dB step) Volume Control (1dB step) 0.1 % 0 30 dB -47 0 dB Treble Control (2dB step) -14 +14 dB Bass Control (2dB step) -14 +14 dB Balance Control 1dB step -79 0 dB Mute Attenuation 2/17 0.01 V Vrms 100 dB TDA7440D Table 5. Electrical Characteristcs Refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified. Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS Supply Voltage 6 9 10.2 V IS Supply Current 4 7 10 mA Ripple Rejection 60 90 SVR dB INPUT STAGE RIN Input Resistance 70 100 VCL Clipping Level THD = 0.3% 2 2.5 Vrms SIN Input Separation The selected input is grounded through a 2.2µ capacitor 80 100 dB 130 KΩ Ginmin Minimum Input Gain -1 0 1 dB Ginman Maximum Input Gain 29 30 31 dB Step Resolution 1.5 2 2.5 dB Input Resistance 20 33 50 KΩ Gstep VOLUME CONTROL Ri Control Range 45 47 49 dB AVMAX Max. Attenuation 45 47 49 dB ASTEP Step Resolution CRANGE EA ET VDC Amute Attenuation Set Error Tracking Error DC Step 0.5 1 1.5 dB AV = 0 to -24dB -1.0 0 1.0 dB AV = -24 to -47dB -1.5 0 1.5 dB AV = 0 to -24dB 0 1 dB AV = -24 to -47dB 0 2 dB 0 0.5 3 mV mV adjacent attenuation steps from 0dB to AV max Mute Attenuation 80 100 +12.0 +14.0 dB BASS CONTROL (1) Gb BSTEP RB Control Range Max. Boost/cut +16.0 dB Step Resolution 1 2 3 dB Internal Feedback Resistance 33 44 55 KΩ +13.0 +14.0 +15.0 dB 1 2 3 dB Control Range 70 76 82 dB Step Resolution 0.5 1 1.5 dB -1.5 0 1.5 dB TREBLE CONTROL (1) Gt TSTEP Control Range Max. Boost/cut Step Resolution SPEAKER ATTENUATORS CRANGE SSTEP EA Attenuation Set Error AV = 0 to -20dB VDC DC Step adjacent attenuation steps AV = -20 to -56dB Amute Mute Attenuation -2 80 0 2 dB 0 3 mV 100 dB NOTE1: 1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device. 2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry. 3/17 TDA7440D Table 5. Electrical Characteristcs (continued) Refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified. Symbol Parameter Test Condition Min. Typ. 2.1 2.6 Max. Unit AUDIO OUTPUTS VCLIP Clipping Level d = 0.3% Vrms RL Output Load Resistance 2 KΩ RO Output Impedance 10 30 50 Ω VDC DC Voltage Level 3.5 3.8 4.1 V 5 15 µV 0 1 dB 0 2 GENERAL ENO Output Noise All gains = 0dB; BW = 20Hz to 20KHz flat Et Total Tracking Error AV = 0 to -24dB AV = -24 to -47dB All gains 0dB; VO = 1Vrms S/N Signal to Noise Ratio SC Channel Separation Left/Right d 106 dB 80 100 dB AV = 0; VI = 1Vrms Distortion dB 95 0.01 0.08 % 1 V BUS INPUT VIL Input Low Voltage VIH Input High Voltage IIN Input Current VIN = 0.4V VO Output Voltage SDA Acknowledge IO = 1.6mA 3 V -5 0 5 µA 0.4 0.8 V Figure 4. Test Circuit 5.6K 5.6nF 100nF 2.2µF MUXOUTL L-IN1 0.47µF L-IN2 15 RB G VOLUME TREBLE 27 SPKR ATT LEFT BASS LOUT 7 100K 21 0/30dB 2dB STEP 3 I2CBUS DECODER + LATCHES 22 20 100K SCL SDA DIG_GND 2 0.47µF R-IN3 BOUT(L) 14 100K 0.47µF R-IN2 BIN(L) 100K 6 0.47µF R-IN1 18 100K 0.47µF L-IN4 TREBLE(L) 9 5 0.47µF L-IN3 INL 8 4 100nF 100K VOLUME G TREBLE 26 SPKR ATT RIGHT BASS ROUT 1 VREF 0.47µF R-IN4 0.47µF 100K 24 28 100K SUPPLY INPUT MULTIPLEXER + GAIN 10 MUXOUTR INR 11 19 TREBLE(R) 2.2µF 5.6nF 4/17 25 RB AGND 12 13 23 BIN(R) BOUT(R) CREF 100nF 5.6K VS 100nF 10µF D98AU885 TDA7440D 3 APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7440D audioprocessor provides 3 bands tones control. 3.1 Bass Stage Several filter types can be implemented, connecting external components to the Bass IN and OUT pins. The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows: 1 F C = ----------------------------------------------------------------2 ⋅ π ⋅ R1 ⋅ R2 ⋅ C1 ⋅ C2 R2 C2 + R2 C1 + R i C1 A V = --------------------------------------------------------------R2 C1 + R2 C2 R1 ⋅ R2 ⋅ C1 ⋅ C2 Q = -------------------------------------------------R2 C1 + R2 C2 Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be: AV – 1 C1 = -----------------------------------------2 ⋅ π ⋅ FC ⋅ Ri ⋅ Q 2 2 Q ⋅ C1 C2 = -----------------------------2 AV – 1 – Q AV – 1 – Q R2 = ---------------------------------------------------------------------2 ⋅ π ⋅ C1 ⋅ F C ⋅ ( A V – 1 ) ⋅ Q Figure 5. Ri internal IN OUT C1 C2 R2 D95AU313 Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and an external capacitor connected between treble pins and ground. Typical responses are reported in Figg. 14 to 17. CREF The suggested 10mF reference capacitor (CREF) value can be reduced to 4.7mF if the application requires faster power ON. 5/17 TDA7440D Figure 6. THD vs. frequency Figure 9. Bass response Ri = 44kΩ C9 = C10 = 100nF (Bout, Bin) R3 = 5.6kΩ Figure 7. THD vs. RLOAD Figure 8. Channel separation vs. frequency 6/17 Figure 10. Treble responsey TDA7440D 4 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7440D and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 4.1 Data Validity As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.2 Start and Stop Conditions As shown in fig. 12 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 4.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 13). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 4.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 11. Data Validity on the I2CBUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 12. Timing Diagram of I2CBUS SCL I2CBUS SDA D99AU1032 START STOP Figure 13. Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START D99AU1033 ACKNOWLEDGMENT FROM RECEIVER 7/17 TDA7440D 5 SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: ■ ■ ■ ■ ■ A start condition (S) A chip address byte, containing the TDA7440D A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P) CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA 1 to DATA n LSB X X B DATA MSB ACK LSB DATA ACK P D96AU420 ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment 5.1 EXAMPLES 5.1.1 No Incremental Bus The TDA7440D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-datas (all these data concern the subaddress selected), a stop condition. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA LSB X X MSB 0 D3 D2 D1 D0 ACK LSB DATA ACK P D96AU421 5.1.2 Incremental Bus The TDA7440D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent in the loop etc, and at the end it receivers the stop condition. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 D96AU422 8/17 1 0 0 0 MSB ACK X DATA 1 to DATA n LSB X X 1 D3 D2 D1 D0 ACK MSB LSB DATA ACK P TDA7440D 5.2 POWER ON RESET CONDITION Table 6. INPUT SELECTION IN2 INPUT GAIN 28dB VOLUME MUTE BASS 0dB TREBLE 2dB SPEAKER MUTE 5.3 DATA BYTES Address = 88 HEX (ADDR:OPEN). Table 7. FUNCTION SELECTION: First byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 X X X B 0 0 0 0 INPUT SELECT X X X B 0 0 0 1 INPUT GAIN X X X B 0 0 1 0 VOLUME X X X B 0 0 1 1 BASS X X X B 0 1 0 0 NOT USED X X X B 0 1 0 1 TREBLE X X X B 0 1 1 0 SPEAKER ATTENUATE "R" X X X B 0 1 1 1 SPEAKER ATTENUATE "L" B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON’T CARE In Incremental Bus Mode, the "not used" function must be addressed in any case. For example to refresh "Volume = 0dB" and Speaker_R = -40dB", the following bytes must be sent: Table 8. SUBADDRESS XXX10010 VOLUME DATA X0000000 BUS DATA XXXX1111 NOT USED DATA XXXX1111 TREBLE DATA XXXX1111 SPEAKER_R DATA X0000010 Table 9. INPUT SELECTION MSB LSB INPUT MULTIPLEXER D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 IN4 X X X X X X 0 1 IN3 X X X X X X 1 0 IN2 X X X X X X 1 1 IN1 9/17 TDA7440D 5.3 DATA BYTES (continued) Table 10. INPUT GAIN SELECTION MSB D7 D6 D5 D4 LSB INPUT GAIN D3 D2 D1 D0 2dB STEPS 0 0 0 0 0dB 0 0 0 1 2dB 0 0 1 0 4dB 0 0 1 1 6dB 0 1 0 0 8dB 0 1 0 1 10dB 0 1 1 0 12dB 0 1 1 1 14dB 1 0 0 0 16dB 1 0 0 1 18dB 1 0 1 0 20dB 1 0 1 1 22dB 1 1 0 0 24dB 1 1 0 1 26dB 1 1 1 0 28dB 1 1 1 1 30dB LSB VOLUME D3 D2 D1 D0 1dB STEPS 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB GAIN = 0 to 30dB Table 11. VOLUME SELECTION MSB D7 D6 D5 0 0 0 0 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB X 1 1 1 VOLUME = 0 to 47dB/MUTE 10/17 D4 0dB X X X MUTE TDA7440D 5.3 DATA BYTES (continued) Table 12. BASS SELECTION MSB D7 D6 D5 D4 LSB BASS D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB LSB TREBLE D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB Table 13. TREBLE SELECTION MSB D7 D6 D5 D4 11/17 TDA7440D 5.3 DATA BYTES (continued) Table 14. SPEAKER ATTENUATE SELECTION MSB D7 12/17 D6 D5 D4 D3 LSB SPEAKER ATTENUATION D2 D1 D0 1dB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 1 1 1 1 -72dB X X X MUTE TDA7440D Figure 17. PINS: 8, 10 Figure 14. PINS: 23 VS VS VS VS 20µA 20K CREF MIXOUT 20K GND D96AU430 D96AU426 Figure 18. PINS: 19, 11 Figure 15. PINS: 26, 27 VS VS 20µA 24 ROUT LOUT INL INR 20µA 33K D96AU427 VREF D96AU434 Figure 19. PINS: 12, 14 Figure 16. PINS: 1, 2, 3, 4, 5, 6, 7, 28 VS VS 20µA 20µA IN 100K VREF 44K D96AU425 BIN(L) BIN(R) D96AU428 13/17 TDA7440D Figure 20. PINS: 13, 15 Figure 22. PIN: 20 VS 20µA 20µA SCL 44K BOUT(L) D96AU424 BOUT(R) D96AU429 Figure 21. PINS: 18, 19 Figure 23. PIN 21 VS 20µA 20µA SDA TREBLE(L) TREBLE(R) 50K D96AU433 14/17 D96AU423 TDA7440D Figure 24. SO-28 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S OUTLINE AND MECHANICAL DATA SO-28 8 ° (max.) 15/17 TDA7440D Table 15. Revision History Date Revision January 2004 1 First Issue June 2004 3 Modified the style-sheet in compliance with the last revision of the “Corporate Technical Pubblications Design Guide”. 16/17 Description of Changes TDA7440D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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