TDA7300 DIGITAL CONTROLLED STEREO AUDIO PROCESSOR SINGLE SUPPLY OPERATION FOUR STEREO INPUT SOURCE SELECTION MONO INPUT TREBLE, BASS, VOLUME, AND BALANCE CONTROL FOUR INDEPENDENT SPEAKER CONTROL (FRONT/REAR) SINGLE SUPPLY OPERATION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS VERY LOW NOISE AND VERY LOW DISTORTION POP FREE SWITCHING DESCRIPTION The TDA7300 is a volume, tone (bass and treble), balance (left/right) and fader (front/rear) proces- DIP28 SO28 ORDERING NUMBERS: TDA7300 TDA7300D sor for high quality audio applications in car radio and Hi-Fi systems. Control is accomplished by serial bus microprocessor interface. The AC signal setting is obtained by resistor networks and analog switches combined with operational amplifiers. The results are: low noise, low distortion and high dynamic range. BLOCK DIAGRAM May 1991 1/16 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. TDA7300 PIN CONNECTION (Top view) ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Value Supply Voltage (VS1) Unit 18 V Tamb Operating Ambient Temperature Range -40 to +85 °C Tstg Storage Temperature -40 to 150 °C THERMAL DATA Symbol R th j-pins Description Thermal Resistance Junction-pins Max SO28 DIP28 Unit 85 65 °C/W ELECTRICAL CHARACTERISTICS (Tamb = 25°C, VS1 = 12V or VS2 = 8.5V , RL = 10kΩ and Rg = 600Ω , f = 1KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY (1) VS1 Supply Voltage VS1 10 12 16 V VS2 Supply Voltage VS2 6 8.5 10 V mA IS2 Supply Current 15 30 40 Vref Reference Voltage (pin 7) 3.5 4.3 5 SVR Ripple Rejection at VS1 f = 300Hz to 10KHz 80 97 dB SVR Ripple Rejection at VS2 f = 300Hz to 10KHz 50 58 dB 30 45 KΩ Vrms V INPUT SELECTORS Ri Input Resistance VIN max Max. Input Signal GV = 0dB 1.5 2.2 INS Input Separation f = 1KHz (2) 90 100 dB f = 10KHz (2) 70 80 dB 3.5 4.3 Vi 2/16 (DC) Input DC Voltage d = 0.3% 5 V TDA7300 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit VOLUME CONTROLS Control Range Gmax 78 Max Gain 8 10 Max Attenuation 64 68 2 12 dB dB 3 dB Attenuator Set Error 2 dB Tracking Error 2 dB 38 41 dB 2 3 dB Attenuator Set Error 2 dB Tracking Error 2 dB Step Resolution GV = -50 to 10dB dB SPEAKER ATTENUATORS Control Range 35 Step Resolution BASS AND TREBLE CONTROL (3) Control Range ±15 Step Resolution 2.5 dB 3.5 dB AUDIO OUTPUT VO Max. Output Voltage RL Output Load Resistance CL Output Load Capacitance RO Output Resistance VO(DC) DC Voltage Level d = 0.3% 1.5 2.2 Vrms 2 KΩ 1 nF 70 150 Ω 3.8 4.5 V BW = 22Hz to 22KHz, Gv = 0dB 6 15 Curve A 4 µV 3 GENERAL e NO S/N d SC Output Noise Gv = 0dB Signal to Noise Ratio All gain = 0dB VO = 1Vrms BW = 22Hz to 22KHz Distortion f = 1KHz; VO = 1V; Gv = 0 Frequency Response (-1dB) Gv = 0 Channnel Separation left/right f = 1KHz f = 10KHz High Low 105 0.01 dB 0.1 % 20 KHz Hz 20 90 70 100 80 dB dB BUS INPUTS VIL Input LOW Voltage VIH Input HIGH Voltage VO Output Voltage SDA Acknowledge Digital Input Current 0.8 2.4 I = 1.6mA -5 V V 0.4 V +5 µA Notes: (1) The circuit can be supplied either at VS1 or without the use of the internal voltage regulator at VS2 . The circuit also operates at a supply voltage VS1 lower than 10V. In this case the ripple rejection of VS2 is valid, because the voltage regulator saturates to a saturation voltage of about 0.8V. (2) The selected input is grounded thru the 2.2µF capacitor. (3) Bass and Treble response see attached diagram. The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network. 3/16 TDA7300 Figure 1: Application Circuit 4/16 TDA7300 Figure 2: P.C. Board and Components Layout of the Fig.1 (1:1 scale) 5/16 TDA7300 Figure 3: Total Output Noise vs. Volume Setting Figure 4: Signal to Noise Ratio vs. Volume Setting Figure 5: Distortion + Noise vs. Frequency Figure 6: Distortion vs. Output Voltage Figure 7: Distortion vs. Load Resistance Figure 8: Channel Separation (L1 - R1) vs. Frequency 6/16 TDA7300 Figure 9: Input Separation (L1 - L2) vs. (VS1 ) Frequency Figure 10: Supply Voltage Rejection (VS1) vs. Frequency Figure 11: Supply Voltage Rejection (VS2 ) vs. Frequency Figure 12: Supply Voltage Rejection vs. VS1 Figure 13: Supply Voltage Rejection vs. VS2 Figure 14: Clipping Level (Vrms) vs. Supply Voltage 7/16 TDA7300 APPLICATION INFORMATION Volume Control Concept Traditional electronic volume control circuits use a multiplier technique with all the disadvantages of high noise and distortion. The used concept, as shown in Fig. 15 with digital switched resistor dividers, provides extremely low noise and distortion. The multiplexing of the resistive dividers is realized with a multiple-input operational amplifier. Figure 16: Bass Control Bass and Treble Control The principle operation of the bass control is shown in Fig. 16. The external filter together with the internal buffer allows a flexible filter design according to the different requirements in car radios. The function of the treble is similar to the bass. A typical curve is shown in Fig.19. Outputs A special class-A output amplifier with a modulated sink current provides low distortion and ground compatibility with low current consumption. Figure 17: Quiescent Current vs. Supply Voltage Figure 15: Volume Control Figure 18: Quiescent Current vs. Temperature 8/16 TDA7300 APPLICATION INFORMATION (continued) Figure 19: Typical Tone Response Figure 20: Complete Car-Radio System using Digital Controlled Audio Processor 9/16 TDA7300 APPLICATION INFORMATION (continued) SERIAL BUS INTERFACE S-BUS Interface and I2CBUS Compatibility Data transmission from microprocessor to the TDA7300 and viceversa takes place thru the 3wire S-BUS interface, consisting of the three lines SDA, SCL, SEN. If SDA and SEN inputs are short-circuited together, then the TDA7300 appears as a standard I2CBUS slave. According to I2CBUS specification the S-BUS lines are connected to a positive supply voltage via pull-up resistors. LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. S-bus: the start/stop conditions (points 1 and 6) are detected exclusively by a transition of the SEN line (1 → 0 / 0 → 1) while the SCL line is at the HIGH level. The SDA line is only allowed to change during the time the SCL line is low (points 2, 3, 4, 5). After the start information (point 1) the SEN line returns to the HIGH level and remains unchanged for all the time the transmission is performed. Data Validity As shown in fig. 21, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Figure 21: Data Validity on the I2CBUS Start and Stop Conditions I2CBUS: as shown in fig.22 a start condition is a HIGH to Figure 22: Timing Diagram of S-BUS and I2CBUS 10/16 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 23). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. TDA7300 APPLICATION INFORMATION (continued) Figure 23: Acknowledge on the I2CBUS Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7300 address (the 8th bit of the byte must be 0). The TDA7300 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) TDA7300 ADDRESS MSB S 1 first byte 0 0 0 LSB 1 0 0 MSB LSB DATA 0 ACK MSB LSB DATA ACK ACK P Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop SOFTWARE SPECIFICATION Chip address (TDA7300 address) MAX CLOCK SPEED 100kbits/s 1 0 0 0 1 MSB MSB 0 1 1 0 0 1 1 1 B2 0 1 0 1 0 1 1 B1 B1 B1 B1 B1 X 0 1 0 0 IIII I LSB Status after power-on reset DATA BYTES 0 1 1 1 1 0 0 0 0 B0 B0 B0 B0 B0 X C3 C3 A2 A2 A2 A2 A2 S2 C2 C2 LSB A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 S1 S0 C1 C0 C1 C0 Function Volume Control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio switch Bass control Treble control Volume Speaker Audio Switch Bass Treble –68dB –38dB Mono +2.5dB +2.5dB X = don’t care Ax = 2dB steps Bx = 10dB steps Cx = 2.5dB steps 11/16 TDA7300 SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) VOLUME MSB 0 0 LSB 0 0 B2 B1 B0 B2 B1 B0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Volume 2dB Steps 0 -2 -4 -6 -8 Not allowed Not allowed Not allowed Volume 10dB steps +10 0 -10 -20 -30 -40 -50 -60 For example if you want setting the volume at -32dB the 8 bit string is: 0 0 1 0 0 0 0 1 SPEAKER ATTENUATORS MSB 1 1 1 1 LSB 0 0 1 1 0 1 0 1 B1 B1 B1 B1 0 0 1 1 B0 B0 B0 B0 0 1 0 1 A2 A2 A2 A2 A1 A1 A1 A1 A0 A0 A0 A0 Speaker LF Speaker RF Speaker LR Speaker RR 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -2 -4 -6 -8 Not allowed Not allowed Not allowed 0 -10 -20 -30 For example attenuation of 24dB on speaker RF is given by: 1 0 1 1 0 0 1 0 12/16 TDA7300 SOFTWARE SPECIFICATION (continued) AUDIO SWITCH - Select the input Channel to Activate MSB 0 LSB 1 0 X X S2 S1 S0 Audio Switch X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Stereo 1 Stereo 2 Stereo 3 Stereo 4 Mono Not Allowed Not Allowed Not Allowed X = don’t care For example to set the stereo 2 channel the 8 bit string may be: 0 1 0 0 0 0 0 1 BASS AND TREBLE - Control Range of ± 15dB (boost and cut) Steps of 2.5dB 0 0 1 1 1 1 0 1 C3 C3 C2 C2 C1 C1 C0 C0 Bass Treble 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 - 15 - 15 - 12.5 - 10 - 7.5 -5 - 2.5 -0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 2.5 5 7.5 10 12.5 15 15 C3 = Sign For example Bass at -12.5dB is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0 13/16 TDA7300 DIP28 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 E 0.009 1.27 D 15.2 MAX. 0.012 0.050 37.34 16.68 1.470 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F 14/16 inch 14.1 0.555 I 4.445 0.175 L 3.3 0.130 TDA7300 SO28 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S 8° (max.) 15/16 TDA7300 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 16/16