STMICROELECTRONICS VNQ600A-8960

VNQ600A(8960)
®P
QUAD CHANNEL HIGH SIDE SOLID STATE RELAY
TYPE
VNQ600A(8960)
RDS(on)(*)
30mΩ
Ilim
25A
VCC
36 V
(*) Per each channel at VCC=13V
DC SHORT CIRCUIT CURRENT: 25A
■ CMOS COMPATIBLE INPUTS
■ PROPORTIONAL LOAD CURRENT SENSE
■ UNDERVOLTAGE & OVERVOLTAGE
nSHUT-DOWN
■ OVERVOLTAGE CLAMP
■ THERMAL SHUT-DOWN
■ CURRENT LIMITATION
■ VERY LOW STAND-BY POWER DISSIPATION
■ PROTECTION AGAINST:
nLOSS OF GROUND & LOSS OF VCC
■ REVERSE BATTERY PROTECTION (**)
■
DESCRIPTION
The VNQ600A(8960) is a quad HSD formed by
assembling two VND600 chips in the same SO-28
ABSOLUTE MAXIMUM RATING
SO-28 (DOUBLE ISLAND)
ORDER CODES
PACKAGE
TUBE
T&R
SO-28
VNQ600A(8960) VNQ600A(8960)TR
package. The VND600 is a monolithic device
designed in| STMicroelectronics VIPower M0-3
Technology. The VNQ600A(8960) is intended for
driving any type of multiple loads with one side
connected to ground. This device has four
independent channels and four analog sense
outputs which deliver currents proportional to the
outputs currents. Active current limitation
combined with thermal shut-down and automatic
restart protect the device against overload. Device
automatically turns off in case of ground pin
disconnection.
Symbol
VCC
-VCC
IOUT
IR
IIN
Parameter
Supply voltage (continuous)
Reverse supply voltage (continuous)
Output current (continuous), for each channel
Reverse output current (continuous), for each channel
Input current
VCSENSE
Current sense maximum voltage
IGND
VESD
EMAX
Ptot
Tj
Tstg
Value
41
-0.3
15
-15
+/- 10
-3
Unit
V
V
A
A
mA
V
+15
-200
V
mA
- INPUT
4000
V
- CURRENT SENSE
2000
V
- OUTPUT
5000
V
- VCC
Maximum Switching Energy
5000
V
126
mJ
6.25
Internally Limited
-55 to 150
W
°C
°C
Ground current at Tpins < 25°C (continuous)
Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF)
(L=0.11mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=40A)
Power dissipation (per island) at Tlead=25°C
Junction operating temperature
Storage temperature
(**) See application schematic at page 9.
June 2003
1/18
VNQ600A(8960)
BLOCK DIAGRAM
VCC 1,2
OVERVOLTAGE
UNDERVOLTAGE
DEMAG 1
DRIVER 1
OUTPUT 1
INPUT 1
ILIM1
LOGIC
IOUT1
INPUT 2
K
CURRENT
SENSE 1
DEMAG 2
DRIVER 2
GND 1,2
OUTPUT 2
ILIM2
OVERTEMP. 1
IOUT2
OVERTEMP. 2
K
OVERVOLTAGE
CURRENT
SENSE 2
VCC 3,4
UNDERVOLTAGE
DEMAG 3
DRIVER 3
OUTPUT 3
INPUT 3
ILIM3
LOGIC
IOUT3
INPUT 4
K
CURRENT
SENSE 3
DEMAG 4
DRIVER 4
GND 3,4
OUTPUT 4
ILIM4
OVERTEMP. 3
OVERTEMP. 4
2/18
IOUT4
K
CURRENT
SENSE 4
VNQ600A(8960)
CURRENT AND VOLTAGE CONVENTIONS
IS1,2
VCC1,2
VCC1,2
IS3,4
VCC3,4
IIN1
ISENSE1
VIN1
IIN2
VSENSE1
ISENSE2
VIN2
VSENSE2
VIN3
IIN3
ISENSE3
VSENSE3 IIN4
VIN4 ISENSE4
VCC3,4
INPUT1
IOUT1
CUR. SENSE1
OUTPUT1
IOUT2
INPUT2
CUR. SENSE2
INPUT3
VOUT2
IOUT3
OUTPUT3
CUR. SENSE3
INPUT4
VOUT1
OUTPUT2
IOUT4
VOUT3
OUTPUT4
VOUT4
CUR. SENSE4
VSENSE4
GND1,2
GND3,4
IGND1,2
IGND3,4
CONNECTION DIAGRAM (TOP VIEW)
VCC1,2
1
28
GND 1,2
VCC1,2
OUTPUT 1
INPUT2
OUTPUT 1
INPUT1
OUTPUT 1
CURRENT SENSE 1
OUTPUT 2
CURRENT SENSE 2
OUTPUT 2
VCC1,2
OUTPUT 2
VCC3,4
OUTPUT 3
GND 3,4
OUTPUT 3
INPUT4
OUTPUT 3
INPUT3
OUTPUT 4
CURRENT SENSE 3
OUTPUT 4
CURRENT SENSE 4
OUTPUT 4
VCC3,4
14
15
VCC3,4
3/18
VNQ600A(8960)
THERMAL DATA (Per island)
Symbol
Rthj-lead
Rthj-amb
Rthj-amb
Parameter
Thermal resistance Junction-lead
Thermal resistance Junction-ambient (one chip ON)
Thermal resistance Junction-ambient (two chips ON)
Value
20
60 (*)
46 (*)
Unit
°C/W
°C/W
°C/W
(*) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC pins.
Horizontal mounting and no artificial air flow.
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C; unless otherwise specified)
(Per each channel)
POWER
Symbol
VCC (**)
VUSD (**)
VOV (**)
RON
Vclamp
Parameter
Operating supply voltage
Undervoltage shut-down
Overvoltage shut-down
Test Conditions
Min
5.5
3
36
IOUT1,2,3,4=5A; Tj=25°C; VCC=13V
30
Unit
V
V
V
mΩ
On state resistance
IOUT1,2,3,4=5A; Tj=25°C; 8V < VCC < 36V
32
mΩ
Clamp Voltage
- 40°C < Tj < 150°C; VCC=13V
ICC=20mA (see note 1)
48
12
60
55
40
mΩ
V
µA
12
25
µA
6
50
0
5
3
mA
µA
µA
µA
µA
41
Off State; VCC=13V; VIN=VOUT=0V
Typ
13
4
Max
36
5.5
Off State; VCC=13V; VIN=VOUT=0V;
IS (**)
Supply current
Tj=25°C
On State; VCC=13V; VIN=5V; IOUT=0A;
RSENSE=3.9KΩ
IL(off1)
IL(off2)
IL(off3)
IL(off4)
Off state output current
Off State Output Current
Off State Output Current
Off State Output Current
VIN=VOUT=0V
VIN=0V; VOUT=3.5V
VIN=VOUT=0V; VCC=13V; Tj=125°C
VIN=VOUT=0V; VCC=13V; Tj=25°C
0
-75
Test Conditions
RL=2.6Ω channels 1,2,3,4 (see fig. 1)
RL=2.6Ω channels 1,2,3,4 (see fig. 1)
RL=2.6Ω channels 1,2,3,4 (see fig. 1)
RL=2.6Ω channels 1,2,3,4 (see fig. 1)
Min
Typ
40
40
0.20
0.20
Max
Unit
µs
µs
V/µs
V/µs
Min
25
Typ
40
Max
70
Unit
A
70
A
200
°C
SWITCHING (VCC=13V)
Symbol
tD(on)
tD(off)
(dVOUT/dt)on
(dVOUT/dt)off
Parameter
Turn-on delay time
Turn-off delay time
Turn-on voltage slope
Turn-off voltage slope
PROTECTIONS
Symbol
Ilim
TTSD
TR
Thyst
Vdemag
VON
(**) Per island
4/18
1
Parameter
DC Short circuit current
Test Conditions
VCC=13V
5.5V<VCC<36V
Thermal shut-down
temperature
Thermal reset
temperature
Thermal hysteresis
Turn-off output voltage
clamp
Output voltage drop
limitation
150
175
135
7
IOUT=2A; L=6mH
IOUT=0.5A; Tj= -40°C...+150°C
°C
15
°C
VCC-41 VCC-48 VCC-55
V
50
mV
VNQ600A(8960)
CURRENT SENSE (9V < VCC< 16V) (See Fig. 3)
Symbol
K1
dK1/K1
K2
dK2/K2
K3
dK3/K3
VSENSE1,2
Parameter
IOUT/ISENSE
Current Sense Ratio Drift
IOUT/ISENSE
Current Sense Ratio Drift
IOUT/ISENSE
Current Sense Ratio Drift
Max analog sense output
voltage
Test Conditions
IOUT1,2=0.35A; VSENSE=0.5V;
Tj= -40°C...+150°C
IOUT1 or IOUT2=0.5A;
VSENSE=0.5V; other channels
open; Tj= -40°C...150°C
IOUT=2A; VSENSE=2.5V; Tj=-40°C
Tj= 25°C...+150°C
IOUT1 or IOUT2=5A; VSENSE=4V;
other channels open;
Tj=-40°C...150°C
IOUT=4A; VSENSE=4V; Tj=-40°C
Tj= 25°C...+150°C
IOUT1 or IOUT2=15A; VSENSE=4V;
other channels open;
Tj=-40°C...150°C
VCC=5.5V; IOUT1,2=2A;
RSENSE=10KΩ
VCC>8V; IOUT1,2=4A;
RSENSE=10KΩ
VSENSEH
RVSENSEH
tDSENSE
Analog sense output voltage in
overtemperature condition
Analog Sense Output
Impedance in
Overtemperature Condition
Current sense delay response
Min
Typ
Max
3300
4350
6000
-10
+10
3900
4850
6000
4150
4850
5800
-6
+6
4150
4900
6000
4400
4900
5750
-6
+6
Unit
%
%
%
2
V
4
V
VCC=13V; RSENSE=3.9KΩ
VCC=13V; Tj>TTSD; All channels
open
5
V
400
Ω
to 90% ISENSE (see note 2)
500
µs
Max
1.25
Unit
V
V
V
µA
µA
V
LOGIC INPUT
Symbol
VIL
VIH
VI(hyst)
IIL
IIH
VICL
Parameter
Low level input voltage
High level input voltage
Input hysteresis voltage
Low level input current
High level input current
Input clamp voltage
Test Conditions
VIN=1.25V
VIN=3.25V
IIN=1mA
IIN= -1mA
Min
3.25
0.5
20
6
Typ
65
75
6.8
-0.7
110
8
V
Note 1: Vclamp and VOV are correlated. Typical difference is 5V.
Note 2: current sense signal delay after positive input slope.
Note: Sense pin doesn’t have to be left floating.
5/18
2
VNQ600A(8960)
TRUTH TABLE (per channel)
CONDITIONS
Normal operation
Overtemperature
Undervoltage
Overvoltage
Short circuit to GND
Short circuit to VCC
Negative output voltage
clamp
6/18
INPUT
OUTPUT
SENSE
L
L
H
L
H
L
0
Nominal
H
L
L
L
VSENSEH
0
H
L
L
L
0
0
H
L
L
L
0
0
H
L
(Tj<TTSD) 0
H
L
L
H
(Tj>TTSD) VSENSEH
0
H
H
< Nominal
L
L
0
0
VNQ600A(8960)
ELECTRICAL TRANSIENT REQUIREMENTS
ISO T/R
7637/1
Test Levels
Test Levels
Test Levels
Test Levels
Test Levels
I
II
III
IV
Delays and Impedance
-25V
+25V
-25V
+25V
-4V
+26.5V
-50V
+50V
-50V
+50V
-5V
+46.5V
-75V
+75V
-100V
+75V
-6V
+66.5V
-100V
+100V
-150V
+100V
-7V
+86.5V
2ms, 10Ω
0.2ms, 10Ω
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
Test Pulse
1
2
3a
3b
4
5
ISO T/R
7637/1
Test Levels Result
Test Levels Result
Test Levels Result
Test Levels Result
I
II
III
IV
C
C
C
C
C
C
C
C
C
C
C
E
C
C
C
C
C
E
C
C
C
C
C
E
Test Pulse
1
2
3a
3b
4
5
Class
C
E
Contents
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure and cannot be
returned to proper operation without replacing the device.
Figure 1: Switching Characteristics (Resistive load RL=2.6Ω)
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
10%
tf
t
ISENSE
90%
INPUT
t
tDSENSE
td(on)
td(off)
t
7/18
1
VNQ600A(8960)
Figure 2: Waveforms (per each chip)
NORMAL OPERATION
INPUTn
LOAD CURRENTn
SENSEn
UNDERVOLTAGE
VCC
VUSDhyst
VUSD
INPUTn
LOAD CURRENTn
SENSEn
OVERVOLTAGE
VOV
VCC
VCC < VOV
VCC > VOV
INPUTn
LOAD CURRENTn
SENSEn
SHORT TO GROUND
INPUTn
LOAD CURRENTn
LOAD VOLTAGEn
SENSEn
SHORT TO VCC
INPUTn
LOAD VOLTAGEn
LOAD CURRENTn
SENSEn
<Nominal
<Nominal
OVERTEMPERATURE
Tj
TTSD
TR
INPUTn
LOAD CURRENTn
SENSEn
ISENSE=
VSENSEH
RSENSE
8/18
VNQ600A(8960)
APPLICATION SCHEMATIC
+5V
Rprot
INPUT1
VCC1,2
VCC3,4
Dld
Rprot
C. SENSE 1
Rprot
INPUT2
Rprot
C. SENSE 2
OUTPUT2
INPUT3
OUTPUT3
OUTPUT1
µC
Rprot
Rprot
Rprot
C. SENSE 3
OUTPUT4
INPUT4
Rprot
C. SENSE 4
GND1,2
GND3,4
RGND
RSENSE1,2,3,4
VGND
DGND
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
GND PROTECTION
REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / 2(IS(on)max).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor
or several devices have to share the same resistor then
the ST suggests to utilize Solution 2 (see below).
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating. The
same applies if the device will be subject to transients on
the VCC line that are greater than the ones shown in the
ISO T/R 7637/1 table.
9/18
1
VNQ600A(8960)
µC I/Os PROTECTION:
If a ground protection network is used and negative
transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up limit
of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 6kΩ.
Recommended Rprot value is 5kΩ.
Figure 3: IOUT/ISENSE versus IOUT
IOUT/ISENSE
6500
6000
max.Tj=-40°C
5500
max.Tj=25...150°C
5000
typical value
min.Tj=25...150°C
4500
4000
min.Tj=-40°C
3500
3000
0
2
4
6
8
10
12
14
16
IOUT (A)
10/18
VNQ600A(8960)
High Level Input Current
Off State Output Current
IL(off1) (uA)
Iih (uA)
5
5
4.5
4.5
Off state
Vcc=36V
Vin=Vout=0V
4
3.5
Vin=3.25V
4
3.5
3
3
2.5
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
100
125
150
175
Tc (°C)
Input Clamp Voltage
Input High Level
Vih (V)
Vicl (V)
3.6
8
7.8
3.4
Iin=1mA
7.6
3.2
7.4
3
7.2
2.8
7
6.8
2.6
6.6
2.4
6.4
2.2
6.2
2
6
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
Tc (°C)
Tc (°C)
Input Low Level
Input Hysteresis Voltage
Vil (V)
Vhyst (V)
2.6
1.5
1.4
2.4
1.3
2.2
1.2
2
1.1
1.8
1
0.9
1.6
0.8
1.4
0.7
1.2
0.6
1
0.5
-50
-25
0
25
50
75
Tc (°C)
11/18
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
VNQ600A(8960)
ILIM Vs Tcase
Overvoltage Shutdown
Vov (V)
Ilim (A)
50
80
48
70
Vcc=13V
46
60
44
50
42
40
40
38
30
36
20
34
10
32
30
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Turn-on Voltage Slope
Turn-off Voltage Slope
dVout/dt(on) (V/ms)
dVout/dt(off) (V/ms)
750
500
700
450
Vcc=13V
Rl=2.6Ohm
650
Vcc=13V
Rl=2.6Ohm
400
600
350
550
300
500
250
450
200
400
150
350
100
300
50
250
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (ºC)
50
75
Tc (ºC)
On State Resistance Vs Tcase
On State Resistance Vs VCC
Ron (mOhm)
Ron (mOhm)
100
80
90
70
Iout=5A
8V<Vcc<36V
80
Iout=5A
Tc= 150°C
60
70
50
60
40
50
40
Tc= 25°C
30
30
20
20
Tc= - 40°C
10
10
0
0
-75
-50
-25
0
25
50
Tc (°C)
75
100
125
150
175
5
10
15
20
25
30
35
40
Vcc (V)
12/18
VNQ600A(8960)
Maximum turn off current versus load inductance
ILMAX (A)
100
A
B
10
C
1
0.001
0.01
0.1
1
10
100
L(mH )
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
13/18
VNQ600A(8960)
SO-28 DOUBLE ISLAND THERMAL DATA
SO-28 Double island PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.5cm2, 3cm2, 6cm2).
Thermal calculation according to the PCB heatsink area
Chip 1
ON
OFF
ON
ON
Chip 2
OFF
ON
ON
ON
Tjchip1
RthA x Pdchip1 + Tamb
RthC x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
(RthA x Pdchip1) + RthC x Pdchip2 + Tamb
Tjchip2
Note
RthC x Pdchip1 + Tamb
RthA x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
Pdchip1=Pdchip2
(RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1≠Pdchip2
RthA = Thermal resistance Junction to Ambient with one chip ON
RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2
RthC = Mutual thermal resistance
Rthj-amb Vs PCB copper area in open box free air condition
RTHj_am b
(°C/W)
70
60
50
RthA
40
RthB
30
20
RthC
10
0
14/18
1
2
3
4
5
PCB Cu heatsink area (cm ^2)/island
6
7
VNQ600A(8960)
SO-28 Thermal Impedance Junction Ambient Single Pulse
Zth(°C/W)
100
0,5 cm ^2/island
3 cm ^2/island
6 cm ^2/is land
10
One channel ON
Two channels
ON on same chip
1
0.1
0.01
0.0001
0.001
0.01
0.1
1
time(s)
Thermal fitting model of a four channels HSD
in SO-28
10
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
1000
Pulse calculation formula
ZTH δ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
Tj_1
100
δ = tp ⁄ T
Thermal Parameter
Pd1
Tj_2
C13
R13
C14
R14
Pd2
R17
Tj_3
R18
C7
C8
C9
R7
R8
R9
C10
C11
C12
Pd3
Tj_4
C15
R15
R10
C16
R16
Pd4
T_amb
R11
R12
Area/island (cm2)
R1=R7=R13=R15 (°C/W)
R2=R8=R14=R16 (°C/W)
R3=R9 (°C/W)
R4=R10 (°C/W)
R5=R11 (°C/W)
R6=R12 (°C/W)
C1=C7=C13=C15 (W.s/°C)
C2=C8=C14=C16 (W.s/°C)
C3=C9 (W.s/°C)
C4=C10 (W.s/°C)
C5=C11 (W.s/°C)
C6=C12 (W.s/°C)
R17=R18 (°C/W)
0.5
0.05
0.3
3.4
11
15
30
0.001
5.00E-03
1.00E-02
0.2
1.5
5
150
6
13
8
15/18
VNQ600A(8960)
SO-28 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
2.65
0.10
MAX.
0.104
0.30
0.004
0.012
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45 (typ.)
D
17.7
E
10.00
e
18.1
0.697
10.65
0.393
1.27
e3
0.713
0.419
0.050
16.51
0.650
F
7.40
7.60
0.291
0.299
L
0.40
1.27
0.016
0.050
S
8 (max.)
16/18
2
VNQ600A(8960)
SO-28 TUBE SHIPMENT (no suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
B
28
700
532
3.5
13.8
0.6
All dimensions are in mm.
A
TAPE AND REEL SHIPMENT (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
16.4
60
22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
All dimensions are in mm.
16
4
12
1.5
1.5
7.5
6.5
2
End
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
17/18
VNQ600A(8960)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 2003 STMicroelectronics - Printed in ITALY- All Rights Reserved.
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18/18