MICREL SY58621L_10

SY58621L
Precision 3.2Gbps CML/LVPECL Backplane
Transceiver with Integrated Loopback
General Description
The SY58621L is a low jitter, high-speed transceiver
with a variable swing LVPECL transmitter buffer and a
CML high-gain receiver optimized for precision telecom
and enterprise server transmission line and backplane
data management. The SY58621L distributes data to
3.2Gbps guaranteed over temperature and voltage.
The SY58621L transmitter differential input includes
Micrel’s unique, patented 3-pin input termination
architecture that directly interfaces to any (AC- or DCcoupled) differential signal as small as 100mV
(200mVPP) without any termination resistor network in
the signal path. The receiver differential input is
optimized to interface directly to AC-coupled signals as
small as 10mV (20mVPP). The receiver output is 50_
source-terminated CML and the transmitter output is
variable swing 80mV to 800mV LVPECL with extremely
fast rise/fall time.
To support remote self-testing, the SY58621L features a
high-speed loopback test mode. The input control signal
LOOPBACK enables an internal loopback path from the
transmitter input to the receiver output.
The SY58621L operates from a 3.3V ±10% supply and
is guaranteed over the full industrial temperature range
of –40°C to +85°C. The SY58621L is part of Micrel’s
®
high-speed, Precision Edge product line. For
applications that requires a CML receiver and
transmitter, consider the SY58620L.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
Applications
∑
∑
∑
∑
Backplane management
Active cable transceivers
SONET/SDH data/clock applications
4X Fibre Channel applications
®
Precision Edge
Features
∑ Guaranteed AC performance over temperature and
voltage:
- Maximum Throughput 3.2Gbps
- <160ps tr/tf time
∑ Transmitter
- Patented input termination directly interfaces to ACor DC-coupled differential inputs
- Variable swing LVPECL output
∑ Receiver
- 32dB high-gain Input
- Internal 50Ω input termination
- Accepts AC-coupled input signals as small as 10mV
(20mvPP)
- 400mV (800mVPP) differential CML output swing
∑ Loss-of-Signal (LOS)
- High-gain, TTL-compatible LOS output with internal
4.75kΩ pull-up
- Programmable LOS level set
∑ Ultra-low jitter design
- <5psRMS random jitter
∑ Patent-pending MUX isolates the receiver and the
transmitter channels minimizing on crosstalk
∑ Selectable loopback diagnostic mode
∑ Output enables on transmitter and receiver outputs
∑ Power supply +3.3V ±10%
∑ Industrial temperature range -40°C to +85°C
∑ Available in 24-pin (4mm x 4mm) QFN
Markets
∑
∑
∑
∑
Precision telecom
Enterprise server
ATE
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2006
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SY58621L
Typical Applications
Functional Block Diagram
Note:
It is recommended that RLOSLVL ≤10kΩ. See the “Typical Operating Characteristics” section for more details.
January 2006
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SY58621L
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead Finish
SY58621LMG
QFN-24
Industrial
621L with Pb-Free bar-line indicator
NiPdAu
Pb-Free
QFN-24
Industrial
621L with Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY58621LMGTR
(2)
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25ºC, DC Electricals only.
2. Tape and Reel.
Pin Configuration
24-Pin QFN
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SY58621L
Pin Description
Inputs
Pin Number
Pin Name
23
LOOPBACK
20
/RXEN
Receiver Output Control. TTL/CMOS control input. /RXEN is an active LOW signal used to
enable the receiver outputs. /RXEN is internally connected to a 25kW pull-down resistor and will
default to a LOW state if left open. VTH = VCC/2.
1, 2
RXIN, /RXIN
Receiver Differential Input. Input accepts AC differential signals as small as 10mV (20mVPP).
Each pin internally terminates to VCC_RXIN-1.3V (internal voltage reference) through 50W. Input
will default to an indeterminate state if left open. See figure 6b.
7
/TXEN
Transmitter Output Control. TTL/CMOS control input. /TXEN is an active LOW signal used to
enable the transmitter output. /TXEN is internally connected to a 25kW pull-down resistor and
will default to a LOW state if left open. VTH = VCC/2.
14, 13
TXIN, /TXIN
Transmitter Differential Input. Input accepts AC- or DC-coupled differential signals as small as
100mV (200mVPP). Each pin terminates to the TXVT pin through 50W. Note that this input will
default to an indeterminate state if left open. See figure 6a.
9
TXVCTRL
Transmitter Output Swing Control. Input that controls the output amplitude of the transmitter.
The operating range of the control input is from VREF_CTRL (max swing) to VCC (min swing).
Control of the output swing can be obtained by using a variable resistor between VREF_CTRL and
VCC_TXQ through a wiper driving TXVCTRL. Setting TXVCTRL to VCC_TXQ sets the output swing
to min swing. Refer to the “Interface Applications” and “Output Stage” sections for more
details.
11
TXVT
January 2006
Pin Description
LOOPBACK Mode Control. TTL/CMOS control input. LOOPBACK is an active HIGH signal
used to control the LOOPBACK MUX. LOOPBACK is internally connected to a 25kW pulldown resistor and will default to a LOW state if left open. VTH = VCC/2.
Input Termination Center-Tap. Each side of the transmitter differential input pair terminates to
the TXVT pin. The TXVT pin provides a center-tap to a termination network for maximum
interface flexibility. Refer to the “Input Stage” section for more details.
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SY58621L
Outputs
Pin Number
Pin Name
22
LOS
19
17, 16
LOSLVL
RXQ, /RXQ
Pin Description
Loss-of-Signal Output. TTL-compatible output with internal 4.75kW pull-up resistor. Loss-ofSignal asserts to logic HIGH when the receiver input amplitudes fall below the threshold set
by LOSLVL.
RX Loss-of-Signal Level Set. A resistor (RLOSLVL) connected between LOSLVL and VCC sets
the threshold for the data input amplitude at which the LOS output is asserted. Default is max
sensitivity. LOSLVL is used to set the Loss-of-Signal (LOS) voltage. It is internally connected
to a 2.8kW pull-down resistor to an internal VREF voltage source. See “Typical Operating
Characteristics,” and “Application Implementation” sections for more details.
Receiver Differential Output. Output is CML compatible. Refer to the “Truth Table” and
“Output Stage” sections for more details. Unused output pair may be left open. The output is
designed to drive 400mV (800mVPP) into 50W to VCC or 100W across the pair.
5, 6
TXQ, /TXQ
Transmitter differential Variable Swing Output. Output is LVPECL-compatible. Please refer
to the “Truth Table” section for details. Unused output pair may be left open. Each output is
designed to drive 80mV (min) to 800mV (typ) into 50_ to VCC-2V depending on TXVCTRL.
8
VREF_CTRL
Transmitter Output Reference Voltage. Output biases to VCC_TXQ-1.3V. Connecting VREF_CTRL
to TXVCTRL sets the transmitter output swing to max swing.
TXVREF-AC
Transmitter Input Reference Voltage. This output biases to VCC-1.3V. It is used when AC
coupling the transmitter input. For AC-coupled applications, connect TXVREF-AC to the
TXVT pin and bypass with a 0.01µF low ESR capacitors to VCC. See “Input Stage” section for
more details. Maximum sink/source current is ±1.5mA.
10
Power Pins
Pin Number
Pin Name
Pin Description
3, 24
GND,
Exposed Pad
12, 15, 18
VCC
3.3V ±10% Positive Power Supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place
as close to each VCC pins as possible. Power pins are not connected internally and must be
connected to the same power supply externally.
21
VCC_RXIN
3.3V ±10% Receive Input Power Supply. Bypass with 0.1µF//0.01µF low ESR capacitors and
place as close to the VCC_RXIN pin as possible. Power pins are not connected internally and
must be connected to the same power supply externally.
4
VCC_TXQ
3.3V ±10% Output Transmit Power Supply. Bypass with 0.1µF//0.01µF low ESR capacitors
and place as close to the VCC_TXQ pin as possible. Power pins are not connected internally
and must be connected to the same power supply externally.
Ground. GND pins and exposed pad must be connected to the same ground plane.
Truth Table
LOOPBACK
RXQ
0
RXIN
TXIN
1
TXIN
RXIN
January 2006
TXQ
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SY58621L
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage
(VCC, VCC_TXQ, VCC_RXIN) .........................–0.5V to +4.0V
Input Voltage
LOSLVL.............................................. VREF –1.2V to VCC
LOOPBACK ................................................–0.5V to VCC
/TXEN, /RXEN ............................................–0.5V to VCC
TXVCTRL.............................VREF_CTRL –1.2V to VCC
TXIN, /TXIN.................................................–0.5V to VCC
LVPECL Output Current (IOUT)
TXQ, /TXQ
Continuous ...........................................................±50mA
Surge..................................................................±100mA
Source or Sink Current on
TXVT ..................................................................±100mA
LOS ........................................................................±5mA
RXQ, /RXQ...........................................................±25mA
RXIN, /RXIN.........................................................±10mA
TXIN, /TXIN..........................................................±50mA
TXVREF-AC, VREF-CTRL ..................................±2mA
Lead Temperature (soldering, 20sec.) ....................... 260°C
Storage Temperature (Ts) ......................... –65°C to +150°C
Supply Voltage
(VCC, VCC_TXQ, VCC_RXIN) ..................+3.0V to +3.6V
Ambient Temperature (TA) ....................–40°C to +85°C
(3)
Package Thermal Resistance
QFN (qJA)
Still-Air.......................................................50°C/W
QFN (yJB)
Junction-to-Board .....................................30°C/W
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Min
Typ
Max
Units
VCC
Power Supply
Condition
3
3.3
3.6
V
VCC_TXQ
Transmit Power Supply
3
3.3
3.6
V
VCC_RXIN
Receive Power Supply
ICC
Power Supply Current
3
3.3
3.6
V
100
150
mA
Min
Typ
Max
Units
No load, max. VCC
Receiver Input DC Electrical Characteristics
VCC_RXIN = 3.3V ±10%; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
RIN
Input Resistance
(RXIN to VREF)
45
50
55
Ω
RDIFF_IN
Input Resistance
(RXIN to /RXIN)
90
100
110
Ω
VIN
Input Voltage Swing
(RXIN, /RXIN)
See Figure 5a
AC-coupled
10
900
mV
VDIFF_IN
Differential Input Voltage Swing
|RXIN - /RXIN|
See Figure 5b
AC-coupled
20
1800
mV
VREF
Internal Reference Voltage
VCC_RXIN
-1.16
V
VCC_RXIN
-1.48
VCC_RXIN
-1.32
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. qJA and yJB
values are determined for a 4-layer board in still-air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
January 2006
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SY58621L
Receiver Output DC Electrical Characteristics
VCC = 3.3V ±10%, RL = 100Ω across the outputs; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
(RXQ, /RXQ)
RL = 50Ω to VCC
VCC
–0.020
VCC
-0.010
VCC
V
VOUT
Output Voltage Swing
(RXQ, /RXQ)
See Figure 5a
325
400
500
mV
VDIFF_OUT
Differential Output Voltage Swing
(RXQ, /RXQ)
See Figure 5b
650
800
1000
mV
ROUT
Single-Ended Output Impedance
45
50
55
Ω
RDIFF_OUT
Differential Output Impedance
90
100
110
Ω
VOFFSET
Differential Output Offset
+140
mV
RL = 50Ω to VCC, limiting mode
–140
Transmitter Input DC Electrical Characteristics
VCC = 3.3V ±10%; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Min
Typ
Max
Units
RIN
Input Resistance
(TXIN to TXVT)
45
50
55
Ω
RDIFF_IN
Differential Input Resistance
(TXIN to /TXIN)
90
100
110
Ω
VIH
Input HIGH Voltage
(TXIN, /TXIN)
1.2
VCC
V
VIL
Input LOW Voltage
(TXIN, /TXIN)
0
VIH -0.1
V
VIN
Input Voltage Swing
(TXIN, /TXIN)
See Figure 5a
0.1
VCC
V
VDIFF_IN
Differential Input Voltage Swing
|TXIN - /TXIN|
See Figure 5b
0.2
VT_IN
TXIN, /TXIN to VT
VTXVREF-AC
Output Reference Voltage
VREF_CTRL
VTXVCTRL
January 2006
Condition
V
1.28
V
VCC -1.4
VCC -1.3
VCC -1.3
V
Output Reference Voltage
VCC -1.4
VCC -1.3
VCC -1.3
V
Input Voltage
(TXVCTRL)
VREF_CTRL
VCC
V
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SY58621L
Transmitter Output DC Electrical Characteristics
VCC_TXQ = 3.3V ±10%, RL = 50Ω to VCC_TXQ – 2V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
VOH
Output HIGH Voltage
(TXQ, /TXQ)
VOL
Output LOW Voltage
(TXQ, /TXQ)
Condition
TXVCTRL = VREF_CTRL
Min
Typ
Max
Units
VCC_TXQ
- 1.145
VCC_TXQ
-1.020
VCC_TXQ
-0.895
V
VCC_TXQ
- 1.945
VCC_TXQ
- 1.820
VCC_TXQ
- 1.695
V
TXVCTRL = VCC_TXQ
VOUT
Output Voltage Swing
(TXQ, /TXQ)
TXVCTRL = VREF_CTRL
See Figure 5a
550
TXVCTRL = VCC_TXQ
See Figure 5a
VDIFF_OUT
Differential Output Voltage Swing
(TXQ, /TXQ)
TXVCTRL = VREF_CTRL
See Figure 5b
1100
TXVCTRL = VCC_TXQ
See Figure 5b
VCC_TXQ
- 1.100
V
800
mV
80
mV
1600
mV
160
mV
LVTTL/CMOS INPUT DC Control Electrical Characteristics(5)
VCC = 3.3V ±10%; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
VIL
/TXEN, /RXEN, LOOPBACK
VIH
/TXEN, /RXEN, LOOPBACK
IIL
/TXEN, /RXEN, LOOPBACK
IIL@VIN = 0.5V
IIH
/TXEN, /RXEN, LOOPBACK
IIH@VIN = VCC
Min
Typ
Max
Units
0.8
V
50
µA
300
µA
2
0
V
Note:
5. /TXEN, /RXEN, and LOOPBACK have an internal pull-down 25kΩ resistor.
January 2006
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SY58621L
LOS DC Electrical Characteristics
VCC = 3.3V ±10%; TA = –40°C to +85°C.
Symbol
Parameter
VLOSLVL
LOSLVL Voltage Range
VOH
Output HIGH Voltage
Source 100µA; VCC ≥ 3.3V
VOL
Output LOW Voltage
Sink 2mA
VSR
LOS Sensitivity Range
LOSAL
Low LOS Assert Level
LOSDL
HYSL
LOSAM
LOSDM
HYSM
LOSAH
LOSDH
HYSH
Low LOS De-assert Level
Low LOS Hysteresis
Medium LOS Assert Level
Medium LOS De-assert Level
Medium LOS Hysteresis
High LOS Assert Level
High LOS De-assert Level
High LOS Hysteresis
Condition
Min
Typ
VREF
Max
Units
VCC
V
2.4
V
7
0.5
V
35
mVPP
RLOSLVL = 10kΩ
7
2 -1 Data Pattern, Note 7
622Mbps
15
mV
3.2Gbps
10
mV
622Mbps
20
mV
3.2Gbps
15
mV
622Mbps
3
dB
3.2Gbps
5.5
dB
622Mbps
20
mV
3.2Gbps
15
mV
622Mbps
30
mV
3.2Gbps
25
mV
622Mbps
4
dB
3.2Gbps
5.5
dB
622Mbps
35
mV
3.2Gbps
30
mV
622Mbps
60
mV
3.2Gbps
55
mV
622Mbps
5
dB
3.2Gbps
5.5
dB
RLOSLVL = 10kΩ
7
2 -1 Data Pattern, Note 7
RLOSLVL = 10kΩ, limiting mode
7
2 -1 Data Pattern, Note 6 and 7
RLOSLVL = 5kΩ
7
2 -1 Data Pattern, Note 7
RLOSLVL = 5kΩ
7
2 -1 Data Pattern, Note 7
RLOSLVL = 5kΩ, limiting mode
7
2 -1 Data Pattern, Note 6 and 7
RLOSLVL = 1kΩ
7
2 -1 Data Pattern, Note 7
RLOSLVL = 1kΩ
7
2 -1 Data Pattern, Note 7
RLOSLVL = 1kΩ, limiting mode
7
2 -1 Data Pattern, Note 6 and 7
Notes:
Ê SD_AssertVoltage ˆ
˜˜ dB.
6. Hysteresis is defined as: 20Log10 ÁÁ
Ë SD_De - assertVoltage ¯
7. See the “Typical Operating Characteristics” section for more details on RLOSLVL and its associated LOS assert and de-assert amplitudes for a
7
7
2 -1 PRBS data pattern. See the “PRBS Discussion” section for more details on the 2 -1 PRBS data pattern.
January 2006
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SY58621L
AC Electrical Characteristics(8)
VCC = VCC_TXQ = VCC_RXIN = 3.3V ±10%, Receiver Load: RL = 100Ω across the outputs. Transmitter Load: RL = 50Ω to
VCC_TXQ – 2V; TA = –40°C to +85°C, unless otherwise stated.
Receiver and Transmitter
Symbol
Parameter
Condition
Min
Typ
tJITTER
Deterministic Jitter (DJ)
Note 9
Random Jitter (RJ)
Note 10
Crosstalk-Induced Jitter
Note 11
Symbol
Parameter
Condition
Min
fMAX
Maximum Operating Frequency
VRXIN ≥ 10mV (20mVPP)
3.2
BW
-3dB
VRXIN ≥ 10mV (20mVPP)
2.5
GHz
S21
Single-Ended Gain
Linear mode
32
dB
AV(DIFF)
Differential Voltage Gain
Linear mode
38
dB
tr, tf
Output Rise/Fall Time
(20% to 80%)
Limiting mode
60
LOS
Frequency
Range
LOS Operating Frequency
Range
Note 12
tOFF
LOS De-assert Time
tON
LOS Assert Time
0.7
Max
Units
Note 13
psPP
5
psRMS
1.2
psRMS
Max
Units
Receiver
Typ
Gbps
120
ps
3.2
Gbps
0.1
0.5
µs
0.2
0.5
µs
Typ
Max
Units
0.622
Transmitter
Symbol
Parameter
Condition
Min
fMAX
Maximum Operating Frequency
VTXIN ≥ 100mV (200mVPP)
3.2
BW
-3dB
VREF_CTRL ≤ TXCTRL ≤ VCC_TXQ
tr, tf
Output Rise/Fall Time
(20% to 80%)
VTXVCTRL = VREF_CTRL
Gbps
2
100
GHz
160
ps
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
23
9. Deterministic jitter is measured with both K28.5 and 2 -1 PRBS data-pattern, measured at <fMAX. VIN = 10mV (20mVpp) RX, 100mV (200mVpp)
23
TX. See the “PRBS Discussion” section for more details on the K28.5 and 2 – 1 PRBS data pattern.
10. Random jitter is measured with a K28.7 character pattern, measured at <fMAX. VIN = 10mV (20mVpp) RX, 100mV (200mVpp) TX. See the “PRBS
Discussion” section for more details on the K28.7 PRBS data pattern.
11. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at
the inputs.
7
12. LOS is guaranteed to be chatter-free at fMAX ≥622Mpbs or fMAX ≥311MHz with VRXIN ≥10mV (20mVPP) with a 2 -1 PRBS data pattern.
13. Contact factory for limits.
January 2006
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SY58621L
Detailed Description
Receiver
The receiver AC-coupled differential input distributes
data to 3.2Gbps with signals as small as 10mV
(20mVPP) or as large as 900mV (1.8VPP). The receiver
input features an internal 50Ω input termination
connected to an internal reference which optimizes
the inputs for AC-coupled signals. Input signals are
linearly amplified with 38dB of differential gain and the
output signal is limited to 400mV (800mVPP).
The receiver output buffer features 50Ω source
termination resistors and a current source that
provides 400mV (800mVPP) swing into 50Ω
termination. The output buffers terminates to standard
CML loads (100Ω across the output pair or
equivalent). See the “Output Stage Receiver” section
for more details.
Transmitter
The transmitter differential input includes Micrel’s
unique, patented 3-pin input termination architecture
that directly interfaces to any (AC- or DC-coupled)
differential signal as small as 100mV (200mVPP)
without any termination resistor network in the signal
path.
The transmitter output buffer terminates to standard
LVPECL loads (RL = 50_ to VCC_TXQ-2V). The output buffer
is a special variable swing LVPECL buffer controlled by
TXVCTRL. The output buffer features emitter follower
output that provides 80mV (160mVPP) to 800mV (1.6VPP)
swing into 50_ transmission lines. See the next section
and Figures 1a and 1b for more details on how to control
the variable output swing feature.
Figure 1a. Voltage Source Implementation
January 2006
Figure 1b. Alternative Implementation
Transmitter PECL Variable-Swing Output Buffer
∑ Connecting VREF_CTRL to TXVCTRL sets the
transmitter output buffer to maximum swing
∑ Setting TXVCTRL to VCC_TXQ, sets the transmitter
output buffer to minimum swing
∑ Control of the transmitter output swing buffers can
be obtained by using a variable resistor connected
between VREF_CTRL and VCC_TXQ with a wiper
connected to TXVCTRL as shown in Figure 1b
Receiver LOS
The SY58621L features a chatter-free Loss-of-Signal
(LOS) TTL compatible output with an internal 4.75kΩ
pull-up resistor. LOS circuitry monitors the input
receiver signal and asserts a signal when the input
signal falls below the threshold set by the
programmable LOS level set pin (LOSLVL). When the
amplitude of the receiver input signal falls below the
threshold, LOS is asserted HIGH with a response time
of ~0.2uS. LOS can be fed into /RXEN to maintain
output stability by disabling the output during a Lossof-Signal condition. Figure 2a and 2b shows the LOS
connection to /RXEN. When /RXEN is HIGH, the
output signal RXQ is held LOW and /RXQ is held
HIGH. Typically, 2dB of LOS hysteresis is adequate to
prevent the receiver output from chattering. LOS
operation is optimized for data rates ≥622Mbps with
an input receiver amplitude of at least 10mV
(20mVPP). Due to the long time constant in slower
data rates below 622Mbps, the SY58621L LOS
function does not guarantee chatter-free operation for
low amplitude signals.
LOSLVL sets the threshold of the LOS input amplitude
detection. Connecting an external resistor, RLOSLVL,
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between VCC and LOSLVL sets the input amplitude
LOS detection trip-point by setting up a voltage divider
between VCC and VREF (an internal voltage source set
at VCC-1.3V), since there is a 2.8kΩ internal resistor
connected between LOSLVL and VREF. The input
voltage range of LOSLVL ranges from VCC to VREF.
See the “Functional Block Diagram” section and
Figures 2a and 2b, to see how RLOSLVL sets up a
voltage divider between VCC and VREF. See the “LOS
Output DC Electrical Characteristics” table and
“Typical Operating Characteristics” section to see how
different RLOSLVL values affect LOS sensitivity.
connected to VCC with a wiper connected to
LOSLVL, as shown in Figure 2b
Figure 2a. Voltage Source Implementation
Figure 2b. Alternative Implementation
LOS Output
∑ Connecting the input /RXEN to the LOS output as
shown in Figures 2a and 2b, maintains receiver
output stability under a Loss-of-Signal condition
∑ Sensitivity of the LOS signal can be programmed
using the LOSLVL input by using a variable resistor
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∑ ≥ 2dB hysteresis is insured if RLOSLVL ≤ 10kΩ
∑ LOS is guaranteed chatter-free at f ≥ 622Mbps
(311MHz)
Hysteresis
The SY58621L provides a minimum of 2dB of LOS
hysteresis, see the Figure 3 for more details.
Figure 3. LOS Hysteresis Assert/De-assert
Ê
SD_AssertVoltage ˆ
˜ dB.
SD_De
- assertVoltage ˜¯
Ë
Hysteresis is defined as: 20Log10 ÁÁ
Loopback
To support diagnostic system testing, the SY58621L
features a loopback test mode, activated by setting
LOOPBACK to logic HIGH. Loopback mode enables
an internal loopback path from the transmitter input to
the receiver output and supports the full 3.2Gbps data
rate throughput.
Crosstalk
The SY58621L features a patent-pending isolation
between the receiver and transmitter channels. The
following guide lines can be used to minimize on
layout induced crosstalk:
1. Ground Stripping
Ground stripping is an effective method to reduce
crosstalk. Ground stripping involves running a
ground trace between the receiver and transmitter
channels.
2. Vertical and Horizontal Traces
Another way to reduce crosstalk is to route the
receiver and transmitter channels on separate
layers with an embedded ground or power supply
layer between the layers. When routing the traces
on different layers, run the receiver traces
horizontal to the transmitter traces and route the
transmitter traces vertical to the receiver traces.
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PRBS Discussion
LOS Testing
7
The LOS function is tested with a 2 -1 PRBS (Pseudo
Random Bit Stream) data-pattern. A PRBS data7
pattern of 2 -1 is used because it is a good
approximation to an 8b10b-encoded NRZ data
stream. 8b10b encodes 8 bits of data and replaces it
with 10 bits of symbol. The extra bits are added to
improve transition density and the BER (Bit Error
Rate) of the system.
Power Supply Filtering
Although the SY58621L is fully differential, it is
recommended that the power supplies are filtered as
shown in Figure 4.
Deterministic Jitter Testing and the K28.5 Pattern
23
The K28.5 (11000001010011111010) and 2 -1 PRBS
data-patterns are used to characterize DJ because
both data patterns have lower spectral frequency
content which provides a best approximation to
scrambled NRZ data streams.
Random Jitter Testing and the K28.7 Pattern
The K28.7 (1111100000…) data pattern is used to
measure RJ since the pattern is free of DJ. In
addition, because the K28.7 data-pattern can be used
TH
st
to compare the TN (N period) to the T0 (1 period),
low frequency jitter components can be accumulated.
Figure 4. Power Supply Filtering Scheme
Item
Description
C1, C2, C3, C23
0.1µF Capacitor
C4, C5, C6, C22
0.01µF Capacitor
L1, L2, L3
1.2µH Ferrite Bead Inductor
Table 1. Bill of Materials
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Typical Operating Characteristics
VCC = VCC_TXQ = VCC_RXIN = 3.3V ±10%, Receiver: RL = 100Ω across the outputs. Transmitter: RL = 50Ω to VCC_TXQ
–2V; TA = 25°C, unless otherwise stated.
RLOSLVL (kΩ)
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RLOSLVL (kΩ)
15
RLOSLVL (kΩ)
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Single-Ended and Differential Swings
Figure 5a. Single-Ended Voltage Swing
Figure 5b. Differential Voltage Swing
Input Stage
Figure 6a. TX Simplified Differential Input Stage
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Figure 6b. RX Simplified Differential Input Stage
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Output Stage
Receiver
Figure 7a. Receiver CML
DC-Coupled Output
January 2006
Figure 7b. Receiver CML
AC-Coupled Output
17
Figure 7c. Receiver CML
DC-Coupled Output (50Ω to VCC)
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Transmitter
The transmitters output is a variable swing LVPECL
open emitter driver. LVPECL has very low output (open
emitter) impedance, and small signal swing which result
in low EMI.
LVPECL is ideal for driving 50Ω and 100Ω-controlled
impedance transmission lines. There are several
techniques for terminating the LVPECL output: Parallel
Termination-Thevenin Equivalent, Parallel Termination
(3-Ressitor), and AC-Coupled Termination. Unused
output pairs may be left floating. However, the unused
half of a single-ended output must be terminated, or
balanced.
Figure 8a. Parallel Thevenin-Equivalent Termination
Figure 8b. Parallel Termination – 3-Resistors
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Interface Applications
Figure 9a. LVPECL Interface
(TX DC-Coupled/RX AC-Coupled)
Figure 9b. LVPECL Interface
(TX AC-Coupled/RX AC-Coupled)
Figure 9d. CML Interface
(TX AC-Coupled/RX AC-Coupled)
Figure 9e. LVDS Interface
(TX DC-Coupled/RX AC-Coupled)
Figure 9c. CML Interface
(TX DC-Coupled/RX AC-Coupled)
Related Product and Support Documentation
Part Number
Function
Data Sheet Link
SY58620L
Precision 4.25Gbps CML Transceiver with
Integrated Loopback
www.micrel.com/product-info/products/sy58620l.shtml
HBW Solutions
New Products and Applications
www.micrel.com/product-info/products/solutions.shtml
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SY58621L
Package Information
24-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
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and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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