5-Channel ESD Protection Array PACDN009 Features Product Description • • The PACDN009 is a diode array designed to provide 5 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes which steers an ESD current pulse to either the positive (VP) or negative (VN) supply. The PACDN009 protects against ESD pulses up to ±15kV Human Body Model (100 pF capacitor discharging through a 1.5KΩ resistor), and ±8kV contact discharge, per International Standard IEC 61000-4-2. • • • • • Five channels of ESD protection ±8kV contact, ±15kV air ESD protection per channel (IEC 61000-4-2 standard) ±15kV of ESD protection per channel (HBM) Low loading capacitance (3pF typical) Low leakage current is ideal for battery-powered devices Available in miniature 8-lead MSOP package RoHS compliant (lead-free) finishing Applications • • • • • • • Consumer electronic products Cellular phones PDAs Notebook computers Desktop PCs Digital cameras and camcorders VGA (video) port protection for desktop and portable PCs ©2010 SCILLC. All rights reserved. May 2010 Rev. 3 This device is particularly well-suited for portable electronics (e.g., cellular phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. It is also suitable for protecting video output lines and I/O ports in computers and peripherals and is ideal for a wide range of consumer electronics products. The PACDN009 is supplied in an 8-lead MSOP package and is available with RoHS compliant lead-free finishing. Publication Order Number: PACDN009/D PACDN009 Typical Application Circuit 3 Electrical Schematic PACDN009 7 0.22μF* 14 56 8 Expansion Connector I/O Port Buffers Handheld/PDA ESD Protection * Capacitor should be placed as close as possible to Pin7 PACKAGE / PINOUT DIAGRAMS TOP VIEW 1 VN CH 2 3 2 4 8 009R CH 1 N.C. 7 6 5 CH 5 VP CH 4 CH 3 PACDN009 8-lead MSOP Package Note: This drawing is not to scale. Rev. 3 | Page 2 of 10 | www.onsemi.com PACDN009 PIN DESCRIPTIONS PIN NAME TYPE DESCRIPTION 1 CH 1 I/O 2 N.C. - 3 VN GND 4 CH 2 I/O ESD Channel 5 CH 3 I/O ESD Channel 6 CH 4 I/O ESD Channel 7 VP Supply 8 CH 5 I/O ESD Channel No connect Negative voltage supply rail or ground reference rail Positive voltage supply rail ESD Channel Ordering Information PART NUMBERING INFORMATION Lead-free Finish Leads Package Ordering Part Number1 Part Marking 8 MSOP PACDN009MR 009R Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Rev. 3 | Page 3 of 10 | www.onsemi.com PACDN009 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS Supply Voltage (VP - VN) 6.0 V Diode Forward DC Current (Note 1) 20 mA Operating Temperature Range -40 to +85 °C Storage Temperature Range -65 to +150 °C (VN - 0.5) to (VP + 0.5) V 200 mW DC Voltage at any channel input Package Power Rating Note 1: Only one diode conducting at a time. STANDARD OPERATING CONDITIONS PARAMETER Operating Temperature Range Operating Supply Voltage (VP - VN) RATING UNITS -40 to +85 °C 0 to 5.5 V ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1) SYMBOL PARAMETER CONDITIONS IP Supply Current (VP-VN)=5.5V VF Diode Forward Voltage IF = 20mA VESD MIN TYP 0.65 MAX UNITS 10 μA 0.95 V ESD Protection Peak Discharge Voltage at any channel Note 2 input, in system a) Human Body Model, MIL-STD-883, Notes 3 ±15 kV ±8 ±15 kV Method 3015 b) Contact Discharge per IEC 61000-4-2 Note 4 c) Air Discharge per IEC 61000-4-2 VCL Channel Clamp Voltage Note 4 kV @15kV ESD HBM Positive Transients Negative Transients ILEAK CIN Channel Leakage Current Channel Input Capacitance @ 1 MHz, VP=5V, VN=0V, VP + 13.0 V VN - 13.0 V ±0.1 ±1.0 μA 3 5 pF VIN=2.5V; Note 2 applies Note 1: All parameters specified at TA=25°C unless otherwise noted. VP = 5V, VN = 0V unless noted. Note 2: From I/O pins to VP or VN only. VP bypassed to VN with a 0.22μF ceramic capacitor (see Application Information for more details). Note 3: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 5.0V, VN grounded. Note 4: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330W, VP = 5.0V, VN grounded. Rev. 3 | Page 4 of 10 | www.onsemi.com PACDN009 Performance Information Input Capacitance vs. Input Voltage Rev. 3 | Page 5 of 10 | www.onsemi.com PACDN009 Application Information Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is: VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt+ L2 x d(IESD ) / dt where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by ΔIESD/Δt, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to fast transient current spikes. In the VCL equation above, the VSUPPLY term, in reality, is given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply DC output voltage and effective output impedance of the power supply respectively. As an example, a ROUT of 1 ohm would result in a 10V increment in VCL for a peak IESD of 10A. If the inductances and resistance described above are close to zero, the rail-clamp ESD protection diodes will do a good job of protection. However, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high frequency ESD energy. So for any brand of rail-clamp ESD protection diodes, a bypass capacitor should be connected between the VP pin of the diodes and the ground plane (VN pin of the diodes) as shown in the Application Circuit diagram below. A value of 0.22µF is adequate for IEC-61000-4-2 level 4 contact discharge protection (+8kV). Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Additional Information See also California Micro Devices Application Notes AP209, “Design Considerations for ESD Protection” and AP219, "ESD Protection for USB 2.0 Systems" Rev. 3 | Page 6 of 10 | www.onsemi.com PACDN009 Figure 1. Application of Positive ESD Pulse between Input Channel and Ground Rev. 3 | Page 7 of 10 | www.onsemi.com PACDN009 Figure 3. PCB Layout Recomendation Rev. 3 | Page 8 of 10 | www.onsemi.com PACDN009 Mechanical Details MSOP-8 Mechanical Specifications, 8 pin The PACDN009 is supplied in a 8-pin MSOP package. Dimensions are presented below. For complete information on the MSOP-8, see the California Micro Devices MSOP Package Information document. PACKAGE DIMENSIONS Package MSOP Pins 8 Dimensions Millimeters Inches Min Max Min Max A 0.75 0.95 0.030 0.037 A1 0.05 0.15 0.002 0.006 B 0.28 0.38 0.011 0.015 C 0.13 0.23 0.005 0.009 D 2.90 3.10 0.114 0.122 E 2.90 3.10 0.114 0.122 e 0.65 BSC H 0.026 BSC 4.90 BSC L 0.40 # per tape and 0.193 BSC 0.70 0.016 0.028 4000 pieces reel Controlling dimension: millimeters Dimensions for MSOP-8 Package Rev. 3 | Page 9 of 10 | www.onsemi.com PACDN009 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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