STB70NF3LL STP70NF3LL N-CHANNEL 30V - 0.0075 Ω - 70A D²PAK/TO-220 LOW GATE CHARGE STripFET™ II POWER MOSFET TYPE STB70NF3LL STP70NF3LL ■ ■ ■ ■ VDSS RDS(on) ID 30 V 30 V < 0.0095 Ω < 0.0095 Ω 70 A 70 A TYPICAL RDS(on) = 0.0075 Ω @ 10 V OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5 V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED DESCRIPTION This application specific Power MOSFET is the third genaration of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. 3 1 D2PAK TO-263 (Suffix “T4”) 3 1 2 TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS ■ SWITCHING APPLICATIONS Ordering Information SALES TYPE STB70NF3LLT4 STP70NF3LL MARKING B70NF3LL@ P70NF3LL@ PACKAGE D2PAK TO-220 PACKAGING TAPE & REEL TUBE ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID(•) ID IDM(••) Ptot dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Operating Junction Temperature (•) Current limited by the package (••) Pulse width limited by safe operating area. Value 30 30 ± 16 70 50 280 100 0.67 5.5 500 Unit V V V A A A W W/°C V/ns mJ -55 to 175 °C (1) ISD ≤70A, di/dt ≤350A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX (2) Starting T j = 25 oC, ID = 35A, VDD = 25V October 2003 NEW DATASHEET ACCORDING TO PCN DSG/CT/2C13 MARKING: P70NF3LL@ B70NF3LL@ 1/10 STB70NF3LL STP70NF3LL THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 1.5 62.5 300 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16 V V(BR)DSS Min. Typ. Max. 30 Unit V 1 10 µA µA ±100 nA Max. Unit ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 4.5 V ID = 35 A ID = 18 A Min. Typ. 1 V 0.0075 0.010 0.0095 0.012 Ω Ω Typ. Max. Unit DYNAMIC Symbol 2/10 Parameter Test Conditions gfs (*) Forward Transconductance VDS = 15 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V f = 1 MHz VGS = 0 ID = 35 A Min. 25 S 1650 540 130 pF pF pF STB70NF3LL STP70NF3LL ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time ID = 35 A VDD = 15 V RG = 4.7 Ω VGS = 4.5 V (Resistive Load, Figure 3) 23 156 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD= 15V ID= 70A VGS= 4.5V 24 8.5 12 33 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol td(off) tf Parameter Test Conditions Min. ID = 35 A VDD = 15 V RG = 4.7Ω, VGS = 4.5 V (Resistive Load, Figure 3) Turn-off Delay Time Fall Time 27 28 ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 70 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100A/µs ISD = 70 A VDD = 25 V Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM (*)Pulsed: Pulse duration = 300 µs, duty cycle (•)Pulse width limited by safe operating area. Safe Operating Area Test Conditions Min. Typ. VGS = 0 40 50 2.5 Max. Unit 70 280 A A 1.3 V ns nC A 1.5 %. Thermal Impedance 3/10 STB70NF3LL STP70NF3LL Output Characteristics Transfer Characteristics Source-drain Diode Forward Characteristics Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/10 STB70NF3LL STP70NF3LL Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Normalized Breakdown Voltage vs Temperature. . . 5/10 STB70NF3LL STP70NF3LL Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/10 STB70NF3LL STP70NF3LL D2PAK MECHANICAL DATA DIM. mm. MIN. TYP. inch. MAX. MIN. A 4.4 4.6 0.173 TYP. 0.181 TYP. A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.028 0.037 B2 1.14 1.7 0.045 0.067 C 0.45 0.6 0.018 0.024 C2 1.21 1.36 0.048 0.054 D 8.95 9.35 0.352 D1 E 8 10 E1 0.368 0.315 10.4 0.394 8.5 0.409 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.591 0.624 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.069 M 2.4 3.2 0.094 R V2 0.4 0° 0.126 0.015 8° 0° 8° 7/10 STB70NF3LL STP70NF3LL TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 L2 16.4 L4 0.645 13.0 0.551 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 8/10 L4 P011C STB70NF3LL STP70NF3LL D2PAK FOOTPRINT TUBE SHIPMENT (no suffix)* TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. mm MIN. A inch MAX. MIN. 330 B 1.5 C 12.8 D 20.2 G 24.4 N 100 T MAX. 12.992 0.059 13.2 0.504 26.4 0.960 0.520 0.795 1.039 3.937 30.4 1.197 BASE QTY BULK QTY 1000 1000 TAPE MECHANICAL DATA DIM. mm MIN. inch MAX. MIN. MAX. 0.421 A0 10.5 10.7 0.413 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0075 0.082 R 50 1.574 T 0.25 0.35 .0.0098 0.0137 W 23.7 24.3 0.933 0.956 * on sales type 9/10 STB70NF3LL STP70NF3LL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 10/10