M TC1142 Inductorless -2x Boost/Buck Regulator Features Package Type • • • • • • Input Range 2.5V to 5.5V Regulated Output Options from -3.0 to -5.0V Output Current 20mA (max) 200kHz Internal Oscillator Frequency External Synchronizing Clock Input Logic Level Shutdown - 1µA (max) Supply Current • Available in 8-Pin MSOP Package 8-Pin MSOP VOUT 1 8 CCLK 7 VIN 3 6 C1+ C1– 4 5 GND C2– 2 C2+ TC1142 Applications General Description • Cellular Phones • Battery Powered/Portable Equipment The TC1142 generates a regulated negative voltage from -3V to -5V at 20mA from an input of 2.5V to 5.5V, using only three external capacitors. Other boost/buck switching regulators must use an inductor, which is larger and radiates EMI. An internal voltage comparator inhibits the charge pump when VOUT is more negative than the regulated value (per the ordering option). The values of flying capacitors C1 and C2 are chosen to be less than COUT in order to reduce the ripple generated from regulating VOUT in this manner. The TC1142 also can be used as a -1x buck regulator by omitting C2, and connecting the C2 pin to VOUT. Device Selection Table Part Number Output Voltage (V)* TC1142-3.0EUA 3.0 8-Pin MSOP -40°C to +85°C TC1142-4.0EUA 4.0 8-Pin MSOP -40°C to +85°C TC1142-5.0EUA 5.0 8-Pin MSOP -40°C to +85°C Package Operating Temp. Range *Other output voltages are available (-3.5V and -4.5V). Please contact Microchip Technology Inc. for details. The part goes into shutdown when the CCLK input is driven low. When in shutdown mode, the part draws a maximum of 1µA. When CCLK is pulled high, the part runs from the internal 200kHz oscillator. The device may be run with an external clock, provided the frequency is greater than 3kHz and less than 500kHz. The TC1142 comes in a space-saving MSOP package. Functional Block Diagram –2x Boost/Buck + – – 5.5V to 3V ON OFF ON OFF VIN CCLK OSC OVERRIDE –1x Buck + 5.5V to 2.5V 0.47µF C1 0.47µF C2 TC1142-50 CCLK 4.7µF COUT OSC OVERRIDE 0.47µF C1 VOUT = –3.0V VOUT TC1142-30 4.7µF COUT C2– GND 2002 Microchip Technology Inc. VIN VOUT = -5.0V VOUT GND DS21360B-page 1 TC1142 1.0 ELECTRICAL CHARACTERISTICS *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Supply Voltage (VIN) with COUT Connected ..........6.5V CCLK Voltage................................-0.3V to (V+ + 0.3V) Power Dissipation.............................................320mW Operating Temperature Range 8-Pin MSOP .................................-40°C to +85°C Storage Temperature Range ..............-65°C to +160°C TC1142 ELECTRICAL SPECIFICATIONS Electrical Characteristics: RL = ∞, VIN = 3.2V, Mode = -2x, C1 = C2 = 0.47µF (Note 1), CCLK = VIH, COUT = 4.7µF, for VR = 3V, VIN = 3.5V, TA = TMIN to TMAX, unless otherwise noted. Symbol Parameter Min Typ Max Units VIN Supply Voltage 2.5 — 5.5 V VOUT Output Voltage -(VR + 0.2) -VR -(VR – 0.2) V VP-P Output Ripple — 100 — mV ISUPPLY Supply Current ISUPPLY1 — 200 400 µA — 0.1 1 µA ROUTCL Closed-Loop Output Resistance — 2 6 Ω ROUT Open-Loop Output Resistance — 30 — Ω fOSC Internal Oscillator Frequency 150 200 275 kHz fCCLK External Clock Frequency, Typical 3 — 500 kHz PEFF Power Efficiency 70 76 — % VIH CCLK Input High Threshold 2.2 — — V VIL CCLK Input Low Threshold — — 1.0 V Note 1: 2: 3: 4: Test Conditions IL = 0mA (Note 2) IL = 10mA CCLK = 0V (Note 3) (Note 4) IL = 10mA, VR = 5V; (See Equation 3-5) Assume C1 and C2 have an ESR of 1Ω. VR is the voltage output specified in the ordering option. Measured in -1x Mode. For VR = 3V, VIN = 2.5V. CCLK is driven with an external clock. Minimum frequency = 1/2t0 at 50% duty cycle, where t0 is the counter timeout period. DS21360B-page 2 2002 Microchip Technology Inc. TC1142 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin No. (8-Pin MSOP) Symbol 1 VOUT Regulated negative output voltage. Description 2 C2– Negative terminal of flying capacitor C2. 3 C2+ Positive terminal of flying capacitor C2. 4 C1– Negative terminal of flying capacitor C1. 5 GND Power supply ground. 6 C1+ Positive terminal of flying capacitor C1. 7 VIN 8 CCLK 2002 Microchip Technology Inc. Power supply positive voltage input (2.5V to 5.5V). Clock control input: If low, the TC1142 is in Shutdown mode (1µA, max). If high, the TC1142 runs off the internal oscillator (200kHz, typ.). CCLK can be overridden by an external oscillator from 3kHz to 500kHz. DS21360B-page 3 TC1142 3.0 DETAILED DESCRIPTION The CCLK pin of the TC1142 has three functions: It can select the internal 200kHz oscillator (when held HIGH), put the TC1142 into shutdown (when held LOW), or provide an external clock input. To achieve this functionality, an internal counter is reset by any positive transition at the CCLK pin, but will time out in typically 160 µsec (i.e., a frequency higher than about 3kHz). If the counter times out following the last positive transition, then the internal clock will be gated through to the charge pump if CCLK is HIGH, or the device will enter shutdown mode if it is LOW. To enter shutdown, CCLK must be LOW and the counter must have timed out. These timing diagrams are shown in Figure 3-4. The TC1142 inductorless -2x boost/buck regulator is an inverting charge pump that uses a pulse-frequency modulation (PFM) control scheme to produce a regulated negative output voltage, -VR, between -3V and -5V (depending on the output voltage option) at 20mA maximum load. Output voltage regulation is achieved by gating ON the clock to the charge pump for a single half-clock period whenever the output is more positive than VR, and gating it OFF when the output is more negative than -VR. The resulting PFM of the clock applied to the charge pump has a high frequency spectral content consisting only of clock harmonics. When using an external clock, the transient noise is then synchronized to the clock and is easier to filter in sensitive applications. A functional circuit diagram of the TC1142 is shown in Figure 3-1. The output voltage VOUT is compared to an on-chip reference voltage, and the comparator output is used to gate the charge pump clock. The charge pump is a negative voltage doubler and has two phases of operation which are further illustrated in Figure 3-2 and Figure 3-3. In phase 1, shown in Figure 3-2, the flying capacitor C1 charges the flying capacitor C2 while the device load is totally serviced by the charge stored on the reservoir capacitor COUT. In phase 2, shown in Figure 3-3, the capacitor C1 is recharged to VIN while the capacitor C2 transfers its charge to the reservoir capacitor COUT. The TC1142 also can be used as a -1x boost/buck regulator by omitting the C2 capacitor and connecting the C2– pin to VOUT. The PFM control scheme minimizes supply current at small loads and permits the use of low value flying capacitors, which saves on printed circuit board space and cost. Due to the TC1142’s doubling and inverting charge pump mechanism, the output voltage is limited to -2VIN. To produce a -5V regulated output, for example, a minimum input voltage of 2.5V is required at VIN. FIGURE 3-1: In normal operation, the TC1142 charge pump stays in phase 2 and only switches to phase 1 as required to maintain output voltage regulation. FUNCTIONAL CIRCUIT DIAGRAM C1+ VIN C1– VIN C2+ VOUT C2– + Shutdown COUT + Clock Circuit – 1.2V + OSC Override DS21360B-page 4 2002 Microchip Technology Inc. TC1142 FIGURE 3-2: TC1142 PHASE 1 (a) C1+ VIN C1– C2+ VIN VOUT C2– COUT + (b) VIN C2+ C1+ VOUT + COUT C1– C2– C1+ (a) Switch positions during phase 1. (b) The equivalent circuit of the charging phase of operation. FIGURE 3-3: TC1142 PHASE 2 (a) C1+ VIN C1– C2+ VIN VOUT C2– + COUT (b) VIN C1+ C2– C2+ C1– VOUT + COUT (a) Switch positions during phase 2. (b) The equivalent circuit of the discharging phase of operation. 2002 Microchip Technology Inc. DS21360B-page 5 TC1142 3.1 Output Voltage and Ripple For values of VIN higher than |VR/2| by several hundred mV, the effect on ripple of the ESR of COUT can be neglected compared to the “overdrive” effect of VIN. For a -2x boost: | V2 |. In this case, the output voltage is given by: Here, it can be seen that VRIPPLE increases with increasing VIN, but can be minimized by choosing small C1 and C2 values and a large COUT value. EQUATION 3-1: 3.2 a.) For unregulated operation when VIN ≤ R VOUT = -|2VIN | + IOROUT 1 f where ROUT = ( 1 1 + C1 C2 ) + RSC2 (C2 + COUT) Here, f is the clock frequency and RS is the total ON resistance of the switches connecting C2 to GND and VOUT in phase 2 of the charge pump operating cycle with the equivalent series resistance (ESR) of C2. The output ripple voltage is given by: EQUATION 3-2: VRIPPLE = IORRIPPLE where RRIPPLE = 1 + 1 + ESR C2 2f(C2 + COUT) 2fCOUT (C2 + COUT) Here, ESR is the equivalent series resistance of COUT. b.) For regulated operation when VIN > | V2 |. Capacitor Selection To maintain low output impedance and ripple, it is recommended that capacitors with low equivalent series resistance (ESR) be used. Additionally, larger values of the output capacitor and smaller values of the flying capacitors will reduce output ripple. For a capacitor value of 4.7µF for COUT, and values of 0.47µF for C1 and C2, the typical output impedance of the TC1142 in regulation is 0.5Ω. For the capacitor ESR not to have a noticeable effect on output impedance, it should not be larger than 1/2fCOUT. This also makes its effect on ripple voltage negligible. For VIN = 3.2V and VR = -5V, the output ripple voltage is less than 70 mVPP. Table 3-1 summarizes output ripple versus capacitor size for an input voltage of 3.2V and a regulated output voltage of -5V. Surface mount ceramic capacitors are preferred for their small size, low cost and low ESR. Low ESR tantalum capacitors also are acceptable. See Table 3-2 for a list of suggested capacitor suppliers. R In this case, the TC1142 is held in phase 2 until the output voltage drops below VR. When this occurs, the TC1142 reverts to phase 1 for a half period of the clock, during which C2 is charged from C1. At the end of this half-period, C2 is reconnected to COUT to boost the output voltage. During the phase 1 time period, the output voltage will drop below VR before it is boosted back, so the minimum output voltage is approximated by: TABLE 3-1: VOLTAGE RIPPLE VS. C1/C2 FLYING CAPACITORS AND OUTPUT CAPACITOR COUT ESR = 0.1Ω, IOUT = 20mA C1, C2 (µF) COUT (µF) VIN (V) VOUT (V) VRIPPLE (mV) 0.1 4.7 3.2 -5 14.6 0.22 4.7 3.2 -5 31.4 0.33 4.7 3.2 -5 46.1 0.47 4.7 3.2 -5 63.9 0.68 4.7 3.2 -5 88.7 1.0 4.7 3.2 -5 123.2 0.1 10 3.2 -5 7.0 0.22 10 3.2 -5 15.1 0.33 10 3.2 -5 22.4 The output ripple voltage is given approximately by: 0.47 10 3.2 -5 31.5 EQUATION 3-4: 0.68 10 3.2 -5 44.7 1.0 10 3.2 -5 63.8 EQUATION 3-3: VOUTMIN = -|VR | + IOROUT where ROUT = VRIPPLE = 1 ESR C2 + 2fCOUT (C2 + COUT) (2VIN – |VR | + ESR IOC2 where N = DS21360B-page 6 (C11 + C21 )) N ( 1 1 + C1 C2 ) (C2 + COUT) 2002 Microchip Technology Inc. TC1142 TABLE 3-2: LOW ESR SURFACE-MOUNT CAPACITOR MANUFACTURERS Manufacturer AVX Corp. Type Phone TPS series surface-mount tantalum 803-448-9411 X7R type surface-mount ceramic Matsuo 267 series surface-mount tantalum 593D, 594D, 595D series surface-mount tantalum 714-969-2491 3. 4. 207-324-4140 Murata Ceramic chip capacitors 800-831-9172 Taiyo Yuden Ceramic chip capacitors 800-348-2496 Tokin Ceramic chip capacitors 408-432-8020 3.3 1. 2. X7R type surface-mount ceramic Sprague For example, a 3.2 Volt VIN, and a -5 Volt VR will have an efficiency of approximately 78%. For loads less than 20% of the maximum available output current, the power efficiency will be substantially reduced. Other factors that affect the actual efficiency include: Power Efficiency Assuming the output is loaded with at least 20% of the maximum available output current, the power efficiency of the TC1142 can be estimated using the following equation: 3.4 FIGURE 3-4: 1. 2. 3. 3.5 VOUT Power efficiency is improved from VR/2VIN to VR/VIN Only one flying capacitor needed The output ripple becomes proportional to VIN – VR rather than 2 VIN – VR. Layout Considerations Proper layout is important to obtain optimal performance. Mount capacitors as close to their connecting device pins as possible to minimize stray inductance and capacitance. It is recommended that a large ground plane be used to reduce noise leakage into other circuitry. TIMING DIAGRAM t0 CCLK Choice of -2x or -1x Connections If required output voltage can be achieved using a -1x configuration then this is preferred for the following reasons: EQUATION 3-5: η = |VR | 2(VIN ) Losses from power consumed by the internal oscillator (if used). I2R losses due to the on-resistance of the MOSFET charge pump switches. Charge pump capacitor losses due to ESR. Losses that occur during charge transfer (from the flying capacitors to the output capacitor) when a voltage difference exists between these capacitors. t0 VIH VIL GND –VR Internal Oscillator Shutdown Shutdown External Clock t0 = counter timeout (~160 µsec) 2002 Microchip Technology Inc. DS21360B-page 7 TC1142 4.0 PACKAGING INFORMATION 4.1 Package Marking Information Package marking data not available at this time. 4.2 Taping Form Component Taping Orientation for 8-Pin MSOP Devices User Direction of Feed PIN 1 P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 8-Pin MSOP 4.3 Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 12 mm 8 mm 2500 13 in Package Dimensions 8-Pin MSOP PIN 1 .122 (3.10) .114 (2.90) .197 (5.00) .189 (4.80) .026 (0.65) TYP. .122 (3.10) .114 (2.90) .043 (1.10) MAX. .016 (0.40) .010 (0.25) .006 (0.15) .002 (0.05) .008 (0.20) .005 (0.13) 6° MAX. .028 (0.70) .016 (0.40) Dimensions: inches (mm) DS21360B-page 8 2002 Microchip Technology Inc. TC1142 Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. DS21360B-page9 TC1142 NOTES: DS21360B-page10 2002 Microchip Technology Inc. TC1142 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 03/01/02 ' #' DS21360B-page 12 2002 Microchip Technology Inc.