FUJITSU MB39A115PFT

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27242-1E
ASSP For Power Supply Applications
5 ch DC/DC Converter IC with
Synchronous Rectification
MB39A115
■ DESCRIPTION
The MB39A115 is a 5-channel DC/DC converter IC using pulse width modulation (PWM) , and the MB39A115 is
suitable for up conversion, down conversion, and up/down converstion. The MB39A115 is built in 5 channels into
TSSOP-38P/BCC-40P package and operates at 2 MHz maximum and, this IC can control and soft-start at each
channel. The MB39A115 is suitable for power supply of high performance potable instruments such as a digital
still camera (DSC).
■ FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Supports for down-conversion with synchronous rectification (ch.1)
Supports for down-conversion and up/down Zeta conversion (ch.2 to ch.4)
Supports for up-conversion and up/down Sepic conversion (ch.5)
Low voltage start-up (ch.5)
: 1.7 V
Power supply voltage range : 2.5 V to 11 V
Reference voltage
: 2.0 V ± 1%
Error amplifier threshold voltage : 1.0 V ± 1% (ch.1) , 1.23 V ± 1% (ch.2 to ch.5)
Oscillation frequency range
: 200 kHz to 2.0 MHz
Standby current
: 0 µA (Typ)
Built-in soft-start circuit independent of loads
Built-in totem-pole type output for MOS FET
Short-circuit detection capability by external signal (−INS terminal)
Copyright©2006 FUJITSU LIMITED All rights reserved
MB39A115
■ PIN ASSIGNMENTS
TOP VIEW
CS2
1
38
CS1
−INE2
2
37
−INE1
FB2
3
36
FB1
DTC2
4
35
VCCO
VCC
5
34
OUT1-1
CTL
6
33
OUT1-2
CTL3
7
32
OUT2
CTL4
8
31
OUT3
CTL5
9
30
OUT4
−INS
10
29
OUT5
VREF
11
28
GNDO
RT
12
27
CS5
CT
13
26
−INE5
GND
14
25
FB5
CSCP
15
24
DTC5
DTC3
16
23
DTC4
FB3
17
22
FB4
−INE3
18
21
−INE4
CS3
19
20
CS4
(FPT-38P-M03)
(Continued)
2
MB39A115
(Continued)
DTC2
FB2
−INE2
CS2
NC
CS1
−INE1
FB1
VCCO
TOP VIEW (Penetration diagram from surface)
40
39
38
37
36
35
34
33
32
3
29
OUT2
CTL4
4
28
OUT3
CTL5
5
27
OUT4
−INS
6
26
OUT5
VREF
7
25
GNDO
RT
8
24
CS5
CT
9
23
−INE5
GND
10
22
FB5
21
DTC5
12
13
CSCP
DTC3
FB3
14
−INE3
11
15
16
17
18
19
20
DTC4
CTL3
FB4
OUT1-2
−INE4
30
CS4
2
CTL
NC
OUT1-1
1
CS3
31
VCC
(LCC-40P-M07)
3
MB39A115
■ PIN DISCRIPTIONS
Block
name
Pin No.
Pin name
I/O
33
FB1
O
Error amplifier output terminal.
37
34
−INE1
I
Error amplifier inverted input terminal.
38
35
CS1
⎯
Soft-start setting capacitor connection terminal.
34
31
OUT1-1
O
P-ch drive output terminal.
(External main side FET gate driving)
33
30
OUT1-2
O
N-ch drive output terminal.
(External synchronous rectification side FET gate driving) .
4
40
DTC2
I
Dead time control terminal.
3
39
FB2
O
Error amplifier output terminal.
2
38
−INE2
I
Error amplifier inverted input terminal.
1
37
CS2
⎯
Soft-start setting capacitor connection terminal.
32
29
OUT2
O
P-ch drive output terminal.
16
12
DTC3
I
Dead time control terminal.
17
13
FB3
O
Error amplifier output terminal.
18
14
−INE3
I
Error amplifier inverted input terminal.
19
15
CS3
⎯
Soft-start setting capacitor connection terminal.
31
28
OUT3
O
P-ch drive output terminal.
23
20
DTC4
I
Dead time control terminal.
22
19
FB4
O
Error amplifier output terminal.
21
18
−INE4
I
Error amplifier inverted input terminal.
20
17
CS4
⎯
Soft-start setting capacitor connection terminal.
30
27
OUT4
O
P-ch drive output terminal.
24
21
DTC5
I
Dead time control terminal.
25
22
FB5
O
Error amplifier output terminal.
26
23
−INE5
I
Error amplifier inverted input terminal.
27
24
CS5
⎯
Soft-start setting capacitor connection terminal.
29
26
OUT5
O
N-ch drive output terminal.
13
9
CT
⎯
Triangular wave frequency setting capacitor connection terminal.
12
8
RT
⎯
Triangular wave frequency setting resistor connection terminal.
TSSOP
BCC
36
ch.1
ch.2
ch.3
ch.4
ch.5
OSC
Description
(Continued)
4
MB39A115
(Continued)
Pin No.
Block
name TSSOP BCC
Pin name
I/O
6
2
CTL
I
Power supply control terminal.
7
3
CTL3
I
ch.3 control terminal.
8
4
CTL4
I
ch.4 control terminal.
9
5
CTL5
I
ch.5 control terminal.
15
11
CSCP
⎯
10
6
−INS
I
35
32
VCCO
⎯
Drive output block power supply terminal.
5
1
VCC
⎯
Power supply terminal.
11
7
VREF
O
Reference voltage output terminal.
28
25
GNDO
⎯
Drive output block ground terminal.
14
10
GND
⎯
Ground terminal.
Control
Power
Description
Short-circuit detection circuit capacitor connection terminal.
Short-circuit detection comparator inverted input terminal.
5
MB39A115
■ BLOCK DIAGRAM
L
VREF priority
Error
− Amp1
+
+
10 µA
CS1 38
+
PWM
Comp.1
−
Dead Time
−INE1 37
1.0 V
FB1 36
Threshold voltage
1.0 V ± 1%
Dead Time
(td = 50 ns)
−INE2 2
CS2 1
L
VREF priority Error
Amp2
10 µA
−
+
+
L
priority
PWM
+ Comp.2
+
−
<<ch.1>>
Io = 300 mA
at VCCO = 7 V
Drive1-1
P-ch
Drive1-2
N-ch
35 VCCO
34 OUT1-1
33 OUT1-2
Io = 300 mA
at VCCO = 7 V
<<ch.2>>
Drive2
P-ch
32 OUT2
1.23 V
Io = 300 mA
at VCCO = 7 V
FB2 3
DTC2 4
−INE3 18
CS3 19
Threshold voltage
1.23 V ± 1%
L
VREF priority Error
Amp3
1 µA
−
+
+
L
priority
+
+
−
PWM
Comp.3
<<ch.3>>
Drive3
P-ch
31 OUT3
1.23 V
FB3 17
DTC3 16
−INE4 21
CS4 20
Io = 300 mA
at VCCO = 7 V
Threshold voltage
1.23 V ± 1%
L
VREF priority Error
Amp4
1 µA
−
+
+
L
priority
PWM
+ Comp.4
+
−
<<ch.4>>
Drive4
P-ch
30 OUT4
1.23 V
FB4 22
DTC4 23
−INE5 26
CS5 27
Io = 300 mA
at VCCO = 7 V
Threshold voltage
1.23 V ± 1%
L
VREF priority Error
Amp5
1 µA
−
+
+
L
priority
PWM
+ Comp.5
+
−
<<ch.5>>
Drive5
N-ch
29 OUT5
1.23 V
FB5 25
DTC5 24
28 GNDO
VREF
100 kΩ
−INS 10
Short-circuit
detection signal
(L : at short-circuit)
CSCP 15
1V
−
+
SCP
Comp.
6
H: at SCP
SCP
H : release
UVLO
0.9 V
CTL3 7
CTL4 8
CTL5 9
Io = 300 mA
at VCCO = 7 V
Threshold voltage
1.23 V ± 1%
0.4 V
UVLO2
CHCTL
OSC
12
13
RT
CT
UVLO1
Error Amp Power supply
SCP Comp. Power supply
Error Amp Reference
1.23 V
bias
Power
VREF
VR ON/OFF
CTL
Accuracy
± 0.8%
2.0 V
11
14
VREF
GND
5 VCC
6 CTL
H : ON (Power ON)
L : OFF (standby mode)
VTH = 1.0 V
MB39A115
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Power supply voltage
VCC
Rating
Condition
Unit
Min
Max
VCC, VCCO terminals
⎯
12
V
Output current
IO
OUT1 to OUT5 terminals
⎯
20
mA
Peak output current
IOP
OUT1 to OUT5 terminals
Duty ≤ 5% (t = 1/fOSC × Duty)
⎯
400
mA
Power dissipation
PD
Ta ≤ +25 °C (TSSOP-38P)
⎯
1680*1
mW
Ta ≤ +25 °C (BCC-40P)
⎯
1020*2
mW
−55
+125
°C
Storage temperature
⎯
TSTG
*1 : When mounted on a 76 × 76 × 1.6 mm FR-4 boards.
*2 : When mounted on a 117 × 84 × 0.8 mm FR-4 boards.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Start power supply voltage
VCC
VCC, VCCO terminals
(ch.5)
1.7
⎯
11
V
Power supply voltage
VCC
VCC, VCCO terminals
(ch.1 to ch.5)
2.5
7
11
V
Reference voltage output current
IREF
VREF terminal
−1
⎯
0
mA
−INE1 to −INE5 terminals
0
⎯
VCC − 0.9
V
−INS terminal
0
⎯
VREF
V
VDTC
DTC2 to DTC5 terminals
0
⎯
VREF
V
VCTL
CTL, CTL3 to CTL5
terminals
0
⎯
11
V
−15
⎯
+15
mA
Input voltage
Control Input voltage
Output current
VINE
IO
OUT1 to OUT5 terminals
Oscillation frequency
fOSC
*
0.2
1.0
2.0
MHz
Timing capacitor
CT
⎯
27
100
680
pF
Timing resistor
RT
⎯
3.0
6.2
39
kΩ
Soft-start capacitor
CS
⎯
0.1
1.0
µF
CS1 to CS5 terminals
Short-circuit detection capacitor
CSCP
⎯
⎯
0.1
1.0
µF
Reference voltage output
capacitor
CREF
⎯
⎯
0.1
1.0
µF
Ta
⎯
−30
+25
+85
°C
Operating ambient temperature
* : Refer to “■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY”.
7
MB39A115
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
8
MB39A115
■ ELECTRICAL CHARACTERISTICS
(VCC = VCCO = 7 V, Ta = +25 °C)
Parameter
Symbol Pin No.
Conditions
Value
Min
Typ
Max
2.00
Unit
VREF1
11
VREF = 0 mA
1.98
2.02
V
VREF2
11
VCC = 2.5 V to 11 V
1.975 2.000 2.025
V
VREF3
11
VREF = 0 mA to −1 mA
1.975 2.000 2.025
V
Input stability
Line
11
VCC = 2.5 V to 11 V
⎯
2*
⎯
mV
Load stability
Load
11
VREF = 0 mA to −1 mA
⎯
2*
⎯
mV
Temperature
stability
∆VREF/
VREF
11
Ta = 0 °C to +85 °C
⎯
0.20*
⎯
%
Short-circuit
output current
IOS
11
VREF = 0 V
⎯
−300*
⎯
mA
Under voltage
lockout
protection
circuit Block
(ch.1 to ch.4)
[UVLO2]
Threshold
voltage
VTH
34
VCC =
1.7
1.8
1.9
V
Hysteresis
width
VH
34
0.05
0.1
0.2
V
Reset voltage
VRST
34
VCC =
1.55
1.7
1.85
V
Under voltage
lockout
protection
circuit Block
(ch.5)
[UVLO1]
Threshold
voltage
VTH
30
VCC =
1.35
1.5
1.65
V
Hysteresis
width
VH
30
0.02
0.05
0.1
V
VRST
30
1.27
1.45
1.63
V
VTH
15
⎯
0.65
0.70
0.75
V
ICSCP
15
⎯
−1.4
−1.0
−0.6
µA
fosc1
29 to
34
CT = 100 pF,
RT = 6.2 kΩ
0.95
1.0
1.05 MHz
fosc2
29 to
34
CT = 100 pF, RT = 6.2 kΩ
VCC = 2.5 V to 11 V
0.945
1.00
1.055 MHz
Frequency
Input stability
∆fOSC/
fOSC
29 to
34
CT = 100 pF, RT = 6.2 kΩ
VCC = 2.5 V to 11 V
⎯
1.0*
⎯
%
Frequency
temperature
stability
∆fOSC/
fOSC
29 to
34
CT = 100 pF, RT = 6.2 kΩ
Ta = 0 °C to +85 °C
⎯
1.0*
⎯
%
Soft-Start Block
Charge
(ch.1, ch.2)
current
[CS1, CS2]
ICS
1, 38
CS1, CS2 = 0 V
−13
−10
−7
µA
Soft-Start Block
Charge
(ch.3 to ch.5)
current
[CS3 to CS5]
ICS
−1.3
−1.0
−0.7
µA
Output voltage
Reference
Voltage Block
[VREF]
Reset voltage
Threshold
Short-circuit
voltage
detection Block
Input source
[SCP]
current
Oscillation
frequency
Triangular
Wave Oscillator Block
[OSC]
⎯
⎯
VCC =
19, 20,
CS3 to CS5 = 0 V
27
(Continued)
9
MB39A115
(VCC = VCCO = 7 V, Ta = +25 °C)
Parameter
Threshold
voltage
Temperature
stability
Input bias
current
Error Amp Block
Voltage gain
(ch.1)
[Error Amp1]
Frequency
bandwidth
Output
voltage
Output source
current
Output sink
current
Threshold
voltage
Temperature
stability
Input bias
current
Error Amp Block Voltage gain
(ch.2 to ch.5)
[Error Amp2 to Frequency
Error Amp5]
bandwidth
Output
voltage
Output source
current
Output sink
current
Symbol Pin No.
Condition
Value
Min
Typ
Max
Unit
VTH1
37
VCC = 2.5 V to 11 V
Ta = +25 °C
0.990 1.000 1.010
V
VTH2
37
VCC = 2.5 V to 11 V
Ta = 0 °C to +85 °C
0.988 1.000 1.012
V
∆VTH/
VTH
37
Ta = 0 °C to +85 °C
IB
37
−INE1 = 0 V
AV
36
BW
36
VOH
36
VOL
36
ISOURCE
36
ISINK
36
VTH1
2, 18,
21, 26
VCC = 2.5 V to 11 V
Ta = +25 °C
1.217 1.230 1.243
V
VTH2
2, 18,
21, 26
VCC = 2.5 V to 11 V
Ta = 0 °C to +85 °C
1.215 1.230 1.245
V
∆VTH/
VTH
2, 18,
21, 26
Ta = 0 °C to +85 °C
IB
2, 18,
21, 26
−INE2 to −INE5 = 0 V
AV
3, 17,
22, 25
BW
3, 17,
22, 25
VOH
3, 17,
22, 25
VOL
3, 17,
22, 25
ISOURCE
3, 17,
22, 25
ISINK
3, 17,
22, 25
⎯
0.1*
⎯
%
−120
−30
⎯
nA
DC
⎯
100*
⎯
dB
AV = 0 dB
⎯
1.4*
⎯
MHz
⎯
1.7
1.9
⎯
V
⎯
⎯
40
200
mV
FB1 = 0.65 V
⎯
−2
−1
mA
FB1 = 0.65 V
150
200
⎯
µA
⎯
0.1*
⎯
%
−120
−30
⎯
nA
DC
⎯
100*
⎯
dB
AV = 0 dB
⎯
1.4*
⎯
MHz
⎯
1.7
1.9
⎯
V
⎯
⎯
40
200
mV
FB2 to FB5 = 0.65 V
⎯
−2
−1
mA
FB2 to FB5 = 0.65 V
150
200
⎯
µA
(Continued)
10
MB39A115
(Continued)
(VCC = VCCO = 7 V, Ta = +25 °C)
Parameter
PWM
Threshold
Comparator
voltage
Block
(ch.1 to ch.5)
[PWM Comp.1 to Input current
PWM Comp.5]
Output source
current
Output sink
current
Output Block
(ch.1 to ch.5)
Output on
[Drive1 to Drive5]
resistor
Control Block
(CTL,
CTL3 to CTL5)
[CTL, CHCTL]
VT100
Value
Unit
Min
Typ
Max
29 to 34 Duty cycle = 0%
0.35
0.4
0.45
V
29 to 34 Duty cycle = 100%
0.85
0.9
0.95
V
−2.0
−0.6
⎯
µA
IDTC
4, 16,
23, 24
ISOURCE
29 to 34
Duty ≤ 5% (t = 1/fOSC × Duty)
OUT = 0 V
⎯
−300*
⎯
mA
ISINK
29 to 34
Duty ≤ 5% (t = 1/fOSC × Duty)
OUT = 7 V
⎯
300*
⎯
mA
ROH
29 to 34 OUT = − 15 mA
⎯
9
18
Ω
ROL
29 to 34 OUT = 15 mA
⎯
9
14
Ω
DTC = 0.4 V
33, 34
OUT2
− OUT1
⎯
50*
⎯
ns
tD2
33, 34
OUT1
− OUT2
⎯
50*
⎯
ns
Threshold
voltage
VTH
34
⎯
0.97
1.00
1.03
V
Input bias
current
IB
10
−25
−20
−17
µA
Output on
condition
VIH
6, 7 to 9 CTL, CTL3 to CTL5
1.5
⎯
11
V
Output off
condition
VIL
6, 7 to 9 CTL, CTL3 to CTL5
0
⎯
0.5
V
ICTLH
6, 7 to 9 CTL, CTL3 to CTL5 = 3 V
5
30
60
µA
ICTLL
6, 7 to 9 CTL, CTL3 to CTL5 = 0 V
⎯
⎯
1
µA
Input current
General
VT0
Condition
tD1
Dead time
Short-Circuit
Detection Block
[SCP Comp.]
Symbol Pin No.
Standby
current
Power supply
current
−INS = 0 V
ICCS
5
CTL, CTL3 to CTL5 = 0 V
⎯
0
2
µA
ICCSO
35
CTL = 0 V
⎯
0
1
µA
ICC
5
CTL = 3 V
⎯
4
6
mA
* : Standard design value
Note : The pin numbers referred are present on TSSOP-38P package.
11
MB39A115
■ TYPICAL CHARACTERISTICS
Reference Voltage vs.
Power Supply Voltage
5
5
Reference Voltage VREF (V)
Power Supply Current ICC (mA)
Power Supply Current vs.
Power Supply Voltage
Ta = +25 °C
CTL = 3 V
4
3
2
1
0
0
2
4
6
10
8
12
Ta = +25 °C
CTL = 3 V
VREF = 0 mA
4
3
2
1
0
0
2
Power Supply Voltage VCC (V)
4
6
8
10
12
Power Supply Voltage VCC (V)
Reference Voltage VREF (V)
Reference Voltage vs.
Operating Ambient Temperature
2.05
2.04
VCC = 7 V
CTL = 3 V
VREF = 0 mA
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
1.95
−40
−20
0
20
40
60
80
100
Operaing Ambient Temperature Ta ( °C)
CTL Terminal Current vs.
CTL Terminal Voltage
5.0
Ta = +25 °C
VCC = 7 V
VREF = 0 mA
4.0
3.0
2.0
1.0
0.0
0
2
4
6
8
10
CTL Terminal Voltage VCTL (V)
12
CTL Terminal Current ICTL (µA)
Reference Voltage VREF (V)
Reference Voltage vs.
CTL Terminal Voltage
250
Ta = +25 °C
VCC = 7 V
200
150
100
50
0
0
2
4
6
8
10
12
CTL Terminal Voltage VCTL (V)
(Continued)
12
MB39A115
Triangular Wave Oscillation Frequency vs.
Timing Resistor
Triangular Wave Oscillation Frequency vs.
Timing Capacity
Triangular Wave Oscillation
Frequency fOSC (kHz)
Triangular Wave Oscillation
Frequency fOSC (kHz)
10000
Ta = +25 °C
VCC = 7 V
CTL = 3 V
CT = 27 pF
1000
CT = 100 pF
CT = 680 pF CT = 220 pF
100
10
1
10
100
1000
10000
Ta = +25 °C
VCC = 7 V
CTL = 3 V
1000
RT = 2.4 kΩ
RT = 36 kΩ RT = 13 kΩ
100
10
10
100
Timing Resistor RT (Ω)
1.00
0.90
Upper limit
0.80
0.70
0.60
0.50
0.40
0.30
Lower limit
0.20
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Triangular Wave Oscillation Frequency fOSC (kHz)
Triangular Wave Upper and Lower
Limit Voltage VCT (V)
Triangular Wave Upper and Lower
Limit Voltage VCT (V)
1.10
Ta = +25 °C
VCC = 7 V
CTL = 3 V
RT = 6.2 kΩ
1000
10000
Timing Capacity CT (pF)
Triangular Wave Upper and Lower Limit Voltage
vs. Triangular Wave Oscillation Frequency
1.20
RT = 6.2 kΩ
Triangular Wave Upper and Lower Limit Voltage
vs. Operating Ambient Temperature
1.20
VCC = 7 V
CTL = 3 V
RT = 6.2 kΩ
CT = 100 pF
1.10
1.00
0.90
Upper limit
0.80
0.70
0.60
0.50
0.40
Lower limit
0.30
0.20
−40
−20
0
20
40
60
80
100
Operating Ambient Temperature Ta ( °C)
Triangular Wave Oscillation
Frequency fOSC (kHz)
Triangular Wave Oscillation Frequency
vs. Operating Ambient Temperature
1100
VCC = 7 V
CTL = 3 V
RT = 6.2 kΩ
CT = 100 pF
1080
1060
1040
1020
1000
980
960
940
920
900
−40
−20
0
20
40
60
80
100
Operating Ambient Temperature Ta ( °C)
(Continued)
13
MB39A115
(Continued)
100
Ta = +25 °C
VCC = 7 V
CTL = 3 V
FB = 2 V
RT = 6.2 kΩ
CT = 100 pF
95
ON Duty (%)
90
85
80
75
70
Calculating value
65
Measurement value
60
55
50
0.6
0.65
0.7
0.75
0.8
0.85
0.9
DTC Terminal Voltage VDTC (V)
Start Power Supply Voltage VCC (V)
Start Power Supply Voltage vs. Timing Resistor
ON Duty vs. DTC Terminal Voltage
2
Ta = −30 °C
Ta = +25 °C
1.5
VCTL = VCC
CT = 100 pF
1
1
10
100
Timing Resistor RT (kΩ)
50
225
40
Ta = +25 °C
VCC = 7 V
Av
30
90
10
45
0
0
−10
−45
−20
−90
−30
−135
−40
−180
−50
1k
10 k
2.0 V
135
φ
20
180
100 k
1M
Phase φ (deg)
Error Amp Voltage Gain AV (dB)
Error Amp Voltage Gain, Phase vs. Frequency
10 kΩ
1 µF +
2.4 kΩ
IN
10 kΩ
240 kΩ
37
−
38
+
+
1.5 V
1.0 V
−225
10 M
36
OUT
Error Amp1
the same as other
channels
Frequency f (Hz)
Power Dissipation vs.
Operating Ambient Temperature
(for TSSOP-38P)
Power Dissipation vs.
Operating Ambient Temperature
(for BCC-40P)
Power Dissipation PD (mW)
Power Dissipation PD (mW)
2000
1800
1600
1400
1200
1000
800
600
400
200
0
−40
−20
0
20
40
60
80
100
Operating Ambient Temperature Ta ( °C)
14
2000
1800
1600
1400
1200
1000
800
600
400
200
0
−40
−20
0
20
40
60
80
100
Operating Ambient Temperature Ta ( °C)
MB39A115
■ FUNCTIONAL DESCRIPTION
1. DC/DC Converter Function
(1) Reference voltage block (VREF)
The reference voltage circuit uses the voltage supplied from the VCC terminal (pin 5) to generate a temperature
compensated stable voltage (2.0 V Typ) used as the reference voltage for the internal circuits of the IC. It is also
possible to supply the load current of up to 1 mA to external circuits as a reference voltage through the VREF
terminal (pin 11) .
(2) Triangular wave oscillator block (OSC)
The triangular wave oscillator block generates the triangular wave oscillation waveform width with 0.4 V to
0.9 V by the timing resistor (RT ) connected to the RT terminal (pin 12) , and the timing capacitor (CT) connected
to the CT terminal (pin 13) . The triangular wave is input to the PWM comparator circuits on the IC.
(3) Error amplifier block (Error Amp1 to Error Amp5)
The error amplifier detects output voltage of the DC/DC converter and outputs PWM control signals. An arbitrary
loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to inverted input
terminal of the error amplifier, enabling stable phase compensation for the system.
You can prevent surge currents when the IC is turned on by connecting soft-start capacitors to the CS1 terminal
(pin 38) to CS5 terminal (pin 27) which are the noninverting input terminals of the error amplifier. The IC is started
up at constant soft-start time intervals independent of the output load of the DC-DC converter.
(4) PWM comparator block (PWM Comp.1 to PWM Comp.5)
The PWM comparator block is a voltage-pulse width converter that controls the output duty depending on the
input/output voltage.
An external output transistor is turned on, during intervals when the error amplifier output voltage and DTC
voltage is higher than the triangular wave voltage.
(5) Output block (Drive1 to Drive5)
The output circuit uses a totem-pole configuration and is capable of driving an external P-ch MOS FET (main
side of ch.1, ch.2, ch.3 and ch.4) and N-ch MOS FET (synchronous rectification side of ch.1 and ch.5).
15
MB39A115
2. Channel Control Function
Use the CTL terminal (pin 6), CS1 terminal (pin 38), CS2 terminal (pin 1), CTL3 terminal (pin 7), CTL4 terminal
(pin 8), and CTL5 terminal (pin 9) to set ON/OFF to the main and each channels.
On/off setting conditions for each channel
CTL
CS1
CS2
CTL3
CTL4
CTL5
Power
ch.1
ch.2
ch.3
ch.4
ch.5
L
X
X
X
X
X
OFF
OFF
OFF
OFF
OFF
OFF
H
GND
GND
L
L
L
ON
OFF
OFF
OFF
OFF
OFF
H
HiZ
GND
L
L
L
ON
ON
OFF
OFF
OFF
OFF
H
GND
HiZ
L
L
L
ON
OFF
ON
OFF
OFF
OFF
H
GND
GND
H
L
L
ON
OFF
OFF
ON
OFF
OFF
H
GND
GND
L
H
L
ON
OFF
OFF
OFF
ON
OFF
H
GND
GND
L
L
H
ON
OFF
OFF
OFF
OFF
ON
H
HiZ
HiZ
H
H
H
ON
ON
ON
ON
ON
ON
Note : Note that current which is over stand-by current flows into VCC terminal when the CTL terminal is in “L” level
and one of the terminals between CTL3 to CTL5 terminals is set to “H” level.
(Refer to CTL3 to CTL5 terminals equivalent circuit)
• CTL3 to CTL5 terminals equivalent circuit
VCC
5
CTL3
200 kΩ
to
CTL5
86 kΩ
ESD
protection
element
223 kΩ
GND
16
14
MB39A115
3. Protection Function
(1) Timer-latch short circuit protection circuit (SCP, SCP Comp.)
The short-circuit detection comparator (SCP) detects the output voltage level of each channel. If the output
voltage of any channel is lower than the short-circuit detection voltage, the timer circuit is actuated to start
charging to the capacitor (Cscp) externally connected to the CSCP terminal (pin 15).
When the capacitor (Cscp) voltage becomes about 0.7 V, the output transistor is turned off and the dead time
is set to 100%.
The short-circuit detection from external input is capable by using −INS terminal (pin 10).
When the protection circuit is actuated, the power supply is recycled or the CTL terminal (pin 6) is set to "L"
level, resetting the latch as the voltage at the VREF terminal (pin 11) becomes 1.27 V (Min) or less (Refer to
“■SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”) .
(2) Under-voltage lockout protection circuit (UVLO)
The transient state or a momentary decrease in the power supply voltage, which occurs when the power supply
is turned on, may cause the control IC to malfunction, resulting in the breakdown or degradation of the system.
To prevent such malfunctions, under-voltage lockout protection circuit detects a decrease in internal reference
voltage level with respect to the power supply voltage, turns off the output transistor, and sets the dead time to
100% while holding the CSCP terminal (pin 15) at the "L" level.
The system returns to the normal state when the power supply voltage reaches the threshold voltage of the
under-voltage lockout protection circuit.
■ PROTECTION CIRCUIT OPERATING FUNCTION TABLE
The following table shows the state that the protection circuit is operating.
Operation circuit
OUT1-1 OUT1-2
OUT2
OUT3
OUT4
OUT5
Short-circuit protection circuit
H
L
H
H
H
L
Under voltage lockout protection circuit
H
L
H
H
H
L
17
MB39A115
■ SETTING THE OUTPUT VOLTAGE
• ch.1
R3
Vo
R1
Error
Amp 1
−
37
−INE1
36
+
+
R2
FB1
1.00 V
CS1
1.00 V
(R1 + R2)
R2
VO
(R1 + R3) ≥
100 µA
VO =
38
Set R1 and R3 refer to above formula, then error amp’s response
is not slow.
• ch.2 to ch.5
R3
Vo
R1
Error
Amp X
−
−INEX
+
+
R2
1.23 V
CSX
FBX
1.23 V
(R1 + R2)
R2
VO
(R1 + R3) ≥
100 µA
VO =
X : Each channel number
Set R1 and R3 refer to above formula, then error amp’s response
is not slow.
■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY
The triangular wave oscillation frequency can be set by connecting a timing resistor (RT ) to the RT terminal (pin
12) and a timing capacitor (CT) to the CT terminal (pin 13).
Triangular wave oscillation frequency : fOSC
fOSC (kHz) =:
18
620000
CT (pF) × RT (kΩ)
MB39A115
■ SETTING THE SOFT-START TIME
To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors
(CS1 to CS5) to the CS1 terminal (pin 38) to CS5 terminal (pin 27) respectively.
As illustrated below, when each CTLX is set to “L” from “H”, ch.1 and ch.2 charge the soft-start capacitors (CS1
and CS2) externally connected to the CS1 and CS2 terminals at about 10 µA.
When each CTLX is set to “H” from “L”, ch.3 to ch.5 charge the soft-start capacitors (CS3 to CS5) externally
connected to the CS3 to CS5 terminals at about 1 µA.
The error amplifier output (FB1 to FB5 terminals) is determined by comparison between the lower voltage of the
two non-inverted input terminal voltage (1.23 V (ch.1 : 1.0 V) , CS terminal voltage) and the inverted input terminal
voltage (−INE1 to −INE5 terminal) . The FB terminal voltage is decided for the soft-start period (CS terminal
voltage < 1.23 V (ch.1 : 1.0 V) ) by the comparison between −INE terminal voltage and CS terminal voltage. The
DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor externally
connected to the CS terminal is charged. The soft-start time is obtained from the following formula :
Soft-start time : ts (time until output 100%)
ch.1
: ts (s) =: 0.100 × CSX (µF)
ch.2
: ts (s) =: 0.123 × CSX (µF)
ch.3 to ch.5 : ts (s) =: 1.23 × CSX (µF)
• Soft-start circuit (ch.1, ch.2)
VREF
Vo
10 µA
R1
−INEX
R2
L priority
Error Amp X
CSX
−
+
+
1.0 V/1.23 V
CSX
CTLX
FBX
X : Each channel number
19
MB39A115
• Soft-start circuit (ch.3 to ch.5)
VREF
Vo
1 µA
R1
−INEX
R2
L priority
Error Amp X
−
+
+
CSX
1.23 V
CSX
FBX
CTLX
CHCTL
X : Each channel number
20
MB39A115
■ PROCESSING WHEN NOT USING CS TERMINAL
When soft-start function is not used, leave the CS1 terminal (pin 38), the CS2 terminal (pin 1), the CS3 terminal
(pin 19), the CS4 terminal (pin 20) and the CS5 terminal (pin 27) open.
• When not setting soft-start time
“Open”
“Open”
1
CS2
CS1
38
CS5
27
CS4
20
“Open”
“Open”
“Open”
19
CS3
21
MB39A115
■ SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION
CIRCUIT
Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier’s
output level to the reference voltage.
While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output
remains at “L” level, and the CSCP terminal (pin 15) is held at “L” level.
If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage
to drop, the output of the short-circuit detection comparator on that channel goes to “H” level.
This causes the external short-circuit protection capacitor CSCP connected to the CSCP terminal (pin 15) to be
charged at 1 µA.
Short-circuit detection time : tCSCP
tCSCP (s) =: 0.70 × CSCP (µF)
When the capacitor CSCP is charged to the threshold voltage (VTH =: 0.70 V) , the latch is set to and the external
FET is turned off (dead time is set to 100%) . At this time, the latch input is closed and CSCP terminal (pin 15)
is held at “L” level.
The short-circuit detection from external input is capable by using −INS terminal (pin 10) . In this case, the shortcircuit detection operates when the −INS terminal voltage becomes the level of the threthold voltage (VTH =: IV)
or less.
22
MB39A115
Note that the latch is reset as the voltage at the VREF terminal (pin 11) is decreased to 1.27 V (Min) or less by
either recycling the power supply or setting the CTL terminal (pin 6) to “L” level.
• Timer-latch short-circuit protection circuit
Vo
FBX
R1
−
−INEX
Error
Amp
+
R2
1.23 V (ch.1 : 1.0 V)
SCP
Comp.
+
+
−
1.1 V
1 µA
To each
channel drive
CSCP
CTL
15
VREF
S
R
Latch
UVLO
X : Each channel
number
23
MB39A115
■ PROCESSING WHEN NOT USING CSCP TERMINAL
To disable the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 15) to GND in the
shortest distance.
• Processing when not using the CSCP terminal
24
14
GND
15
CSCP
MB39A115
■ SETTING THE DEAD TIME
When the device is set for step-up or inverted output based on the step-up, step-up/down Zeta method, step up/
down Sepic method, or flyback method, the FB terminal voltage may reach and exceed the triangular wave
voltage due to load fluctuation. If this is the case, the output transistor is fixed to a full-ON state (ON duty =
100%). To prevent this, set the maximum duty of the output transistor.
When the DTC terminal is opened the maximum duty is 90% (Typ) because of this IC built-in resistor which sets
the DTC terminal voltage.
To disable the DTC terminal, connect it to the VREF terminal (pin 11) as illustrated below (when dead time is
not set).
• When dead time is set:
(Setting with built-in resistor =: 90%)
• When dead time is not set:
11 VREF
“Open”
DTCX
DTCX
X : Each channel number
X : Each channel number
To change the maximum duty using external resistors, set the DTC terminal voltage by dividing resistance using
the VREF voltage. Refer to "When dead time is set : (Setting by external resistors)."
It is possible to set without regard for the built-in resistance value (including tolerance) when setting the external
resistance value to 1/10 of the built-in resistance or less.
Note that the VREF load current must be set such that the total current for all the channels does not exceed 1 mA.
When the DTC terminal voltage is higher than the triangular wave voltage, the output transistor is turned on.
The formula for calculating the maximum duty is as follows, assuming that the triangular wave amplitude and
triangular wave lower limit voltage are about 0.5 V and 0.4 V, respectively.
DUTY (ON) Max =:
Vdt =
Rb
Ra + Rb
Vdt − 0.4 V
0.5 V
× 100 (%)
× VREF (condition : Ra <
R1
10
, Rb <
R2
10
)
Note : DUTY obtained by the above-mentioned formula is a calculated value. For setting, refer to “ON Duty vs.
DTC Terminal Voltage” in “■ TYPICAL CHARACTERISTICS”.
25
MB39A115
• When dead time is set :
(Setting by external resistors)
VREF
11
Ra
R1 : 131.9 kΩ
DTCX
Vdt
Rb
GND
To PWM
Comp.X
R2 : 97.5 kΩ
14
X : Each channel number
Setting example (for an aim maximum ON duty of 80% (Vdt = 0.8 V) with Ra = 13.7 kΩ and Rb = 9.1 kΩ)
• Calculation using external resistors Ra and Rb only
Vdt =
Rb
Ra + Rb
DUTY (ON) Max=:
× VREF =: 0.80 V
Vdt − 0.4 V
0.5 V
× 100 (%) =: 80% ⋅ ⋅ ⋅ ⋅ (1)
• Calculation taking account of the built-in resistor (tolerance ± 20%) also
Vdt =
(Rb, R2 Combined resistance)
(Ra, R1 Combined resistance) + (Rb, R2 Combined resistance)
DUTY (ON) Max=:
Vdt − 0.4 V
0.5 V
× VREF =: 0.80 V ± 0.13%
× 100 (%) =: 80% ± 0.2% • • • • (2)
Based on (1) and (2) above, selecting external resistances of 1/10th or less of the built-in resistance enables
the built-in resistance to be ignored.
As for the duty dispersion, please expect ± 5% at (fosc = 1 MHz) due to the dispersion of a triangular wave
amplitude.
26
MB39A115
■ OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF
When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds each threshold
voltage (VTH1, 2) of UVLO1 and UVLO2 (under voltage lockout protection circuit) , UVLO1 and UVLO2 are
released, and the operation of output drive circuit of each channel becomes possible.
When CTL is off, VR and VREF fall. When VREF decreases and UVLO1 and UVLO2 fall below each reset
voltage (VRST1, 2) , UVLO operates and output drive circuit of each channel is forcibly done the operation stop,
and makes the output an off state.
In the period until reaching to 2.0 V by VREF voltage after UVLO1 and UVLO2 are released by turning on CTL
(refer to a and b in “• Timing chart”) and the period until decreasing of VREF from 2.0 V after off CTL and
operating of UVLO1 and UVLO2 (refer to a’ and b’ in “• Timing chart”) , the bias voltage and the bias current in
IC do not reach a prescribed value because VREF which is the reference voltage does not reach 2.0 V, and
the speed of response of IC has decreased.
Moreover, when in this period IC does the input sudden charge or the load sudden charge or turning on and off
of CTL3 to CTL5, IC cannot conform and the output might overshoot. Therefore, impress the voltage to CTL
terminal by which the VREF voltage never stays in the above-mentioned period.
• CTL block equivalent circuit
H : at SCP
SCP
ch.1 to ch.4
To output drive circuit
H : Possible to operate
L : Forced stop
CS1 to CS4
To charge/discharge circuit
H : Possible to charge
L : Forced discharge
UVLO2
H : UVLO release
UVLO1
bias
ch.5
To output drive circuit
H : Possible to operate
L : Forced stop
CS5
Error Amp reference To charge/discharge circuit
H : Possible to charge
1.0 V/1.23 V
L : Forced discharge
VCC
5
H : UVLO release
VREF
VR
Power
ON/OFF
CTL
6
CTL
11
VREF
27
MB39A115
• Timing chart
VR = 1.23 V (Typ)
Error Amp
Reference
voltage VR
VTH1
VTH2
VREF = 2.00 V (Typ)
VRST2
VRST1
Reference
voltage
VREF
UVLO5 release
b
UVLO5
b
UVLO5 effect
a
UVLO1 to 4
ch.5
Output Drive
circuit control
UVLO1 to UVLO4 release
a
UVLO1 to
UVLO4 effect
Possible operate
Fixed full off
Fixed full off
Possible operate
ch.1 to ch.4
Output Drive
circuit control
CTL
terminal
voltage
28
Fixed full off
Fixed full off
1.1 ± 0.2 V (Typ)
MB39A115
■ ABOUT THE LOW VOLTAGE OPERATION
1.7 V or more is necessary for the VCC terminal (pin 5) and the VCCO terminal (pin 35) for the self-power supply
type to use the step-up circuit as the start voltage.
Even if thereafter VIN voltage decreases to 1.5 V, operation is possible if the VCC terminal voltage and the
VCCO terminal voltage rise to 2.5 V or more after start-up. However, it is necessary not to exceed the maximum
duty set value by the duty due to the VIN decrease. Including other channels, execute an enough operation
margin confirmation when using it.
VIN
A
Step-up A
<<ch.5>>
R1
R2
26
−INE5
VREF
R4
CS5
27
Error
Amp5
−
+
+
1.23 V
PWM
Comp.5
Drive5
+
+
N-ch
−
VCCO
35
29
0.9 V
0.4 V
Vo5
(5 V)
OUT5
VCC
5
DTC5
24
Max Duty R5
setting
29
MB39A115
■ I/O EQUIVALENT CIRCUIT
• Channel control block (ch.3 to ch.5)
• Control block
• Reference voltage block
VCC
VCC 5
1.23 V
ESD
protection
element
+
−
CTL 6
ESD
protection
element
CTLX
53 kΩ
11 VREF
86 kΩ
79 kΩ
124 kΩ
ESD
protection
element
278 kΩ
223 kΩ
GND
GND
GND 14
• Soft-start block
• Short-circuit detection block
• Short-circuit detection
comparator block
VCC
VREF
(2.0 V)
VREF
(2.0 V)
100 kΩ
VREF
(2.0 V)
CSX
−INS 10
(1 V)
2 kΩ
15 CSCP
GND
GND
• Triangular wave oscillator block (RT)
GND
• Triangular wave oscillator block (CT)
VREF
(2.0 V)
VREF
(2.0 V)
0.64 V
+
−
CT 13
12 RT
GND
GND
• Error amplifier block (ch.1 to ch.5)
VCC
VREF
(2.0 V)
−INEX
CSX
FBX
1.0 V (ch.1)
1.23 V (ch.2 to ch.5)
GND
X : Each cannel No.
(Continued)
30
MB39A115
(Continued)
• PWM comparator block
• Output block (ch.1 to ch.5) )
VCC
VCCO 35
FB2 to FB5
CT
OUTX
DTCX
GNDO 28
GND
X : Each cannel No.
31
MB39A115
■ APPLICATION EXAMPLE
Step down
(synchronous
rectification)
A
A
R14 R15
510 Ω 4.3 kΩ −INE1
37
R16
24 kΩ
CS1
38
R17
C18
1 kΩ
1.5 µF
Q1
VCCO
35
0.1µF
C17
34
OUT1-1
L1
Vo1
1.2 V/600 mA
4.7 µH
C1
1 µF
D1
Q2
C2
2.2 µF
<<ch.1>>
FB1
36
C19
0.1 µF
33
OUT1-2
Step down
B
R18 R19
510 Ω 15 kΩ −INE2
R20
15 kΩ
C20
1.5 µF
VIN
(5.5 V to 8.5 V)
CS2
2
1
R21
1 kΩ
32
<<ch.2>>
C3
1 µF
OUT2
C4
2.2 µF
D2
Step down
C
L3
Q4
Vo3
3.3 V/200 mA
22 µH
C5
1 µF
31
<<ch.3>>
C6
2.2 µF
D3
OUT3
Step down
D
L4
Q5
DVo4
5.0 V/100 mA
47 µH
C7
1 µF
30
<<ch.4>>
29
28
Q7
OUT5
GNDO
C12
1 µF
E
TVo5-1
15 V/40 mA
D7
T2
<<ch.5>>
C8
2.2 µF
D4
OUT4
Transformer
D9
C13
C15
2.2
µF
2.2
µF
CSCP
15
C28
2200 pF
5
CTL3 7
CTL4 8
CTL5 9
6
H : ON
L : OFF
VTH = 1.0
VCC
C16
0.1 µF
CTL
H : ON (Power ON)
L : OFF (Standby state)
VTH = 1.0 V
12
RT
R42
6.2 kΩ
32
Vo2
2.5 V/400 mA
10 µH
FB2
3
C21
0.1 µF DTC2
4
R24 R25
3.3 kΩ 22 kΩ −INE3
C
18
R26
15 kΩ
CS3
19
R27
C22
1 kΩ
0.15 µF
FB3
17
C23
0.1 µF DTC3
16
R30 R31
3 kΩ 43 kΩ −INE4
D
21
R32
15 kΩ
CS4
20
R33
C24
1 kΩ
0.15 µF
FB4
22
C25
0.1 µF DTC4
23
R36 R37
12 kΩ 100 kΩ −INE5
E
26
R38
10 kΩ
CS5
27
R39
C26
0.15 µF
1 kΩ
FB5
R40
25
C27
33 kΩ 0.1 µF DTC5
24
R41
20 kΩ
Short-circuit
−INS
detection signal
10
(L : at short-circuit)
Charge
current
1 µA
B
L2
Q3
13
Accuracy
CT
±5%
C29
100 pF (2.0 MHz)
11
VREF
C30
0.1
µF
Accuracy
± 1%
14
GND
TVo5-3
−15 V/−10 mA
MB39A115
■ PARTS LIST
COMPONENT
ITEM
SPECIFICATION
VENDOR
PARTS No.
Q1, Q3 to Q5
Q2, Q7
P-ch FET
N-ch FET
VDS = −20 V, ID = −1.0 A
VDS = 30 V, ID = 1.4 A
SANYO
SANYO
MCH3307
MCH3408
D1 to D4
D7, D9
Diode
Diode
VF = 0.4 V (Max) , at IF = 1 A
VF = 0.55 V (Max) , at IF = 0.5 A
SANYO
SANYO
SBS004
SB05-05CP
L1
L2
L3
L4
Inductor
Inductor
Inductor
Inductor
4.7 µH
10 µH
22 µH
47 µH
1.4 A, 37 mΩ
0.94 A, 56 mΩ
0.63 A, 130 mΩ
0.59A, 210 mΩ
TDK
TDK
TDK
TDK
RLF5018T-4R7M1R4
RLF5018T-100MR94
RLF5018T-220MR63
SLF6028T-470MR59
T2
Transformer
⎯
⎯
SUMIDA
CLQ52 5388-T139
C1, C3, C5, C7
C2, C4, C6, C8
C12
C13, C15
C16, C17, C19
C18, C20
C21, C23, C25
C22, C24, C26
C27, C30
C28
C29
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
1 µF
2.2 µF
1 µF
2.2 µF
0.1 µF
1.5 µF
0.1 µF
0.15 µF
0.1 µF
2200 pF
100 pF
25V
25V
25V
25V
50V
10V
50V
16V
50V
50V
50V
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
C3216JB1E105K
C3216JB1E225K
C3216JB1E105K
C3216JB1E225K
C1608JB1H104K
C2012JB1A155K
C1608JB1H104K
C1608JB1C154K
C1608JB1H104K
C1608JB1H222K
C1608CH1H101J
R14, R18
R15
R16
R17, R21, R27
R19, R20, R26
R24
R25
R30
R31
R32
R33, R39
R36
R37
R38
R40
R41
R42
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
510 Ω
4.3 kΩ
24 kΩ
1 kΩ
15 kΩ
3.3 kΩ
22 kΩ
3 kΩ
43 kΩ
15 kΩ
1 kΩ
12 kΩ
100 kΩ
10 kΩ
33 kΩ
20 kΩ
6.2 kΩ
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
RR0816P-511-D
RR0816P-432-D
RR0816P-243-D
RR0816P-102-D
RR0816P-153-D
RR0816P-332-D
RR0816P-223-D
RR0816P-302-D
RR0816P-433-D
RR0816P-153-D
RR0816P-102-D
RR0816P-123-D
RR0816P-104-D
RR0816P-103-D
RR0816P-333-D
RR0816P-203-D
RR0816P-622-D
Notes : SANYO
TDK
SUMIDA
ssm
: SANYO Electric Co., Ltd.
: TDK Corporation
: Sumida Corporation
: SUSUMU CO., LTD.
33
MB39A115
■ REFERENCE DATA
TOTAL Efficiency vs. Input Voltage
100
TOTAL Efficiency η (%)
95
90
85
Ta = +25 °C
Vo1 = 1.2 V, 600 mA
Vo2 = 2.5 V, 400 mA
Vo3 = 3.3 V, 200 mA
Vo4 = 5.0 V, 100 mA
Vo5-1 = 15 V, 40 mA
Vo5-3 = −15 V, −10 mA
fosc = 1 MHz setting
80
75
70
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
Input Voltage VIN (V)
Each Channel Efficiency vs. Input Voltage
Each Channel Efficiency η (%)
100
95
ch.4
90
ch.3
ch.2
85
ch.5
80
Ta = +25 °C
Vo1 = 1.2 V, 600 mA
Vo2 = 2.5 V, 400 mA
Vo3 = 3.3 V, 200 mA
Vo4 = 5.0 V, 100 mA
Vo5-1 = 15 V, 40 mA
Vo5-3 = −15 V, −10 mA
fosc = 1 MHz setting
75
70
5.0
5.5
6.0
ch.1
Note : Only concerned channel is ON.
Including external SW Tr driving current
6.5
7.0
7.5
8.0
8.5
9.0
Input Voltage VIN (V)
(Continued)
34
MB39A115
ch.1 and ch.2 Efficiency vs. Load Current
100
VIN = 7.2 V
Ta = +25 °C
ch.1 and ch.2 Efficiency η (%)
95
IO1 (ch.1)
IO2 (ch.2)
120 mA: Discontinuance mode
100 mA: Discontinuance mode
90
ch.2
85
ch.1
80
75
70
Note : Only concerned channel is ON.
Including external SW Tr driving current
65
60
0
50
100
150
200
250
300
350
400
450
500
550
600
Load Current IO (mA)
ch.3 and ch.4 Efficiency vs. Load Current
100
ch.4
ch.3 and ch.4 Efficiency η (%)
95
90
ch.3
VIN = 7.2 V
Ta = +25 °C
85
80
75
70
IO3 (ch.3) 50 mA:
Discontinuance mode
IO4 (ch.4) 30 mA:
Discontinuance mode
65
Note : Only concerned channel is ON.
Including external SW Tr driving current
60
0
50
100
150
200
250
300
350
400
Load Current IO (mA)
(Continued)
35
MB39A115
ch.5 Efficiency vs. Load Current
100
95
VIN = 7.2 V
Ta = +25 °C
ch.5 Efficiency η (%)
90
85
80
ch.5
75
70
65
IO5-1
30 mA: Discontinuance mode
Notes
Only feedback controlling output is get
by using transformer channel.
TVO5-3 ( 15 V): IO = 10 mA fixed
Only concerned channel is ON.
Including external SW Tr driving current
60
0
10
20
30
40
50
60
Load Current IO (mA)
(Continued)
36
MB39A115
Switching waveform
OUT1-1 [V]
10
5
OUT1-2 [V]
ch.1
VIN = 7.2 V
Vo1 = 1.2 V
lo1 = 600 mA
10
0
5
0
VD [V]
10
5
0
t [µs]
0 0.05 0.10 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
ch.2
VIN = 7.2 V
Vo2 = 2.5 V
lo2 = 400 mA
OUT2 [V]
10
T
5
0
VD [V]
10
5
0
t [µs]
0
OUT3 [V]
10
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ch.3
VIN = 7.2 V
Vo3 = 3.3 V
lo3 = 200 mA
T
5
0
VD [V]
10
5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
t [µs]
(Continued)
37
MB39A115
(Continued)
ch.4
VIN = 7.2 V
Vo4 = 5 V
lo4 = 100 mA
OUT4 [V]
10
5
T
0
VD [V]
10
5
0
t [µs]
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ch.5
VIN = 7.2 V
Vo5-1 = 15 V
Vo5-3 = −15 V
Io5-1 = 40 mA
lo5-3 = −10 mA
OUT5 [V]
10
5
0
VD [V]
15
10
5
0
t [µs]
0
38
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MB39A115
■ USAGE PRECAUTIONS
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply a negative voltages.
• The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause
abnormal operation.
■ ORDERING INFORMATION
Part number
Package
MB39A115PFT
38-pin plastic TSSOP
(FPT-38P- M03)
MB39A115PV2
40-pin plastic BCC
(LCC-40P-M07)
Remarks
39
MB39A115
■ PACKAGE DIMENSIONS
38-pin plastic TSSOP
Lead pitch
0.50 mm
Package width ×
package length
4.40 × 9.70 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.10 mm MAX
(FPT-38P-M03)
38-pin plastic TSSOP
(FPT-38P-M03)
9.70±0.10(.382±.004)
1.10(.043)
MAX
0~8˚
0.60±0.10
(.024±.004)
0.25(.010)
0.10±0.10
(.004±.004)
4.40±0.10 6.40±0.10
(.173±.004) (.252±.004)
INDEX
0.127±0.05
(.005±.002)
0.50(.020)
0.90±0.05
(.035±.002)
0.10(.004)
9.00(.354)
C
2002 FUJITSU LIMITED F38003Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
40
MB39A115
(Continued)
40-pin plastic BCC
Lead pitch
0.50 mm
Package width ×
package length
6.00 mm × 6.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.05 g
(LCC-40P-M07)
40-pin plastic BCC
(LCC-40P-M07)
21
31
5.20(.205)TYP
5.10(.201)TYP
0.80(.031)MAX
(Mount height)
6.00±0.10(.236±.004)
0.50(.020)
TYP
21
0.50±0.10
(.020±.004)
0.50(.020)
TYP
0.14(.006)
MIN
6.00±0.10
(.236±.004)
31
5.25(.207)
REF
5.20(.205)
TYP
4.00(.157)
REF
0.50±0.10
(.020±.004)
INDEX AREA
5.10(.201)
TYP
"C"
11
11
1
"B"
0.075±0.025
(.003±.001)
(Stand off)
Details of "A" part
0.14(.006)
MIN
"A"
4.00(.157)REF
5.25(.207)REF
Details of "B" part
0.70±0.06
(.028±.002)
1
0.55±0.06
(.022±.002)
Details of "C" part
C0.20(.008)
0.55±0.06
(.022±.002)
0.05(.002)
0.60±0.06
(.024±.002)
C
2004 FUJITSU LIMITED C40057S-c-1-1
0.30±0.06
(.012±.002)
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
41
MB39A115
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited
Business Promotion Dept.
F0604