STMICROELECTRONICS EMIF10

EMIF10-LCD01F2
IPAD™
10 line EMI filter and ESD protection
Main product characteristics:
Where EMI filtering in ESD sensitive equipment is
required :
■
LCD for Mobile phones
■
Computers and printers
■
Communication systems
■
MCU Boards
Flip-Chip
(25 bumps)
Description
The EMIF10-LCD01F2 is a 10 line highly
integrated device designed to suppress EMI/RFI
noise in all systems subjected to electromagnetic
interferences. The EMIF10 Flip-Chip packaging
means the package size is equal to the die size.
This filter includes ESD protection circuitry, which
prevents damage to the application when it is
subjected to ESD surges up to 15 kV.
Order code
Part Number
Marking
EMIF10-LCD01F2
FL
Figure 1.
Benefits
■
EMI symmetrical (I/O) low-pass filter
■
High efficiency in EMI filtering
■
Very low PCB space consuming: < 6 mm2
■
Lead free package
■
Very thin package: 0.69 mm
■
High efficiency in ESD suppression on input
pins (IEC 61000-4-2 level 4)
■
High reliability offered by monolithic integration
■
High reducing of parasitic elements through
integration and wafer level packaging.
Figure 2.
Pin Configuration (bump side)
5
4
3
2
1
I5
I4
I3
I2
I1
A
I10
I9
I8
I7
I6
B
GND
GND
GND
GND
GND
C
O10
O9
O8
O7
O6
D
O5
O4
O3
O2
O1
E
Basic Cell Configuration
Low-pass Filter
Output
Input
Ri/o = 100Ω
Cline = 35pF
Complies with following standards:
GND
GND
GND
IEC 61000-4-2
level 4 input pins
15 kV
(air discharge)
8 kV
(contact discharge)
MIL STD 883G - Method 3015-7 Class 3
January 2007
TM: IPAD is a trademark of STMicroelectronics.
Rev 3
1/8
www.st.com
8
Characteristics
EMIF10-LCD01F2
1
Characteristics
Table 1.
Absolute Maximum Ratings (Tamb = 25° C)
:
Symbol
Tj
Parameter
Value
Unit
125
°C
Junction temperature
Top
Operating temperature range
-40 to + 85
°C
Tstg
Storage temperature range
-55 to +150
°C
Table 2.
Electrical Characteristics (Tamb = 25° C)
Symbol
Parameter
I
VBR
Breakdown voltage
IRM
Leakage current @ VRM
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic resistance
IPP
Peak pulse current
RI/O
Series resistance between Input and Output
Cline
Input capacitance per line
IF
Symbol
IPP
Min.
Typ.
Max.
Unit
6
8
10
V
500
nA
100
110
Ω
@ 0 V bias
28
35
pF
Induced rise and fall time 10-90% at 26 MHz frequency
signal V = 1.9 V (Rt / Ft input 1 ns, 50Ω impedance generator)
8(1)
IR = 1 mA
IRM
VRM = 3 V
90
RI/O
Rt / Ft
V
IRM
IR
Test conditions
VBR
Cline
VF
VCL VBR VRM
ns
1. guaranteed by design
Figure 3.
0
S21(dB) attenuation measurement
Figure 4.
dB
10
-10
-10
-20
-30
-30
-50
-40
Analog cross talk measurement
dB
-70
F(Hz)
F(Hz)
-50
0.1 M
2/8
1.0 M
10.0 M
100.0 M 1.0 G
10.0 G
-90
0.1 M
1.0 M
10.0 M 100.0 M
1.0 G
10.0 G
EMIF10-LCD01F2
Figure 5.
Figure 7.
ESD response to IEC 61000-4-2
Figure 6.
(+15 kV air discharge) on one input
and on one output
ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input
and on one output
Vin
Vin
Vout
Vout
Line capacitance versus applied
voltage
CLine(pF)
35
30
25
20
15
10
5
0
0.0
1.0
Figure 9.
Characteristics
Figure 8.
Rise time 10-90% measurements
with 1.9 V signal at 26 MHz
frequency (50 Ω generator)
VLine(V)
2.0
3.0
4.0
5.0
Fall time 10-90% measurements
with 1.9 V signal at 26 MHz
frequency (50 Ω generator)
3/8
Characteristics
EMIF10-LCD01F2
Figure 10. Aplac model
EMIF10-LCD01F2 model
Ground return
Figure 11. Aplac parametersl
ZRZ structure
aplacvar Remif10low 100
aplacvar Cemif10flow 17.5pF
Bumps
aplacvar Lbump 50pH
aplacvar Rbump 20m
aplacvar Cbump 1.5pF
Bulk
aplacvar Rsub 100m
Gnd connections
aplacvar Rgnd 100m
aplacvar Lgnd 200pH
aplacvar Cgnd 0.15pF
4/8
BV = 7
CJO = Cemif10low
IBV = 1u
IKF = 1000
IS = 10f
ISR = 100p
N=1
M = 0.3333
RS = 0.015
VJ = 0.6
TT = 50n
EMIF10-LCD01F2
2
Ordering information scheme
Ordering information scheme
EMIF
yy
-
xxx zz
Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
= 3: Leadfree Pitch = 400µm, Bump = 250µm
Package information
Figure 12. Flip-Chip Dimensions
500 µm ± 50
315 µm ± 50
2.42 mm ± 50µm
Figure 13. Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year ww = week)
650 µm ± 65
2.42 mm ± 50µm
500 µm ± 50
3
250 µm ± 40
Figure 14. Footprint recommendation
Copper pad Diameter:
250µm recommended, 300 µm max
E
x x z
y ww
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 315 µm copper pad diameter
5/8
Ordering information
EMIF10-LCD01F2
Figure 15. Flip-Chip tape and reel specification
Dot identifying Pin A1 location
1.75 +/- 0.1
Ø 1.5 +/- 0.1
4 +/- 0.1
3.5 +/- 0.1
ST E
xxz
yww
ST E
xxz
yww
ST E
xxz
yww
8 +/- 0.3
0.73 +/- 0.05
4 +/- 0.1
User direction of unreeling
All dimensions in mm
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Note:
More packing information is available in the application notes:
AN1235: “Flip-Chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
4
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Ordering information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
EMIF10-LCD01F2
FL
Flip-Chip
9.3 mg
5000
Tape and reel (7”)
EMIF10-LCD01F2
5
Revision history
Revision history
Date
Revision
Changes
14-Feb-2005
1
Initial release.
17-Mar-2005
2
Capacitance Cline specification changed from 47 pF (typ) to 28 pF
(typ) and 35 pF (max).
30-Jan-2007
3
Reformatted to current standards. Reduced die size and updated
Figures 3 and 4.
7/8
EMIF10-LCD01F2
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