STS1NK60Z N-CHANNEL 600V - 13Ω - 0.25A - SO-8 Zener-Protected SuperMESH™ Power MOSFET TYPE STS1NK60Z VDSS RDS(on) ID Pw 600 V < 15 Ω 0.25 A 2W TYPICAL RDS(on) = 13Ω EXTREMELY HIGH dv/dt CAPABILITY ESD IMPROVED CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. SO-8 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS AC ADAPTORS AND BATTERY CHARGERS SWITH MODE POWER SUPPLIES (SMPS) ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STS1NK60Z S1NK60Z SO-8 TAPE & REEL June 2003 1/8 STS1NK60Z ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 600 V Drain-gate Voltage (RGS = 20 kΩ) 600 V Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 0.25 A ID Drain Current (continuous) at TC = 100°C 0.16 A 1 A IDM () PTOT Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor VESD(G-S) dv/dt (1) Tj Tstg 2 W 0.016 W/°C 800 V Gate source ESD(HBM-C=100pF, R=1.5KΩ) Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature 4.5 V/ns -55 to 150 -55 to 150 °C °C 62.5 °C/W ( ) Pulse width limited by safe operating area (1) ISD ≤0.3A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. THERMAL DATA Rthj-amb Thermal Resistance Junction-ambient Max GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/8 STS1NK60Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Test Conditions Min. Typ. Max. Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 50 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 50 µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 0.4 A V(BR)DSS 600 Unit 3 V 3.75 4.5 V 13 15 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Test Conditions Min. VDS = V, ID = 0.4 A VDS = 25V, f = 1 MHz, VGS = 0 VGS = 0V, VDS = 0V to 480V 0.5 S 94 17.6 2.8 pF pF pF 11 pF SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 300V, ID = 0.4 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) 5.5 5 ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 480V, ID = 0.8 A, VGS = 10V 4.9 1 2.7 6.9 nC nC nC Typ. Max. Unit SWITCHING OFF Symbol Parameter Test Conditions Min. td(off) tf Turn-off Delay Time Fall Time VDD = 300V, ID = 0.4A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) 13 28 ns ns tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time VDD =480V, ID = 0.8A, RG = 4.7Ω, VGS = 10V (Inductive Load see, Figure 5) 28 12.5 48 ns ns ns SOURCE DRAIN DIODE Symbol Parameter Test Conditions ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 0.25A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 0.8 A, di/dt = 100A/µs VDD = 20V, Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM Min. Typ. 140 224 3.2 Max. Unit 0.25 1 A A 1.6 V ns nC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/8 STS1NK60Z Safe Operating Area Thermal Impedance Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/8 STS1NK60Z Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/8 STS1NK60Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STS1NK60Z SO-8 MECHANICAL DATA mm DIM. MIN. TYP. A a1 MIN. TYP. 1.75 0.1 0.003 0.009 1.65 0.65 MAX. 0.068 0.25 a2 a3 inch MAX. 0.064 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 c1 45 (typ.) e 1.27 e3 3.81 0.050 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8 (max.) 0016023 7/8 STS1NK60Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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