STP10NK70ZFP STP10NK70Z N-CHANNEL 700V - 0.75Ω - 8.6A - TO220-TO220FP Zener-Protected SuperMESH™ MOSFET General features Type VDSS Package RDS(on) STP10NK70Z 700 V <0.85 Ω STP10NK70ZFP 700 V <0.85 Ω ID Pw 8.6 A 8.6 A 110 W 35 W ■ EXTREMELY HIGH dv/dt CAPABILITY ■ IMPROVED ESD CAPABILITY ■ 100% AVALANCHE TESTED ■ GATE CHARGE MINIMIZED ■ VERY LOW INTRINSIC CAPACITANCES ■ VERY GOOD MANUFACTURING REPEABILITY 3 1 TO-220 2 3 1 2 TO-220FP Internal schematic diagram Description The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Applications ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTOR AND PFC Order codes Sales Type Marking Package Packaging STP10NK70Z P10NK70Z TO-220 TUBE STP10NK70ZFP P10NK70ZFP TO-220FP TUBE August 2005 Rev 2 1/13 www.st.com 13 STP10NK70Z - STP10NK70ZFP 1 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value TO-220 VDS VDGR VGS Unit TO-220FP Drain-Source Voltage (VGS = 0) 700 V Drain-gate Voltage (RGS = 20kΩ) 700 V Gate-Source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 8.6 8.6 (Note 3) A ID Drain Current (continuous) at TC = 100°C 5.4 5.4 (Note 3) A Drain Current (pulsed) 34 34 (Note 3) A Total Dissipation at TC = 25°C 150 35 W Derating Factor 1.20 0.28 W/°C IDM Note 2 PTOT Vesd(G-S) G-S ESD (HBM C=100pF, R=1.5kΩ) 4000 V dv/dt Note 1 Peak Diode Recovery voltage slope 4.5 V/ns VISO Insulation Withstand Volatge (DC) Tj Tstg Table 2. -- Operating Junction Temperature Storage Temperature 2500 -55 to 150 V °C Thermal data TO-220 TO-220FP Unit 0.83 3.6 °C/W Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-amb Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tl Table 3. Avalanche characteristics Symbol Parameter Max Value Unit IAR Avalanche Current, repetitive or Not-Repetitive (pulse width limited by Tj max) 8.6 A EAS Single Pulse Avalanche Energy (starting Tj=25°C, ID=IAR, VDD = 50V) 350 mJ 2/13 STP10NK70Z - STP10NK70ZFP 2 2 Electrical characteristics Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol Parameter V(BR)DSS Drain-Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current (VGS = 0) IGSS Test Conditions ID = 1mA, V GS= 0 Min. Typ. Max. 700 Unit V VDS = Max Rating, VDS = Max Rating,Tc = 125°C 1 50 µA µA Gate Body Leakage Current (VDS = 0) VGS = ±20V, VDS = 0 ±10 µA VGS(th) Gate Threshold Voltage VDS= VGS, ID = 100 µA 3.75 4.5 V RDS(on) Static Drain-Source On Resistance VGS= 10 V, ID= 4.5 A 0.75 0.85 Ω Typ. Max. Unit Table 5. Symbol gfs Note 4 Ciss Coss Crss Coss eq. Note 5 Qg Qgs Qgd Table 6. Symbol td(on) tr td(off) tf tr(Voff) tf tc 3 Dynamic Parameter Forward Transconductance Test Conditions Min. VDS =15V, ID = 4.5A Input Capacitance VDS =25V, f=1 MHz, V GS=0 Output Capacitance Reverse Transfer Capacitance Equivalent Ouput Capacitance VGS=0, VDS =0V to 560V Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=560V, ID = 9 A VGS =10V (see Figure 17) 7.7 S 2000 190 41 pF pF pF 98 pF 64 12 33 90 nC nC nC Typ. Max. Unit Switching times Parameter Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD=350 V, ID=4.5 A, RG=4.7Ω, VGS=10V (see Figure 18) VDD=350 V, ID=4.5A, RG=4.7Ω, VGS=10V (see Figure 18) VDD=560 V, ID=9A, RG=4.7Ω, VGS=10V (see Figure 18) Min. 22 19 ns ns 46 19 ns ns 11 10 22 ns ns ns 3/13 STP10NK70Z - STP10NK70ZFP 2 Electrical characteristics Table 7. Source drain diode Symbol Parameter ISD ISDMNote 2 Source-drain Current Source-drain Current (pulsed) VSDNote 4 Forward on Voltage ISD=8.6 A, V GS=0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD=9A, di/dt = 100A/µs, VDD=35 V, Tj=150°C trr Qrr IRRM Table 8. Symbol BVGSO Note 6 Test Conditions Min. Typ. Max. Unit 8.6 34 A A 1.6 V 720 5.4 15 ns µC A Gate-source zener diode Parameter Gate-Source Breakdown Voltage Test Conditions Igs=±1mA (Open Drain) Min. 30 Typ. Max. Unit V (1) ISD ≤8.6 A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX (2) Pulse width limited by safe operating area (3) Limited only by maximum temperature allowed (4) Pulsed: pulse duration = 300µs, duty cycle 1.5% (5) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80%VDSS (6)The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 4/13 STP10NK70Z - STP10NK70ZFP 2.1 2 Electrical characteristics Electrical Characteristics (curves) Figure 1. Safe Operating Area for TO-220 Figure 2. Thermal Impedanc for TO-220 Figure 3. Safe Operating Area for TO-220FP Figure 4. Thermal Impedance for TO-220FP Figure 5. Output Characteristics Figure 6. Transfer Characteristics 5/13 STP10NK70Z - STP10NK70ZFP 2 Electrical characteristics Figure 7. Transconductance Figure 8. Static Drain-Source on Resistance Figure 9. Gate Charge vs Gate -Source Voltage Figure 11. Capacitance Variations Figure 10. Normalized Gate Threshold Voltage Figure 12. Normalized on Resistance vs vs Temperatute Temperature 6/13 STP10NK70Z - STP10NK70ZFP Figure 13. Source-drain Diode Forward Characteristics 2 Electrical characteristics Figure 14. Normalized BVDSS vs Temperature Figure 15. Maximum Avalanche Energy vs Temperature 7/13 3 Test circuits 3 STP10NK70Z - STP10NK70ZFP Test circuits Figure 16. Switching Times Test Circuit For Resistive Load Figure 17. Gate Charge Test Circuit Figure 18. Test Circuit For Indictive Load Switching and Diode Recovery Times Figure 20. Unclamped Inductive Load Test Circuit Figure 19. Unclamped Inductive Waveform 8/13 STP10NK70Z - STP10NK70ZFP 4 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/13 STP10NK70Z - STP10NK70ZFP 4 Package mechanical data TO-220 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 10/13 TYP 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 STP10NK70Z - STP10NK70ZFP 4 Package mechanical data TO-220FP MECHANICAL DATA mm. DIM. MIN. A 4.4 inch TYP MAX. MIN. TYP. 4.6 0.173 0.181 MAX. 0.106 B 2.5 2.7 0.098 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 .0385 0.417 L5 2.9 3.6 0.114 0.141 L6 15.9 16.4 0.626 0.645 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L7 L3 L6 F2 H G G1 F F1 L7 L2 L5 1 2 3 L4 11/13 STP10NK70Z - STP10NK70ZFP 5 Revision History 5 12/13 Revision History Date Revision 22-Aug-2005 2 Changes Inserted Ecopack indication STP10NK70Z - STP10NK70ZFP 5 Revision History Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 13/13