STP10NK50Z STF10NK50Z N-CHANNEL 500V - 0.55Ω - 9A TO-220 / TO-220FP Zener-Protected SuperMESH™MOSFET Table 1: General Features Figure 1: Package TYPE VDSS RDS(on) ID Pw STP10NK50Z STF10NK50Z 500 V 500 V < 0.7 Ω < 0.7 Ω 9A 9 A(*) 125 W 30 W ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.55 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. 3 1 TO-220 2 TO-220FP Figure 2: Internal Schematic Diagram APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC ■ LIGHTING Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STP10NK50Z P10NK50Z TO-220 TUBE STF10NK50Z F10NK50Z TO-220FP TUBE Rev. 2 September 2005 1/12 STP10NK50Z - STF10NK50Z Table 3: Absolute Maximum ratings Symbol Parameter Value TO-220 VDS VDGR VGS Unit TO-220FP Drain-source Voltage (VGS = 0) 500 V Drain-gate Voltage (RGS = 20 kΩ) 500 V Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 9 9 (*) A ID Drain Current (continuous) at TC = 100°C 5.7 5.7(*) A Drain Current (pulsed) 36 36(*) A Total Dissipation at TC = 25°C 125 30 W 0.24 W/°C IDM ( ) PTOT Derating Factor VESD(G-S) dv/dt (1) 1 Gate source ESD(HBM-C=100pF, R=1.5KΩ) Peak Diode Recovery voltage slope VISO Insulation Withstand Voltage (DC) Tj Tstg Operating Junction Temperature Storage Temperature 4000 V 4.5 V/ns -- 2500 -55 to 150 V °C ( ) Pulse width limited by safe operating area (1) ISD ≤ 9 A, di/dt ≤200A/µs, VDD ≤ 400 (*) Limited only by maximum temperature allowed Table 4: Thermal Data TO-220 TO-220FP Rthj-case Thermal Resistance Junction-case Max 1 Rthj-amb Thermal Resistance Junction-ambient Max 62.5 4.2 °C/W °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Table 5: Avalanche Characteristics Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 9 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, I D = IAR, VDD = 50 V) 230 mJ Table 6: Gate-Source Zener Diode Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Min. Igs=± 1mA (Open Drain) 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/12 STP10NK50Z - STF10NK50Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off Symbol V(BR)DSS Parameter Test Conditions Min. Typ. Max. 500 Unit Drain-source Breakdown Voltage I D = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 50 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20 V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, I D = 100 µA RDS(on) Static Drain-source On Resistance VGS = 10 V, I D = 4.5 A 3 V 3.75 4.5 V 0.55 0.7 Ω Typ. Max. Unit Table 8: Dynamic Symbol gfs (1) Parameter Test Conditions Min. Forward Transconductance VDS = 15 V, ID = 4.5 A Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, f = 1 MHz, VGS = 0 1219 159 40 pF pF pF Equivalent Output Capacitance VGS = 0V, VDS = 0V to 400 V 806 pF td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD = 250 V, ID = 4.5 A RG = 4.7Ω VGS = 10 V (see Figure 19) 19 17 43 15 ns ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 400 V, ID = 9 A, VGS = 10 V (see Figure 22) 39.2 7.42 20.7 nC nC nC Ciss Coss Crss Coss eq. (3) S 7 Table 9: Source Drain Diode Symbol Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage I SD = 9 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 9 A, di/dt = 100 A/µs VDD = 35 V, T j = 25°C (see Figure 20) 268 1.83 13.7 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 9 A, di/dt = 100 A/µs VDD = 35 V, T j = 150°C (see Figure 20) 343 2.6 15.15 ns µC A trr Qrr IRRM trr Qrr IRRM Test Conditions Min. Typ. Max. Unit 9 36 A A 1.6 V Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/12 STP10NK50Z - STF10NK50Z Figure 3: Safe Operating Area For TO-220 Figure 6: Thermal Impedance For TO-220 Figure 4: Safe Operating Area For TO-220FP Figure 7: Thermal Impedance For TO-220FP Figure 5: Output Characteristics Figure 8: Transfer Characteristics 4/12 STP10NK50Z - STF10NK50Z Figure 9: Transconductance Figure 12: Static Drain-source On Resistance Figure 10: Gate Charge vs Gate-source Voltage Figure 13: Capacitance Variations Figure 11: Normalized Gate Threshold Voltage vs Temperature Figure 14: Normalized On Resistance vs Temperature 5/12 STP10NK50Z - STF10NK50Z Figure 15: Source-Drain Forward Characteristics Figure 16: Maximum Avalanche Energy vs Temperature 6/12 Figure 17: Normalized BVdss vs Temperature STP10NK50Z - STF10NK50Z Figure 18: Unclamped Inductive Load Test Circuit Figure 21: Unclamped Inductive Wafeform Figure 19: Switching Times Test Circuit For Resistive Load Figure 22: Gate Charge Test Circuit Unclamped Inductive Load Test Circuit Figure 20: Test Circuit For Inductive Load Switching and Diode Recovery Times 7/12 STP10NK50Z - STF10NK50Z In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 8/12 STP10NK50Z - STF10NK50Z TO-220 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 9/12 STP10NK50Z - STF10NK50Z TO-220FP MECHANICAL DATA mm. DIM. MIN. A 4.4 inch TYP MAX. MIN. TYP. 4.6 0.173 0.181 MAX. 0.106 B 2.5 2.7 0.098 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 .0385 0.417 L5 2.9 3.6 0.114 0.141 L6 15.9 16.4 0.626 0.645 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L7 L3 L6 F2 H G G1 F F1 L7 L2 10/12 L5 1 2 3 L4 STP10NK50Z - STF10NK50Z Table 10: Revision History Date Revision 01-Jul-2005 08-Sep-2005 1 2 Description of Changes First Release. Inserted Ecopak indication 11/12 STP10NK50Z - STF10NK50Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 12/12