NEC 23C256

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD23C256112A
NAND INTERFACE
256M-BIT MASK-PROGRAMMABLE ROM
Description
The µPD23C256112A is a 256 Mbit NAND interface programmable mask read-only memory that operates with a
single power supply. The memory organization consists of (512 + 16 (Redundancy)) bytes x 32 pages x 2,048 blocks.
The µPD23C256112A is a serial type mask ROM in which addresses and commands are input and data output
serially via the I/O pins.
The µPD23C256112A is packed in 48-pin PLASTIC TSOP(I).
Features
• Word organization
(33,554,432 + 1,048,576
Note
) words by 8 bits
• Page size
(512 + 16
Note
) by 8 bits
• Block size
(16,384 + 512
Note
) by 8 bits
Note Underlined parts are redundancy.
Caution Redundancy is not programmable parts and is fixed to all FFH.
• Operation mode
READ mode (1), READ mode (2), READ mode (3), RESET, STATUS READ, ID READ
• Operating supply voltage : VCC = 3.3 ± 0.3 V
• Access Time
Memory cell array to starting address
: 7 µs (MAX.)
Read cycle time
: 50 ns (MIN.)
/RE access time
: 35 ns (MAX.)
• Operating supply current
During read
: 30 mA (MAX.) (50 ns cycle operation)
During standby (CMOS) : 100 µA (MAX.)
Ordering Information
Part Number
Package
µPD23C256112AGY-xxx-MJH
48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
µPD23C256112AGY-xxx-MKH
48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
(xxx : ROM code suffix No.)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15902EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
©
2001
µPD23C256112A
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
[ µPD23C256112AGY-xxx-MJH ]
Marking Side
NC
NC
NC
IC
IC
GND
R, /B
/RE
/CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
/WE
IC
IC
IC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
I/O0 to I/O7
: Address Inputs / Command Inputs / Data Outputs
CLE
: Command Latch Enable Input
ALE
: Address Latch Enable Input
/WE
: Write Enable Input
/RE
: Read Enable Input
/CE
: Chip Enable Input
Note1
R, /B
: READY, /BUSY Output
VCC
: Supply voltage
Vss
: Ground
NC
IC
Note2
Note3
GND
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VCC
VSS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
: No connection
: Internal connection
: GND
Notes 1. This pin is an open-drain output pin. Therefore, a pull-up resistor is required when using this pin.
2. Some signals can be applied because this pin is not connected to the inside of the chip.
3. Leave this pin unconnected or connected to VSS.
Remark Refer to Package Drawings for the 1-pin index mark.
2
Data Sheet M15902EJ2V0DS
µPD23C256112A
48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
[ µPD23C256112AGY-xxx-MKH ]
Marking Side
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VCC
VSS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O0 to I/O7
: Address Inputs / Command Inputs / Data Outputs
CLE
: Command Latch Enable Input
ALE
: Address Latch Enable Input
/WE
: Write Enable Input
/RE
: Read Enable Input
/CE
: Chip Enable Input
Note1
R, /B
: READY, /BUSY Output
VCC
: Supply voltage
Vss
: Ground
NC
IC
Note2
Note3
GND
NC
NC
NC
IC
IC
GND
R, /B
/RE
/CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
/WE
IC
IC
IC
NC
NC
NC
: No connection
: Internal connection
: GND
Notes 1. This pin is an open-drain output pin. Therefore, a pull-up resistor is required when using this pin.
2. Some signals can be applied because this pin is not connected to the inside of the chip.
3. Leave this pin unconnected or connected to VSS.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15902EJ2V0DS
3
µPD23C256112A
Input / Output Pin Functions
Pin name
Input / Output
Input, Output
I/O0 to I/O7
(Address Inputs / Command
Inputs / Data Outputs)
Function
I/O port for address input, command input, and data output. I/O pins.
Input pin for signal for controlling loading of commands to command register in
device. By making this signal high level at the rising edge or falling edge of the /WE
signal, the data of the I/O0 to I/O7 pins is loaded to the command register as
commands.
CLE
(Command latch Enable
Input)
Input
ALE
(Address latch Enable
Input)
Input
Input pin for signal for controlling loading of address data to the address register in
the device. By making this signal high level at the rising edge or falling edge of the
/WE signal, the data of the I/O0 to I/O7 pins is loaded as address.
/WE
(Write Enable Input)
Input
Input pin for signal for loading the data from the I/O0 to I/O7 pins inside the device.
/RE
(Read Enable Input)
Input
Input pin for signal for serially outputting data. The output data of I/O0 to I/O7 is
determined after tREA from the falling edge of the /RE signal, and the internal address
counter is incremented by +1 at the rising edge of the /RE signal.
/CE
(Chip Enable Input)
Input
Input pin for device selection signal. During read, the standby mode is entered by
making this signal high level.
Output
Output pin for signal that notifies the internal operating status of the device to
external. This is an open-drain output signal. During read, Busy is output during
operation (R, /B = low level), and upon completion, Ready (R, /B = high level) is
automatically output.
R, /B
(READY, /BUSY Output)
4
Data Sheet M15902EJ2V0DS
µPD23C256112A
Block Diagram
I/O0
Dara Register Circuit
I/O2
I/O3
I/O4
I/O5
I/O6
Input / Output Buffer
I/O1
Status Register
Sense Amplifier
ID Register
Address
Register
Y-Selector
Command
Register
CLE
ALE
/WE
/RE
Vcc
Control Logic
/CE
READ Contorol Circuit
X-Decoder
I/O7
Memory Cell Matrix
READY/BUSY
Control Circuit
R, /B (Open-drain)
Vss
Data Sheet M15902EJ2V0DS
5
µPD23C256112A
Memory Area
1 Page = 528 Bytes
0
•
•
•
255 256
•
•
•
511
• 527
0
1
2
•
1 Block
= 32 Pages •
•
30
31
•
•
•
(A)
(B)
•
(C)
2,048 Blocks
= 65,536 Pages
•
•
•
•
•
65,533
65,534
65,535
512 Bytes
(Main memory)
16 Bytes
(Redundancy)
• The start address (SA) during read operation is specified divided into three areas using three types of read
commands.
In read mode (1), start address (SA) is set in area (A).
In read mode (2), start address (SA) is set in area (B).
In read mode (3), start address (SA) is set in area (C).
One page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy).
One block consists of 32 pages.
Caution The data of area (C) is redundancy. Redundancy is not programmable parts and is fixed to all FFH.
6
Data Sheet M15902EJ2V0DS
µPD23C256112A
Operation Modes
Command input, address input, and serial read are all performed from I/O pins, and the respective statuses are
controlled by the CLE, ALE, /WE, /RE, and /CE signals.
Command
input cycle
Address input cycle
Serial read cycle
CLE
/CE
/WE
ALE
/RE
I/O0 to I/O7
High-Z
High-Z
High-Z
Busy
R, /B
Operation mode
Mode
CLE
ALE
/CE
/WE
/RE
Command input cycle
H
L
L
H
Address input cycle
L
H
L
H
Serial read cycle
L
L
L
H
CLE
ALE
/CE
/WE
/RE
I/O0 to I/O7
Data output
L
L
L
H
L
Data output
Output High-Z
L
L
L
H
H
High-Z
Standby
L
L
H
H
×
High-Z
Operation mode during serial read
Mode
Remark × : VIH or VIL
Data Sheet M15902EJ2V0DS
7
µPD23C256112A
Operation Commands
The following six operation settings are possible by inputting commands from I/O pins.
Command
HEX
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Read mode(1)
00H
L
L
L
L
L
L
L
L
Read mode(2)
01H
L
L
L
L
L
L
L
H
Read mode(3)
50H
L
H
L
H
L
L
L
L
Reset Note2
FFH
H
H
H
H
H
H
H
H
Status read
70H
L
H
H
H
L
L
L
L
90H
H
L
L
H
L
L
L
L
Note1
ID read
Note3
Command receivable
during Busy
Notes 1. The data output in read mode (3) is all FFH.
2. The only command that can be executed when the device is Busy is the reset command. Do not set any
of the other commands while the device is Busy.
3. For ID read, input “00H” during the first address cycle after setting a command.
I/O Pin Correspondence Table during Address Input Cycle (Address Setting)
(1) When 00H or 01H command is set [Read mode (1), Read mode (2)]
Command
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st address cycle
A7
A6
A5
A4
A3
A2
A1
A0
2nd address cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd address cycle
A24
A23
A22
A21
A20
A19
A18
A17
(2) When 50H command is set [Read mode (3)]
Command
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st address cycle
×
×
×
×
A3
A2
A1
A0
2nd address cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd address cycle
A24
A23
A22
A21
A20
A19
A18
A17
Remarks 1. A0 to A24 are internal addresses.
2. Internal address A8 is set internally with command 00H or 01H.
3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address
cycle are VIH or VIL.
8
Data Sheet M15902EJ2V0DS
µPD23C256112A
Usage Cautions
(1) Rated operation
Operation using timing other than shown in the timing charts is not guaranteed.
(2) Commands that can be input
The only commands that can be input are 00H, 01H, 50H, 70H, 90H, and FFH. Do not input any other commands.
If other commands are input, the subsequent operation is not guaranteed.
(3) Command limitations during Busy period
Do not input commands other than the reset command (FFH) during the Busy period. If a command is input
during the Busy period, the subsequent operation is not guaranteed.
(4) Cautions regarding /RE clock
• Following the last /RE clock, do not input the /RE clock until the R, /B pin changes from Busy to Ready.
• Do not input the /RE clock other than during data output.
(5) Cautions upon power application
Since the state of the device is undetermined upon power on, input high level to the /CE pin and execute the reset
command following power on.
(6) Cautions during read mode
• Perform address input immediately following command input. If address input is done without performing
command input first, the correct data cannot be output because the operation mode is undetermined.
• To execute the read mode after the read mode has been stopped with the reset command (FFH) and /CE, input
again a command and address.
(7) Busy output following access of last address in page in read mode
After the access to the last address in a page, if the delay (tRHCH) from /RE to /CE is 30 ns or less, the Ready
status is maintained and Busy is not output by keeping /CE high level for a set period (tCEH).
tCEH
/CE
tRHCH
/RE
526
527
R, /B
Data Sheet M15902EJ2V0DS
9
µPD23C256112A
Electrical Specifications
Absolute Maximum Ratings
Parameter
Rating
Unit
VCC
–0.5 to +4.6
V
VI
–0.3 to VCC+0.3
V
Input / Output voltage
VI/O
–0.3 to VCC+0.3 ( ≤ 4.6)
V
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–65 to +150
°C
Supply voltage
Input voltage
Symbol
Condition
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (TA = 25°C)
Parameter
Symbol
Input capacitance
CI
Output capacitance
CO
Test condition
MIN.
TYP.
f = 1 MHz
MAX.
Unit
10
pF
10
pF
MAX.
Unit
DC Characteristics (TA = 0 to 70°C, VCC = 3.3 ± 0.3 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
High level input voltage
VIH
2.0
VCC + 0.3
V
Low level input voltage
VIL
–0.3
+0.8
V
High level output voltage
VOH
IOH = –400 µA
Low level output voltage
VOL
IOL = 2.1 mA
0.4
V
2.4
V
Input leakage current
ILI
VI = 0 V to VCC
±10
µA
Output leakage current
ILO
VO = 0 V to VCC
±10
µA
Power supply current in read
ICCO1
/CE = VIL, IOUT = 0 mA, tCYCLE = 50 ns
30
mA
Power supply current
in command input
ICCO3
tCYCLE = 50 ns
30
mA
Power supply current
in address input
ICCO5
tCYCLE = 50 ns
30
mA
Standby current (TTL)
ICCS1
/CE = VIH
1
mA
Standby current (CMOS)
ICCS2
/CE = VCC – 0.2 V
100
µA
(R, /B) pin output current
IOL(R, /B)
10
VOL = 0.4 V
Data Sheet M15902EJ2V0DS
8
mA
µPD23C256112A
AC Characteristics (TA = 0 to 70°C, VCC = 3.3 ± 0.3 V)
Parameter
Symbol
MIN
CLE setup time
tCLS
0
ns
CLE hold time
tCLH
10
ns
/CE setup time
tCS
0
ns
/CE hold time
tCH
10
ns
Write pulse width
tWP
25
ns
ALE setup time
tALS
0
ns
ALE hold time
tALH
10
ns
Data setup time
tDS
20
ns
Data hold time
tDH
10
ns
Write cycle time
tWC
50
ns
/WE high hold time
tWH
15
ns
Ready to /RE falling edge
tRR
20
ns
Read pulse width
tRP
35
ns
Read cycle time
tRC
50
ns
/RE access time (serial data access)
tREA
/CE high hold time for last address in serial read cycle
tCEH
/RE access time (ID read )
tREAID
/RE high to output High-Z
tRHZ
/CE high to output High-Z
tCHZ
/RE high hold time
tREH
15
ns
tIR
0
ns
Output High-Z to /RE falling edge
TYP.
MAX.
35
100
10
Unit
ns
ns
35
ns
30
ns
20
ns
/RE access time (status read)
tRSTO
35
ns
/CE access time (status read)
tCSTO
45
ns
/WE high to /CE low
tWHC
30
ns
/WE high to /RE low
tWHR
30
ns
ALE low to /RE low (ID read)
tAR1
100
ns
/CE low to /RE low (ID read)
tCR
100
ns
Memory cell array to starting address
tR
7
µs
/WE high to Busy
tWB
200
ns
ALE low to /RE low (read cycle)
tAR2
/RE last clock rising edge to Busy (in sequential read)
tRB
/CE high to Ready (when interrupted by /CE in read mode)
Device reset time
tCRY
Note
tRST
50
ns
200
ns
1
µs
6
µs
Note tCRY (time from /CE high to Ready) depends on the pull-up resister of the R, /B output pin.
Data Sheet M15902EJ2V0DS
11
µPD23C256112A
AC Test Conditions
Input waveform (Rise / Fall Time ≤ 5 ns)
1.5 V
Test points
1.5 V
1.5 V
Test points
1.5 V
Output waveform
Output load
1 TTL + 100 pF
12
Data Sheet M15902EJ2V0DS
Read Cycle Timing Chart (1)
(In case of read mode (1))
CLE
tCLS
tCLH
tCS
tCH
/CE
tWC
tCS
tCEH
tR
/WE
tALH
tALS
tWP
tALH
tWH
tCRY
Data Sheet M15902EJ2V0DS
tAR2
tCHZ
ALE
tRR
tRC
tRC
/RE
tRP
tWB
tDS
I/O0 to I/O7
00H
tDH
tDS
tDS
A0 to A7
tDH
tREH
A9 to A16
tDH
tRHZ
tRHZ
tDS
A17 to A24
High-Z
tDH
DOUT
DOUT
N
tREA
N+1
527
tRB
Output page M data
Remarks 1. Start address (SA) specification when read is performed with command 00H. N: 0 to 255
2. Then time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R,/B output pin.
13
µPD23C256112A
R, /B
Access
page M
High-Z
DOUT
14
Read Cycle Timing Chart (2)
(In case of read mode (2))
CLE
tCLS
tCLH
tCS
tCH
/CE
tWC
tCS
tCEH
tR
/WE
tALH
tALS
tWP
tALH
tWH
tCRY
Data Sheet M15902EJ2V0DS
tAR2
tCHZ
ALE
tRR
tRC
tRC
/RE
tRP
tWB
tDS
I/O0 to I/O7
01H
tDH
tDS
tDS
tDH
A9 to A16
tDH
tRHZ
tRHZ
High-Z
A0 to A7
tREH
tDS
A17 to A24
tDH
DOUT
DOUT
256+N
tREA
256+N+1
High-Z
527
tRB
Output page M data
Remarks 1. Start address (SA) specification when read is performed with command 01H. N: 0 to 255
2. Then time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R,/B output pin.
µPD23C256112A
R, /B
Access
page M
DOUT
Read Cycle Timing Chart (3)
(In case of read mode (3))
CLE
tCLS
tCLH
tCS
tCH
/CE
tWC
tCS
tCEH
tR
/WE
tALH
tALS
tWP
tWH
tALH
tCRY
tAR2
Data Sheet M15902EJ2V0DS
tCHZ
ALE
tRR
tRC
tRC
/RE
tRP
tWB
tDS
I/O0 to I/O7
50H
tDH
tDS
tDS
A0 to A3
tDH
tREH
tRHZ
tDS
A9 to A16
tDH
A17 to A24
High-Z
tDH
tRHZ
DOUT
DOUT
512+N
tREA
512+N+1
DOUT
High-Z
527
tRB
Access
page M
Remarks 1.
2.
3.
4.
Output page M data
Start address (SA) specification when read is performed with command 50H. N: 0 to 15
The start address of area C (redundancy data) is specified with A0 to A3 during the 1st address cycle. At this time, A4 to A7 are Don't Care.
The time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R, /B output pin.
The data that is output is FFH.
15
µPD23C256112A
R, /B
16
Read Cycle Timing Chart (4)
(When /CE is made high level in the read mode)
CLE
tCLS
tCLH
tCS
tCH
/CE
tR
tWC
tCS
/WE
tALH
tALS
tALH
tWH
tWP
tAR2
Data Sheet M15902EJ2V0DS
tCHZ
ALE
tRC
tRC
tRR
/RE
tRP
tWB
tDS
I/O0 to I/O7
tDH
Command
input
Address
input
tDH
tRHZ
tDS
tDS
tDS
Address
input
tDH
tRHZ
tREH
Address
input
High-Z
tDH
DOUT
DOUT
DOUT
N
tREA
N+1
N+2
Access
page M
Remark If /CE is made high level during the read cycle, the read operation until that time is cancelled.
Therefore, to perform read again, execute a new command and new address input.
µPD23C256112A
R, /B
High-Z
µPD23C256112A
Sequential Read
In read modes (1), (2), and (3), when a command (00H, 01H, 50H) is input and an address specified, if it is in the
block that includes the address that was specified first, the address is automatically incremented and the read
operation is continuously performed until the last address in the same block, by inputting the /RE clock. At this time, a
Busy period (tR) occurs after the last address is accessed in a page.
Note
Command
input Address
Page M
data output
input
00H
Command
Output of in last page input
Address
in block
input
00H
Page M+1
data output
01H
01H
50H
50H
tR
tR
tR
tR
Busy
Busy
Busy
Busy
tCRY Note
Data output
tR
R, /B
Busy
Busy
In same block
(Maximum of 32 pages)
Note To perform read again after reading the 527th byte of data of the last page of block, stop the read operation once,
and then restart the read operation by inputting again the read command and an address.
Relationship Between Command and Start Address (SA) during Sequential Read
(A)
0
(B)
256
(C)
512
527
(A)
0
(B)
256
(A)
(C)
512
527
0
(B)
256
(C)
512
527
SA
SA
SA
1 block
= 32 pages
Sequential read mode (1)
(When "00H" command is input)
Sequential read mode (2)
(When "01H" command is input)
Sequential read mode (3)Note
(When "50H" command is input)
Note When the "50H" command is set, only the (C) area (redundancy data part) is continuously read.
• When the “00H” command is set, the start address (SA) is set to area (A).
• When the “01H” command is set, the start address (SA) is set to area (B).
• When the “50H” command is set, the start address (SA) is set to area (C).
Data Sheet M15902EJ2V0DS
17
18
Sequential Read Cycle Timing Chart (1)
(In case of read mode (1))
CLE
tCLS
tCLH
tCS
tCH
/CE
tWC
tCS
tR
/WE
tALH
tALS
tWP
tALH
tWH
tAR2
Data Sheet M15902EJ2V0DS
ALE
tRR
tRC
tRC
/RE
tR
tRP
tWB
tDS
I/O0 to I/O7
00H
tDH
tDS
tDS
A0 to A7
tDH
tRR
tREH
tRHZ
tDS
A9 to A16
A17 to A24
tDH
tDH
High-Z
DOUT
DOUT
N
tREA
N+1
High-Z
DOUT
DOUT
High-Z
DOUT
0
527
tRB
Output page M data
Remark Start address (SA) specification when read is performed with command 00H. N: 0 to 255
Access
page M+1
Output page
M+1 data
µPD23C256112A
R, /B
Access
page M
1
Sequential Read Cycle Timing Chart (2)
(In case of read mode (2))
CLE
tCLS
tCLH
tCS
tCH
/CE
tWC
tCS
tR
/WE
tALH
tALS
tWP
tALH
tWH
Data Sheet M15902EJ2V0DS
tAR2
ALE
tRR
tRC
tRC
/RE
tR
tRP
tWB
tDS
I/O0 to I/O7
01H
tDH
tDS
tDS
A0 to A7
tDH
tRR
tREH
tRHZ
tDS
A9 to A16
A17 to A24
tDH
tDH
High-Z
DOUT
DOUT
256+N
tREA
256+N+1
High-Z
DOUT
DOUT
High-Z
DOUT
0
527
tRB
Remark Start address (SA) specification when read is performed with command 01H. N: 0 to 255
Output page M data
Access
page M+1
Output page
M+1 data
19
µPD23C256112A
R, /B
Access
page M
1
20
Sequential Read Cycle Timing Chart (3)
(In case of read mode (3))
CLE
tCLS
tCLH
tCS
tCH
/CE
tWC
tCS
tR
/WE
tALH
tALS
tWP
tALH
tWH
Data Sheet M15902EJ2V0DS
tAR2
ALE
tRR
tRC
tRC
/RE
tR
tRP
tWB
tDS
I/O0 to I/O7
tDH
tDS
tDS
tRHZ
tDS
High-Z
50H
A0 to A3
tDH
A9 to A16
tDH
tRR
tREH
A17 to A24
tDH
DOUT
DOUT
512+N
tREA
512+N+1
High-Z
High-Z
DOUT
527
DOUT
DOUT
512
513
tRB
Access
page M
Output page M data
Remark Start address (SA) specification when read is performed with command 50H. N: 0 to 15
Access
page M+1
Output page
M+1 data
µPD23C256112A
R, /B
µPD23C256112A
Status Read
Status information can be output from the I/O pins with the /RE clock following input of the 70H command. Status
read is a function to recognize the status of the device from external.
tCLS
CLE
tCLS
tCLH
tCS
tCH
/CE
tCSTO
/WE
tCHZ
tWHC
tWP
tRHZ
/RE
tWHR
tDS
I/O0 to I/O7
tDH
tIR
High-Z
70H
Status
High-Z
tRSTO
R, /B
Ready
Status
Status output data Note
I/O0
Ready / Busy
0/1
I/O1
Not used
0
I/O2
Not used
0
I/O3
Not used
0
I/O4
Not used
0
I/O5
Not used
0
I/O6
Ready / Busy
1/0
I/O7
Write protect
0
Note Use the status read command only during Ready.
Data Sheet M15902EJ2V0DS
21
µPD23C256112A
ID Read
To recognize the ID code (maker code / device code) of this device in a system, execute the ID read command.
The ID code can be read with the following timing.
tCLS
CLE
tCLS
tCLH
tCS
tCH
/CE
tCH
tCS
tCR
/WE
tALH
tALS tWP
tALH
tAR1
ALE
tRC
/RE
tRP
tDS
tDS
tDH
tREH
tDH
Maker code
90H
I/O0 to I/O7
00H
High-Z
Device code
10H
58H
tREAID
tREAID
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
HEX
Maker code
L
L
L
H
L
L
L
L
10H
Device code
L
H
L
H
H
L
L
L
58H
Cautions 1. If the /RE clock is input after the maker code and device code are output, the output data is not
guaranteed. Therefore, do not input the /RE clock following device code output.
2. Do not input an address other than 00H after setting the ID read command (90H). If an address other
than 00H is input, the data following /RE clock input is not guaranteed.
22
Data Sheet M15902EJ2V0DS
µPD23C256112A
Reset Cycle Timing Chart
CLE
tCLS
tCLH
tCS
tCH
/CE
/WE
tRST
tALS
tWP
tALH
ALE
tDS
I/O0 to I/O7
tDH
FFH
tWB
R, /B
Data Sheet M15902EJ2V0DS
23
µPD23C256112A
Package Drawings
48-PIN PLASTIC TSOP(I) (12x18)
1
detail of lead end
48
F
G
R
Q
24
L
25
S
E
P
I
A
J
C
S
D
K
N
B
M M
S
NOTES
ITEM
MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
12.0±0.1
B
0.45 MAX.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
C
0.5 (T.P.)
D
0.22±0.05
E
0.1±0.05
F
1.2 MAX.
G
1.0±0.05
I
16.4±0.1
J
0.8±0.2
K
0.145±0.05
L
0.5
M
0.10
N
0.10
P
18.0±0.2
Q
3° +5°
−3°
R
S
0.25
0.60±0.15
S48GY-50-MJH1-1
24
Data Sheet M15902EJ2V0DS
µPD23C256112A
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
E
S
L
Q
R
24
G
25
F
K
N
S
D
S
I
J
M M
B
C
A
P
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
ITEM
A
MILLIMETERS
12.0±0.1
B
0.45 MAX.
C
0.5 (T.P.)
D
0.22±0.05
E
0.1±0.05
F
1.2 MAX.
G
1.0±0.05
I
16.4±0.1
J
0.8±0.2
K
0.145±0.05
L
0.5
M
0.10
N
0.10
P
18.0±0.2
Q
3° +5°
−3°
R
0.25
S
0.60±0.15
S48GY-50-MKH1-1
Data Sheet M15902EJ2V0DS
25
µPD23C256112A
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD23C256112A.
Types of Surface Mount Device
µPD23C256112AGY-MJH : 48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
µPD23C256112AGY-MKH : 48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
26
Data Sheet M15902EJ2V0DS
µPD23C256112A
Revision History
Edition/
Date
2nd edition/
This
edition
p.1
Page
Previous
edition
p.1
Type of
revision
Modification
Location
Features
Sep. 2002
Description
(Previous edition → This edition)
Read cycle time:
50ns(MAX.) → 50ns(MIN.)
p.4
p.4
Modification
Input/Output Pin Functions
Signal Descriptions→Input/Output Pin Functions
p.9
p.23
Modification
Usage Cautions
Moved in front of Electrical Specifications page
Data Sheet M15902EJ2V0DS
27
µPD23C256112A
[ MEMO ]
28
Data Sheet M15902EJ2V0DS
µPD23C256112A
[ MEMO ]
Data Sheet M15902EJ2V0DS
29
µPD23C256112A
[ MEMO ]
30
Data Sheet M15902EJ2V0DS
µPD23C256112A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M15902EJ2V0DS
31
µPD23C256112A
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4