NTE7156 Integrated Circuit DC–Coupled Vertical Deflection Circuit Description: The NTE7156 is a power circuit in a 9–Lead SIP type package designed for use in 90° and 110° color deflection systems for field frequencies of 50Hz to 120Hz. This device provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system. Features: D Few External Components D Highly Efficient Fully DC–Coupled Vertical Output Bridge Circuit D Vertical Flyback Switch D Guard Circuit D Protection Aaginst: – Short–Circuit of the Output Pins (7 and 4) – Short–Circuit of the Output Pins to VP D Temperature Protection D High EMC Immunity Because of Common Mode Inputs D A Guard Signal in Zoom Mode Absolute Maximum Ratings: DC Supply Supply Voltage, VP Non–Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Flyback Supply Voltage, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Note 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V Vertical Circuit Output Current (Peak–to–Peak Value, Note 2), IO(P–P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A Output Voltage (Pin7), VO(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52V Note 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62V Flyback Switch Peak Output Current, IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15A Thermal Data Virtual Junction Temperature, TVJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20° to +75°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Thermal Resistance, Virtual Junction–to–Ambient, RthVJ–C . . . . . . . . . . . . . . . . . . . . . . . . . . . 40K/W Thermal Resistance, Virtual Junction–to–Case, RthVJ–A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4K/W Short–Circuit Time (Note 3), tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Hour Note 1. A flyback supply voltage of > 50V up to 60V is allowed in application. A 22–nF capacititor in series with a 22Ω resistor (depending on IO and the inductance of the coil) has to be connected between Pin7 and GND. The decoupling capacitor of VFB has to be connected between Pin6 and Pin3. This supply voltage line must have a resistance of 33Ω. Note 2. IO maximum determined by current protection. Note 3. Up to VP = 18V. Electrical Characteristics: (VP = 17.5V, TA = +25°C, VFB = 45V, fi = 50Hz, II(sb) = 400µA unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit DC Supply Operating Supply Voltage VP 9 – 25 V Flyback Supply Voltage VFB VP – 50 V VP – 60 V – 30 55 mA 19.8 – – V Note 1 Supply Current IP No Load, No Signal Output Voltage Swing (Scan) VO Idiff = 0.6mA(P–P), Vdiff = 1.8V(P–P), IO = 3A(P–P) Linearity Error LE IO = 3A(P–P), Note 4 – 1 3 % IO = 50mA(P–P), Note 4 – 1 3 % Vertical Circuit Output Voltage Swing (Flyback) VO(A) – VO(B) VO Idiff = 0.3mA, IO = 1.5A – 39 – V Forward Voltage of the Internal Efficiency Diode (VO(A) – VFB) VDF IO = –1.5A, Idiff = 0.3mA – – 1.5 V Output Offset Current |IOS| Idiff = 0, II(sb) = 50µA to 500µA – – 30 mA Idiff = 0 – – 72 µV/K Offset Voltage at the Input of the Feedback Amplifier (VI(fb) – VO(B)) ∆VOS T DC Output Voltage VO(A) Idiff = 0, Note 5 – 8 – V Open Loop Voltage Gain (V7–4/V1–2) GVO Note 6, Note 7 – 80 – dB Note 6 – 80 – dB – 0 – dB – 40 – Hz Open Loop Voltage Gain (V7–4/V9–4, V1–2 = 0) Voltage Ratio V1–2/V9–4 VR Frequency Response (–3dB) fres Current Gain (IO/Idiff) GI – 5000 – ∆GC T – – 10–4 K Signal Bias Current II(sb) 50 400 500 µA Flyback Supply Current IFB During Scan – – 100 µA Note 9 – 80 – dB – 2.7 – V Current Gain Drift as a Function of Temperature Open Loop, Note 8 Power Supply Ripple Rejection PSRR DC Input Voltage VI(DC) Common Mode Input Voltage VI(CM) II(sb) = 0 0 – 1.6 V Ibias II(sb) = 0 – 0.1 0.5 µA ∆II(sub) = 300µA(P–P), fi = 50Hz, Idiff = 0 – 0.2 – mA Not Active, VO(guard) = 0V – – 50 µA 1.0 – 2.5 mA 4.6 – 5.5 V – – 40 V Input Bias Current Common Mode Output Current IO(CM) Guard Circuit Output Current IO Active, VO(guard) = 3.6V Output Voltage on Pin8 Allowable Voltage on Pin8 VO(guard) IO = 100µA Maximum Leakage Current = 10µA Notes: Note 1. A flyback supply voltage of > 50V up to 60V is allowed in application. A 22–nF capacititor in series with a 22Ω resistor (depending on IO and the inductance of the coil) has to be connected between Pin7 and GND. The decoupling capacitor of VFB has to be connected between Pin6 and Pin3. This supply voltage line must have a resistance of 33Ω. Note 4. The linearity error is measured without S–correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal I4 – I7 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and linearity error for not adjacent blocks (LENAB) are given below: LEAB = ak – a(k + 1) – amin a ; LEAB = max aavg aavg Note 5. Referenced to VP. Note 6. The V values within formulae relate to voltages at or across relative pin numbers, i.e. V7–4/V1–2 = voltage value across Pin7 and Pin4 divided by voltage value across Pin1 and Pin2. Note 7. V9–4 AC short–circuited. Note 8. Frequency response V7–4/V9–4 is equal to frequency response V7–4/V1–2. Note 9. At V(ripple) = 500mV eff; measured across RM; fi = 50Hz. Pin Connection Diagram (Front View) 9 8 7 6 5 4 3 2 1 VI(fb) VO(guard) VO(A) VFB GND VO(B) VP Idrive(neg) Idrive(pos) .945 (24.0) Max .788 (20.0) Max .173 (4.4) Seating Plane .130 (3.25) R .472 (12.0) 1 9 .079 (2.0) .100 (2.54) .663 (16.85) .017 (0.43)