NTE7162 Integrated Circuit DC−Coupled Vertical Deflection and East−West Output Circuit Description: The NTE7162 is a power circuit in a 13−Lead Staggered SIP type package designed for use in 90° and 110° color deflection systems for field frequencies of 50Hz to 120Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly effecient class G system and an East− West driver for sinking the diode modulator current. Features: D Few External Components D Highly Efficient Fully DC−Coupled Vertical Output Bridge Circuit D Vertical Flyback Switch D Guard Circuit D Protection Against: Short−Circuit of the Output Pins Short−Circuit of the Output Pins to VP D High EMC Immunity due to Common Mode Inputs D Temperature Protectection D East−West Output Stge with One Single Conversion Resistor Absolute Maximum Ratings: Supply Voltage, VP Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Non−Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Flyback Supply Voltage, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Flyback Supply Voltage (Note 1), VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V Output Current (Peak−to−Peak Value, Note 2), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A Output Voltage (Pin9), VO(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52V Output Voltage (Pin9, Note 1), VO(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52V Peak Output Current, IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5A Output Voltage (IO(sink) = 10µA, Note 3), VO(sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Output Current (VO(sink) = 2V, Note 3), IO(sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Note 1. A flyback supply voltage of > 50V up to 60V i allowed in application. A 220nF capacitor in series with a 22Ω resistor (depending on IO and the inductance of the coil) has to be connected between Pin9 and GND. The decoupling capacitor of VFB has to be connected between Pin8 and Pin4. The supply voltage line must have a resistance of 33Ω. Note 2. IO maximum determined by current protection. Note 3. The operating area is limited by a straight line between the points VO(sink) = 40V; IO(sink) = 10µA and VO(sink) = 2V; IO(sink) = 500mA. Absolute Maximum Ratings (Cont’d): Virtual Junction Temperature, TVJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25° to +75°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C Thermal Resistance, Virtual Junction−to−Case, RthVJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4K/W Thermal Resistance, Virtual Junction−to−Ambient (In Free Air), RthVJA . . . . . . . . . . . . . . . . . 40K/W Short−Circuiting Time (Note 4), tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Hour Note 4. Up to VP = 10V. Electrical Characteristics: (VP = 17.5V, VFB = 45V, VO(sink) = 20V, fi = 50Hz, II(sb) = 400µA, TA = +25°C unless otherwise specified) Parameter DC Supply Operating Supply Voltage Flyback Supply Voltage Symbol Test Conditions VP VFB IP Note 1 No Signal, No Load Min Typ Max Unit 9 VP − − − − − 30 25 50 60 55 V V V mA 19.8 − − V − − − 1 1 39 3 3 − % % V Supply Current Vertical Circuit Output Voltage Swing (Scan) VO Linearity Error LE Output Voltage Swing (Flyback) VO(A) − VO(B) Forward Voltage of the Internal Effeciency Diode (VO(A) − VFB) Output Offset Current Offset Voltage at the Input of the Feedback Amplifier VI(fb) = VO(B) Output Offset Voltag as a Function of Temperature DC Output Voltage Open Loop Voltage Gain V9−5/V1−2 V9−5/V3−5, V1−2 = 0 VO Idiff = 0.6mA (Peak−to−Peak), Vdiff = 1.8V (Peak−to−Peak), IO = 3A (Peak−to−Peak) IO = 3A (Peak−to−Peak), Note 5 IO = 50mA (Peak−to−Peak), Note 5 Idiff = 0.3mA, IO = 1.5A VDF IO = −1.5A, Idiff = 0.3mA − − 1.5 V Idiff = 0, II(sb) = 50µA to 500µA Idiff = 0, II(sb) = 50µA to 500µA − − − − 30 18 mA mV Idiff = 0 − − 72 µV/K Idiff = 0, Note 6 − 8 − V Note 7, Note 8 Note 7 − − 80 80 − − dB dB |IOS| |VOS| ∆VOS T VO(A) GV Note 1. A flyback supply voltage of > 50V up to 60V i allowed in application. A 220nF capacitor in series with a 22Ω resistor (depending on IO and the inductance of the coil) has to be connected between Pin9 and GND. The decoupling capacitor of VFB has to be connected between Pin8 and Pin4. The supply voltage line must have a resistance of 33Ω. Note 5. The linearity error is measured without S−correction and based on the same measurement priinciple as performed on the screen. The measuring method is as follows: Divide the output signal I5 − I9 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. measure the value of two succeeding parts called one block starting with 2 and 3 (block 1) and ending with 20 an 21 (block 10). Thus part 1 and 22 are unused. The equations for lineariy error for adjacent blocks (LEAB) and linearity error for not adjacent blocks (LENAB) are given below: ak − a(k + 1) amax − amin LEAB = ; LENAB = aavg aavg Note 6. Referenced to VP. Note 7. The V values within formulae relate to voltages at or across the relative pin numbers, i.e. V9−5/V1−2 = voltage value across Pin9 and Pin5 divided by voltage value across Pin1 and Pin2. Note 8. V3−5 AC short−circuited. Electrical Characteristics Cont’d): Parameter (VP = 17.5V, VFB = 45V, VO(sink) = 20V, fi = 50Hz, II(sb) = 400µA, TA = +25°C unless otherwise specified) Symbol Voltage Ratio V1−2/V3−5 Frequency Response (−3dB) Current Gain (IO/Idiff) Current Gain as a Function of Temperature Signal Bias Current Flyback Supply Current Power Supply Ripple Rejection DC Voltage at the Input Common Mode Input Voltage Input Bias Current Common Mode Output Current II(sb) IFB PSRR VI(DC) VI(CM) Ibias IO(CM) East−West Amplifier Saturation Voltage Open Loop Voltage Gain (V11/V12) Frequency Response (−3dB) Linearity Error VO(sink) GV fres LE Input Bias Current (Pin12) DC Input Voltage Offset Voltage Set Current Maximum Allowed Voltage at Pin13 Guard Circuit Output Current Output Voltage Allowable Voltage on Pin10 VR fres GI ∆GI T Test Conditions Note 9 During Scan Note 10 II(sb) = 0 II(sb) = 0 ∆II(sb) = 300µA (Peak−to−Peak), fi = 50Hz, Idiff = 0 IO(sink) = 500mA, II(corr) = 0µA, Note 11 VO(sink) = 3V VO(sink) = 10V, Note 5 Ibias VI(DC) Iset V13−7 IO VO(guard) Not Active, VO(guard) = 0V Active, VO(guard) = 3.6V IO = 100µA Maximum Leakage Current = 10µA Min Typ Max Unit − − − − 0 40 5000 − − − − 10−4 dB Hz 50 − − − 0 − − 400 − 80 2.7 − 0.1 0.2 500 100 − − 1.6 0.5 − µA µA dB V V µA mA − − − − − − − − − 2.0 47 4000 − − − 1 1 − 2.5 − − 1 0.5 2 − − 0.3 V dB Hz % % µA V mA V − 1.0 4.6 − − − − − 50 2.5 5.5 40 µA mA V V /K Note 5. The linearity error is measured without S−correction and based on the same measurement priinciple as performed on the screen. The measuring method is as follows: Divide the output signal I5 − I9 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. measure the value of two succeeding parts called one block starting with 2 and 3 (block 1) and ending with 20 an 21 (block 10). Thus part 1 and 22 are unused. The equations for lineariy error for adjacent blocks (LEAB) and linearity error for not adjacent blocks (LENAB) are given below: ak − a(k + 1) amax − amin LEAB = ; LENAB = aavg aavg Note 9. Frequency response V9−5/V3−5 is equal to frequency response V9−5/V1−2. Note10. At V(ripple) = 500mV eff; measured across RM; fi = 50Hz. Note 11. The output Pin11 requires a capacitor with a minimum value of 68nF. Pin Connection Diagram (Front View) 13 II (set) 12 II (corr) 11 VO (sink) 10 VO (guard) 9 Output Voltage A 8 VFB 7 GND 6 N.C. 5 Output Voltage B 4 VP 3 Feedback Voltage Input 2 Idrive (neg) 1 Idrive (pos) .944 (24.0) Max .173 (4.4) .780 (19.8) .127 3.25 1 .472 (12.0) .640 (16.25) 13 .460 (11.7) .134 (3.4) .169 (4.3) .200 (5.08)