OKI Semiconductor MSM5416258B Technical Information 262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5416258B is a 262,144-word x 16-bit dynamic RAM fabricated in OKI's CMOS silicon gate technology. The MSM5416258B achieves high integration,high-speed operation,and low-power consumption due to quadruple polysilicon double metal CMOS. The MSM5416258B is available in a 40-pin plastic SOJ. FEATURES • 262,144-word by 16-bit configuration • Single 5V power supply, ±10% tolerance • Input :TTL compatible • Output :TTL compatible, 3-state • Refresh : 512 cycles/8ms • Fast page mode with EDO,read modify write capability • Byte wide control: 2 CAS control • CAS before RAS refresh, Hidden refresh, RAS only refresh capability • Package : 40-Pin 400 mil plastic SOJ (SOJ40-P-400) (Product : MSM5416258B-xxJS) xx : indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family Cycle Time (Min.) tCAC tOEA Power Dissipation tRC tHPC 9ns 48ns 12ns 1485mW 9ns 9ns 55ns 13ns 1458mW 10ns 10ns 60ns 13ns 1430mW tRAC tAA MSM5416258B-28 28ns 15ns 9ns MSM5416258B-30 30ns 16ns MSM5416258B-35 35ns 19ns PIN CONFIGURATION ( TOP VIEW ) Vcc DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss Pin Names A0-A8 Function Address Input RAS Row Address Strobe LCAS,UCAS Column Address Strobe DQ0-15 WE Data-Input/ Data-Output Write Enable OE Output Enable Vcc Power Supply ( +5V ) Vss NC Ground ( 0V ) No Connection Note1 : The same power supply voltage must be provided to every Vcc pin, and the same GND voltage level must beprovideded to every Vss pin. 40Pin 400mil SOJ REVISION-2 1997.11.10, specification are subject to change without advanced notice. BLOCK DIAGRAM WE OE Timing Generater RAS I/O Controller LCAS I/O Controller UCAS 8 Output Buffers 8 Input Buffers 8 8 Input Buffers 8 8 DQ0~DQ7 9 A0~A8 9 Column Address Buffer 9 Internal Address Counter Refresh Control Clock Row Address 9 Buffer Row Decoders Word Drivers Column Decoders Sence amplifier 16 I/O 16 Selector Memory cells DQ8~DQ15 8 Output Buffers 8 Vcc On Chip VBB Generater Vss FUNCTION TABLE DQPin Input Pin Functinal Mode RAS LCAS UCAS WE OE H L * H * H * * High-Z High-Z DOUT High-Z Lower Byte Read L L H H L * L High-Z L * H High-Z L H L L L High-Z L L L H L H L L H H L L L L H L L L H L H H DQ0~DQ7 DQ8~DQ15 Standby Refresh DOUT DOUT Upper Byte Read DOUT DIN Don`t Care Lower Byte Write Don`t Care DIN Upper Byte Write DIN Word Write High-Z - DIN High-Z Word Read ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Rating Symbol Conditions Value Voltage on any pin relative to Vss Vt Ta=25°C -1.0 ~ +7.0 Unit V Short circuit output current Ios Ta=25°C 50 mA Power dissipation PD Ta=25°C 1.5 W Operrating temperrature Topr 0 ~ +70 °C Storage temperature Tstg -55 ~ +150 °C Recommended Operating Conditions Parameter Supply voltage Symbol (Ta=0°Cto 70°C) Conditions Vcc Vss Min. Typ. Max. 4.5 0 5.0 0 5.5 0 Unit V V Input high voltage VIH 2.4 6.5 V Input low voltage VIL -1.0 0.8 V Capacitance Parameter Input capacitance (A0~A8) (Vcc=5V±10%,Ta=25°C,f=1MHz) Symbol CIN1 Conditions Typ. Max. 8 Unit pf Input capacitance (RAS,LCAS,UCAS,WE,OE) CIN2 8 pf Input / output capacitance (DQ0~DQ15) CI/0 9 pf DC CHARACTERISTICS (Vcc=5V±10%, Ta=0 to 70°C) Parameter MSM5416258B MSM5416258B MSM5416258B -28 -30 -35 Symbol Condition Output High Voltage VOH IOH= - 1.0mA 2.4 Vcc 2.4 Vcc 2.4 Vcc V Output Low Voltage VOL IOL= 2.0mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI 0V≤VIN≤Vcc -10 10 -10 10 -10 10 µA Output Leakage Current ILO DQi Disable 0V≤Vo≤5.5V -10 10 -10 10 -10 10 µA - 270 - 265 - 260 mA 1,2 Min. Max. Min. Max. Min. Max. Unit Note Average Power Supply Current (Operating) ICC1 Power Supply Current (Standby) ICC2 RAS,CAS = VIH - 3 - 3 - 3 mA 1 Average Power Supply Current (RAS only Refresh) ICC3 RAS=Cycling CAS=VIH tRC=Min. - 270 - 265 - 260 mA 1,2 Average Power Supply Current (Fast Page Mode) ICC4 RAS=VIL CASCycling tHPC=Min. - 270 - 265 - 260 mA 1,3 Average Power Supply Current (CAS Before RAS Refresh) ICC5 RAS=Cycling CAS Befor RAS - 270 - 265 - 260 mA 1,2 RAS,CAS Cycling tRC=Min. Notes : 1. Icc Max. is specified as Icc for the output open cindition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. AC CHARACTERISTICS (1/2) (Vcc =5V±10%, Ta =0~70°C) Parameter Random read or write cycle time Read/Write cycle time Hyper page mode cycle time MSM5416258B MSM5416258B -28 -30 Symbol MIN MAX MIN MAX tRC 48 55 tRMW 70 MSM5416258B -35 MIN MAX Unit 60 ns 75 85 ns Note tHPC 12 13 13 ns Fast page mode read/write cycle time tPRMW 34 35 45 ns Access time from RAS tRAC 28 30 35 ns 7,12,13 Access time from CAS Access time from column address tCAC 9 9 10 ns 7,12 tAA 15 16 19 ns 7,13 Access time from OE tOEA 9 9 10 ns Access time from CAS precharge tCPA 17 18 21 ns 7,12 Data hold after CAS low tCOH 3 ns 17 Output buffer turn-off delay time tOFF 3 7 3 8 3 8 ns 8 OE to data output buffer turn-off delay time tOEZ 3 7 3 8 3 8 ns 8 RAS to data output buffer turn-off delay time tREZ 3 7 3 8 3 8 ns 8 WE to data output buffer turn-off delay time tWEZ 3 7 3 8 3 8 ns 8 Transition time tT 2 35 2 35 2 35 ns Refresh preiod tREF 8 ms RAS precharge time tRP 17 RAS pulse width tRAS 28 10,000 30 10,000 35 10,000 ns RAS pulse width (Fast page mode) tRASP 28 100,000 30 100,000 35 100,000 ns RAS hold time tRSH 7 7 8 ns RAS hold time reference to OE tROH 7 7 8 ns CAS precharge time tCP 4 CAS pulse width tCAS 5 CAS hold time tCSH CAS to RAS precharge time tCRP 22 5 RAS to CAS delay time tRCD 10 19 RAS to column address delay time tRAD 8 13 Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 6 6 7 ns Column address set-up time tASC tCAH 0 5 0 5 ns Column address hold time 0 5 Column address hold time from RAS tAR 21 22 25 ns Column address to RAS lead time Read command set-up time tRAL tRCS 15 18 0 0 20 0 ns ns Read command hold time tRCH 0 0 0 ns Read command hold time reference to RAS tRRH 0 0 0 ns WE pulse width tWEP 10 10 10 ns 3 3 8 8 4 10,000 5 ns 20 18 ns 4 10,000 5 10,000 ns ns 30 25 5 ns 5 11 22 13 26 ns 8 15 10 16 ns 12 13 ns 9 9 AC CHARACTERISTICS (2/2) Parameter Write command set-up time Write command hold time Write command pulse width (Vcc=5V±10%, Ta=0~70°C) MSM5416258B MSM5416258B MSM5416258B -35 -28 -30 Unit Symbol MIN MAX MIN MAX MIN MAX ns tWCS 0 0 0 ns tWCH 5 5 6 Note tWP 5 5 6 ns Write command hold time from RAS tWCR 21 22 26 ns OE command hold time Write command to CAS lead time tOEH 5 5 6 ns tCWL 5 5 6 ns Write command to RAS lead time tRWL 7 7 8 ns Data to CAS delay time tDZC 0 0 0 ns Data to OE delay time tDZO 0 0 0 ns Data-in set-up time Data-in hold time tDS 0 0 0 ns 10 tDH 5 5 6 ns 10 Data-in hold time referenced to RAS tDHR 21 22 26 ns OE to Data-in delay time tOED 7 7 8 ns OE "L" to CAS "H" lead time tOCH 5 5 8 ns CAS "H" to OE "L" lead time Hi-Z command pulse width tCHO 5 5 8 ns tOEP 5 6 8 ns CAS to WE delay time tCWD 18 18 20 ns 11 Column address to WE delay time tAWD 24 27 30 ns 11 RAS to WE delay time tRWD 37 40 45 ns 11 CAS active delay time from RAS precharge tRPC 0 0 0 ns RAS to CAS set-up time (CAS before RAS) tCSR 5 6 8 ns RAS to CAS hold time (CAS before RAS) tCHR 6 6 8 ns Notes: 1. All voltages are referenced to Vss. 2. This parameter is dependent upon the cycle rate. 3. This parameter is dependent upon the output loading. Specified values are obtained with the output open. 4. An initial pause of 200µs is required after power-up, followed by any 8RAS cycles. (Example: RAS-only-refresh) before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8CAS before RAS cycles instead of 8RAS cycles are required. 5. The AC characteristics assume tT=5ns. 6. VIH (Min.)and V IL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and V IL. 7. Data outputs are measured with a load of 30 pF. DOUT reference levels: V OH/VOL=1.8V/1.4V. 8. tREZ (Max.), tOFF (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the outputs achieve the open circuit condition and are not referebced to output voltage levels. This parameter is sampled and not 100 % tested. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to CAS leadind edge of early write cycles and to WE leading edge in OE-controlled write cycles and read-modify-write cycles. 11. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS (Min.), the cycle is an early write cycle and the data out pins will remain open circuit throughout the entire cycle. If tRWD≥tRWD (Min.), tCWD≥tCWD (Min.) and tAWD≥tAWD (Min.), the cycle is a read-modifywrite cycle and the data out will contain data read from the selected cell. If neither or the above sets of conditions is satisfied, the condition of the data out is indetermunate. 12. Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCDC. 13. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 14. Input levels at the AC testing are 3.0V/0V. 15. Addresses (A0 - A8) may be changed two times or less while RAS =V IL. 16. Addresses (A0 - A8) may be changed once or less while CAS =V IH and RAS =V IL. 17. This is guaranteed by design. ( tCOH=tCAC - output transition time). This parameter is not 100 % tested. 18. This parameter is dependent upon the number of address transitions. Specified values are measured with a maximum of two transitions per address cycle in Fast Page Mode. READ CYCLE (RAS output control ) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD UCAS LCAS A0-8 tAR tRAD tASR tRAH tASC tRAL tCAH COLUMN ROW tRCS tRCH WE tRRH tROH tOEZ tOEA OE tCAC tOFF tAA DQ0-7 HZ VALID DATA tRAC tOFF DQ8-15 HZ VALID DATA : "H" or "L" READ CYCLE (CAS output control ) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD UCAS LCAS tAR tRAD tASR tRAH A0-A8 ROW tRAL tASC tCAH COLUMN tRCS tRRH WE tROH tOEA tOEZ OE tCAC tOFF tAA DQ0-7 HZ VALID DATA tRAC DQ8-15 HZ VALID DATA : "H" or "L" EARLY WRITE CYCLE (LCAS and UCAS active) tRC tRAS tRP RAS tCSH tCRP LCAS UCAS tAR tRAD tASR A0-8 tRSH tCAS tRCD tRAL tASC tRAH tCAH COLUMN ROW tCWL tRWL tWP WE tWCR tWCS tWCH OE tDHR tDS DQ0-7 VALID DATA tDS DQ8-15 tDH tDH VALID DATA : "H" or "L" LATE WRITE CYCLE (LCAS and UCAS active) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD LCAS UCAS tAR tRAD tASR A0-8 tRAH tRAL tASC tCAH COLUMN ROW tCWL tRWL tWP tRCS WE tWCR tOEH OE tDS DQ0-7 VALID DATA tDS DQ8-15 tDH tDH VALID DATA : "H" or "L" READ MODIFY WRITE CYCLE (LCAS and UCAS active) tRMW tRAS tRP RAS tCSH tCRP LCAS UCAS tAR tRAD tASR tRAH A0-8 tRSH tCAS tRCD tRAL tASC ROW tCAH COLUMN tCWL tAWD tRCS tRWL tWP WE tRWD tCWD tDZO tOEA tOEZ O E tOEH tOED tCAC tDS tDZC DQ07 OUT tDH IN tRAC tDS DQ8-15 OUT tDH IN : "H" or "L" FAST PAGE MODE READ CYCLE with Extended Data Out tRC tRASP tRP RAS tCRP LCAS tRCD tCSH tCAS tCP tPC tCAS tRSH tCAS tCP UCAS tAR tRAD tASR tRAH tASC A0-8 ROW tCAH COLUMN tASC tCAH COLUMN tASC tRAL tCAH COLUMN tRCH tRCS WE tRRH tOEA OE tCAC tAA DQ0-7 HZ tCAC tCAC tCOH tCOH VALID DATA tRAC VALID DATA tCPA tCPA tAA tAA tOEZ tREZ VALID DATA tOEZ tREZ DQ8-15 HZ VALID DATA VALID DATA VALID DATA : "H" or "L" FAST PAGE MODE READ Hi-Z OPERATION tRC tRP tRASP RAS tAR tRSH tHPC tCSH tCRP tCP tRCD LCAS tCAS tCP tCP tCRP tCAS tCAS tCAS UCAS tRAL tRAD tASR A0-8 tRAH ROW tASC tCAH COLUMN tASC tASC tCAH tASC tCAH COLUMN COLUMN COLUMN tCAH tRRH tRCS tRCH tRCS tRCH WE tOCH tCHO tRAC tOEA OE tCAC tCAC tAA tCAC tAA tCPA tDOH tWEP tOEP tOEP tCAC tAA tOEZ tOEA tOEZ tOEA tWEZ tREZ tAA DQ0-7 VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA DQ8-15 VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA : "H" or "L" FAST PAGE MODE EARLY WRITE CYCLE tRC tRASP tRP RAS tCRP LCAS UCAS A0-8 WE tCSH tRCD tCAS tAR tRAD tASR tRAH tASC ROW tCAH COLUMN tCWL tWCS tWCH tWP tPC tCP tASC tCAS tCAH COLUMN tCWL tWCS tWCH tWP tRSH tCAS tCP tASC tRAL tCAH COLUMN tCWL tWCS tWCH tWP OE DQ0-7 DQ8-1 5 tDS tDH tDS tDH tDS tDH Input Data Input Data Input Data tDS tDH tDS tDH tDS tDH Input Data Input Data Input Data : "H" or "L" FAST PAGE MODE READ MODIFY WRITE CYCLE tRC tRASP tRP RAS tCRP LCAS UCAS tRCD tAR tRAD tASR tRAH tASC A0-8 ROW tCAH tASC COLUMN @ tRCS tCWD tWP tOEA tCAH tOEZ tRSH tCAS tCP tASC COLUMN tCWL tAWD WE tPRMW tCAS tCP tCAS tRAL tCAH COLUMN tCWL tAWD tCWL tAWD tCWD tWP tCWD tWP tOEA tOEZ tOEA tOEZ tCAC tCAC OE tCAC tDH tAA tDS DQ0-7 OUT tCAC tAA IN tDH tAA tDS DQ8-15 OUT tDH tDS OUT tCAC IN tDH tAA tDS IN OUT tDH tAA tDS OUT tAA tDS IN IN tCAC OUT tDH IN : "H" or "L" CAS BEFORE RAS REFRESH CYCLE tRC tRAS tRP tRP RAS tRPC tCSR tCHR tRPC LCAS INHIBIT FALLING TRANSITION UCAS A0-8 WE OE tOFF HZ DQ0-7 tOFF DQ8-15 HZ : "H" or "L" HIDDEN REFRESH CYCLE tRC tRAS tRP tRAS RAS tCRP LCAS UCAS A0-8 tRCD tCHR tRSH tAR tRAD tRAL tASR tRAH tASC tCAH COLUMN ROW tRCS WE tRRH tROH tOEZ tOEA OE tRAC DQ0-7 HZ tRAC DQ8-15 HZ tOFF tCAC tAA VALID DATA tOFF tCAC tAA VALID DATA : "H" or "L" RAS ONLY REFRESH CYCLE tRC tRAS tRP RAS tCRP tRPC LCAS UCAS tASR A0-8 tRAH ROW WE OE DQ0-7 DQ8-15 HZ HZ : "H" or "L" PACKAGE OUTLINES AND DIMENSIONS (Unit: mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5mm or more 1.70 TYP. Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5mm or more 1.86 TYP. SOJ42-P-400-1.27 Mirror finish 20/20