RF2196 Preliminary 2 3V PCS LINEAR POWER AMPLIFIER Typical Applications • 3 V CDMA 2000 PCS Handsets • 3V CDMA KPCS Handsets • Spread-Spectrum Systems • 3V TDMA/GAIT PCS Handsets • Portable Battery-Powered Equipment Product Description 2 2 0.45 0.28 3.75 The RF2196 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide process, and has been designed for use as the final RF amplifier in 3V CDMA and CDMA2000 handsets as well as other applications in the 1750MHz to 1910MHz band. The RF2196 has a low power mode to extend battery life under low output power conditions. The package is an ultra small 4mmx4mm leadless plastic package with backside ground. 1 0.80 TYP 0.75 0.50 3.75 + 1 1.60 4.00 12° 1.50 SQ INDEX AREA 3 3.20 0.75 0.65 4.00 1.00 0.90 0.05 0.00 NOTES: 1 Shaded Pin is Lead 1. 2 Dimensions in mm. Dimension applies to plated terminal and is measured between 0.10 mm and 0.25 mm from terminal tip. The terminal #1 identifier and terminal numbering convention 3 shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The identifier may be either a mold or marked feature. 4 5 Optimum Technology Matching® Applied Si BJT Si Bi-CMOS ü GaAs HBT GaAs MESFET SiGe HBT Si CMOS Pins 1 and 9 are fused. Package Warpage: 0.05 max. Package Style: LCC, 16-Pin, 4x4 Features GND RF IN NC NC NC • Single 3V Supply 1 16 15 14 13 10 VCC 5 6 7 8 9 GND VPD2 4 RF OUT 11 VCC1 RF OUT MODE 3 NC 12 VCC1 GND VPD1 2 Functional Block Diagram Rev A0 010518 • 29dBm Linear Output Power • 35% Linear Efficiency • Low Power Mode (Up to 20dBm) • 55mA Idle Current Ordering Information RF2196 RF2196 PCBA 3V PCS LINEAR Power Amplifier Fully Assembled Evaluation Board RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 2-203 POWER AMPLIFIERS • 3V CDMA PCS Handsets RF2196 Preliminary Absolute Maximum Ratings Parameter Rating Unit +8.0 +5.2 +4.2 VDC VDC VDC +3.0 +10 -30 to +110 -30 to +150 Modified JEDEC Level 2 VDC dBm °C °C Supply Voltage (RF off) Supply Voltage (POUT ≤31dBm) Mode Voltage (VMODE) POWER AMPLIFIERS 2 Control Voltage (VREG) Input RF Power Operating Case Temperature Storage Temperature Moisture Sensitivity Parameter Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Case T=25°C, VCC =3.4V, VREG =2.85V, VMODE =0V to 0.5V, Freq=1850MHz to 1910MHz (unless otherwise specified) High Power State (VMODE Low) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection 1850 25 1910 27 -50 -63 29 35 -46 -62 <2:1 Input VSWR Output VSWR MHz dB dBc dBc dBm -44 % dBc POUT =29dBm ACPR @1.25MHz -56 dBc ACPR @2.25MHz 10:1 6:1 Noise Power -141 dBm/Hz Low Power State (VMODE High) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Max ICC Adjacent Channel Power Rejection Input VSWR Output VSWR 2-204 Condition 1850 16 16 1910 20 -45 -60 20 160 <-50 <-60 2:1 No damage. No oscillations. >-70dBc At 80MHz offset. Case T=25°C, VCC =3.4V, VREG =2.85V, VMODE =2V to 3V, Freq=1850MHz to 1910MHz (unless otherwise specified) MHz dB dBc dBc dBm -46 mA dBc POUT =+16dBm (all currents included) ACPR @1.25MHz -58 dBc ACPR @2.25MHz 10:1 6:1 No damage. No oscillations. >-70dBc Rev A0 010518 RF2196 Preliminary Specification Min. Typ. Max. Unit Case T=25°C, VCC =3.4V, VREG =2.85V, VMODE =0V to 0.5V, Freq=1850MHz to 1910MHz (unless otherwise specified) High Power State CDMA 2000 1x (VMODE LOW) Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Pilot+FCH 9600+SCH0 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection 1850 1910 27 26.5 MHz dB dBm -49 dBc -61 dBc ACPR@ 2.25MHz dBm 4.5dB peak to average at CCDF of 1% -46 dBc ACPR@ 1.25MHz -63 dBc ACPR@ 2.25MHz Case T=25°C, VCC =3.4V, VREG =2.85V, VMODE =2V to 3V, Freq=1850MHz to 1910MHz 29 Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection 1850 16 16 2 2.5dB Backoff included in IS95D 5.4dB peak to average at CCDF of 1% ACPR@ 1.25MHz Low Power State CDMA 2000 1x (VMODE HIGH) Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Condition 19 1910 MHz dB 20 dBm 5.4dB peak to average at CCDF of 1% -52 dBc ACPR@ 1.25MHz -65 dBc ACPR@ 2.25MHz 20 dBm 4.5dB peak to average at CCDF of 1% -52 dBc ACPR@ 1.25MHz -65 dBc ACPR@ 2.25MHz DC Supply Supply Voltage Quiescent Current VREG Current VMODE Current Total Current (Power Down) VREG “Low” Voltage VREG “High” Voltage VMODE “Low” Voltage VMODE “High” Voltage Rev A0 010518 3.0 0 2.75 0 2.0 3.4 185 55 5 2.85 4.2 10 1 10 0.5 2.95 0.5 V mA mA mA mA µA V V V 3.0 V VMODE =Low VMODE =High VREG =Low 2-205 POWER AMPLIFIERS Parameter RF2196 Pin 1 2 Function GND VREG1 3 MODE 4 VREG2 5 GND 6 NC 7 RF OUT 8 9 10 RF OUT GND VCC 11 VCC1 12 13 VCC1 NC 14 NC 15 NC 16 RF IN POWER AMPLIFIERS 2 Preliminary Description Interface Schematic This pin is internally grounded to the die flag. Power Down control for first stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). For nominal operation (High Gain Mode), VMODE is set LOW. When set HIGH, the driver and final are dynamically scaled to reduce the device size and as a result to reduce idle current. Power Down control for the second stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). Connect to ground plane via 15nH inductor. DC return for the second stage bias circuit. This pin has no internal bonding; therefore, this pin can be connected to output pin 7, connected to the ground plane, or not connected. Slight tuning of the output match may be required due to stray capacitance of the pin. RF output and power supply for final stage. This is the unmatched colRF OUT lector output of the second stage. A DC block is required following the matching components. The biasing may be provided via a parallel L-C set for resonance at the operating frequency of 1710MHz to 1910MHz. From Bias It is important to select an inductor with very low DC resistance with a Network 1A current rating. Alternatively, shunt microstrip techniques are also applicable and provide very low DC resistance. Low frequency bypassing is required for stability. Same as pin 7. See pin 7. This pin is internally grounded to the die flag. Supply for bias reference and control circuits. High frequency bypassing may be necessary. Power supply for first stage and interstage match. Pins 11 and 12 should be connected by a common trace where the pins contact the printed circuit board. Same as pin 11. It is recommended that these pins be connected to the ground plane for improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11 and 12). It is recommended that these pins be connected to the ground plane for improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11 and 12). It is recommended that these pins be connected to the ground plane for improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11 and 12). RF input. An external 15pF series capacitor is required as a DC block. In addition, the matching circuit shown is required to improve input VSWR. VCC1 15 pF TL RF IN 3.6 pF GND1 From Bias Stages Pkg Base 2-206 GND Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. Rev A0 010518 RF2196 Preliminary Application Schematic US - CDMA RF IN Matching network for optimum input return loss 2 Interstage tuning for centering frequency response 3.6 pF Bypassing for VREG1 and VREG2 + 1 µF RF Choke - Bias inductor for the amplifier interstage TL4 15 pF 1 Jumper 16 15 14 13 VREG 2 Jumper 12 11 pF TL3 15 pF Bias return 12 nH Matching network for optimum load impedance 3 11 4 10 5 6 7 4.7 pF 8 TL1 TL2 9 Bypassing for VCC 10 nF Ferrite 10 Ω 1 kΩ VMODE POWER AMPLIFIERS 15 pF 1 µF + VCC 15 pF 2.5 nH 15 pF 10 nF 4.7 µF 2.2 pF 2.2 pF 15 pF Transmission Line Length Pins 1 and 9 are internally grounded to the die flag. RF OUT Rev A0 010518 CDMA (US) TL1 TL2 TL3 TL4 30 mils 140 mils 15 mils 200 mils 2-207 RF2196 Preliminary Evaluation Board Schematic US - CDMA RF IN C5 15 pF POWER AMPLIFIERS 2 C24 3.6 pF P1 P1 1 VCC P2 P1 1 VREG P3 P1 1 VMODE P4 P1 1 GND TL4 C26 1 uF + R12 Jumper C27 15 pF 1 16 15 14 13 P2 R11 Jumper R1 1 kΩ P3 2 12 3 11 4 10 C13 15 pF 5 6 7 C1** 4.7 pF L4 12 nH 8 TL1 CDMA (US) C30 (pF) C1 (pF) L1 (nH) C14 (pF) 11 4.7 2.5 2.2 P1 C4 15 pF C28 10 nF C2 4.7 uF * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). Transmission Line Length CDMA (US) 2-208 C25 + 1 uF L1* 2.5 nH C3 15 pF RF OUT C8 10 nF C6 15 pF 9 Pins 1 and 9 are internally grounded to the die flag. Board C30 11 pF L2 Ferrite 10 Ω C7 2.2 pF TL2 C14** 2.2 pF TL3 TL1 TL2 TL3 TL4 30 mils 140 mils 15 mils 200 mils Rev A0 010518 RF2196 Preliminary Evaluation Board Layout Board Size 2.0” x 2.0” Board Thickness 0.028”; Board Material FR-4; Multi-Layer; Ground Plane at 0.014” POWER AMPLIFIERS 2 Rev A0 010518 2-209 RF2196 Preliminary POWER AMPLIFIERS 2 2-210 Rev A0 010518