CXG1015N Power Amplifier/Antenna Switch for PHS Description The CXG1015N is a power amplifier/antenna switch MMIC for PHS. This is designed using the Sony’s GaAs J-FET process and operates at a single positive power supply. Features • Single positive power supply 3.0 V • Output power 20.2 dBm (Antenna switch transfer output pin power) • Low current consumption 160 mA (Output power of 20.2 dBm) • High power gain 39 dB Typ. (Output power of 20.2 dBm) • Low insertion loss 0.5 dB Typ. • Small mold package 20-pin SSOP (Pin interval of 0.5 mm pitch) Structure GaAs J-FET MMIC 20 pin SSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD 6 • Voltage between gate and source Vgs0 1.5 • Drain current IDD 550 • Power dissipation PD 3 • Channel temperature • Operating temperature • Storage temperature Tch Topr Tstg V V mA 150 –35 to +85 –65 to +150 W °C °C °C Applications • Power amplifiers for PHS • Antenna switches for PHS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E97749-TE CXG1015N Electrical Characteristics Power Amplifier + Antenna Switch Transfer Block VDD=3.0 V, VCTL=2.0 V, f=1.90 GHz Item ∗ Current consumption ∗ Gate voltage adjustment value Output power (Power Amplifier + Antenna Switch Transfer Block) ∗ Power gain ∗ Adjacent channel leak power ratio (600 kHz±100 kHz) (Ta=25 °C) Symbol IDD VGG2 Min. POUT 20.2 GP 35.5 0 ACPR600 Typ. 160 0.25 Max. 0.7 Unit mA V dBm 39 42 dB –59 –54 dBc ∗ Values where VGG1 and VGG2 are adjusted so that IDD becomes 160 mA when the power amplifier output pin and the antenna switch transfer input pin are connected on the Sony’s recommended evaluation board and the output power on the antenna switch transfer output pin is 20.2 dBm. Antenna Switch Receive Block VCTL(L)=0 V, VCTL(H)=3.0 V Item Insertion loss Isolation Control pin current (Ta=25 °C) Symbol IL ISO ICTL —2— Min. 20 Typ. 0.5 24 40 Max. 0.8 100 Unit dB dB µA CXG1015N Block Diagram VDD1 VDD2 VDD3 RX VCTL2 PAIN ANT VGG1 VPCTL VGG2 PAOUT TX VCTL1 Pin Configuration 1 Antenna Switch Operation VCTL1=3 V VCTL2=0 V VCTL1=0 V VCTL2=3 V 20 PAIN VGG1 GND VPCTL VDD1 GND GND VGG2 VDD2 GND GND PAOUT VDD3 GND GND TX VCTL2 VGG2 Gate voltage adjustment pin ANT Variation of IDD and POUT due to adjustment (2) Simple adjustment (IDD read) When the RF input (PIN) is off, the gate voltage (VGG2) is set to 0.4 V and IDD is read. The output power (POUT) is adjusted to 20.2 dBm. IDD=160±20 mA POUT=20.2 dBm 1kΩ VGG1 Recommended Current Adjustment Method (1) VGG2/PIN separate adjustment (VGG2 adjustment 1) (PIN adjustment 1) When the RF input (PIN) off, the current consumption (IDD) is adjusted to 160 mA. ON OFF OFF ON Gate Bias Circuit of Power Amplifier Block VCTL1 RX ANT-TX ANT-RX ANT-TX ANT-RX (VGG2 adjustment 2) (PIN adjustment 2) The current consumption (IDD) is finely adjusted to 160 mA. The output power (POUT) is finely adjusted to 20.2 dBm. IDD=160 mA POUT=20.2±0.2 dBm IDD=160±5 mA POUT=20.2 dBm (VGG2 setting) (PIN adjustment) The formula∗ where VGG2=f (IDD: VGG2=0.4 V) is used to set VGG2. The output power (POUT) is adjusted to 20.2 dBm. ∗ e.g. VGG2=a-b × IDD —3— IDD=160±5 mA POUT=20.2 dBm CXG1015N Recommended Evaluation Circuit PAIN VGG2 R1=1kΩ L1=1.8nH L2=2.2nH L3=18nH GND VDD L2 L3 C4 R1 VPCTL C4 L3 C4 C1=1pF C2=30pF C3=100pF C4=1nF C5=10nF C3 C5 C1 C2 L2 L1 RX C2 C2 C3 C2 C3 GND Via Hole VCTL2 VCTL1 ANT Glass fabric-base epoxy board GND for the overall back side Dimension : 25 mm × 25 mm Thickness : 0.2 mm Recommended Gate Bias Circuit and Circuit Characteristics (V) 3.0V 100Ω 6.8kΩ RV1 Variable resistor RV RV2 10kΩ (Max.) VGG2 VGG2 0.5 180Ω 1kΩ 0 5 RV1 (kΩ) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —4— CXG1015N Recommended External Circuit 2.2nH 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 RX 9 12 VCTL2 10 11 PAIN 1nF 18nH 1nF VDD1 1nF 18nH 30pF VDD2 10nF 1.8nH VDD3 (VGG1) 100pF VPCTL 1kΩ VGG2 1pF 2.2nH (PAOUT) 30pF 30pF (TX) 100pF VCTL1 30pF 100pF Example of Representative Characteristics (Ta=25 °C) Antenna Switch Receive Block IL, Iso. vs. Freq. 0 0 –1 –10 –2 –20 –3 –30 Iso. –4 –40 –5 –50 0 1 2 Frequency (GHz) 3 —5— Iso.-Isolation (dB) IL-Insertion loss (dB) IL ANT CXG1015N 15 –50 POUT 10 –55 5 –60 0 –65 ACPR –5 –45 –40 –35 –30 –25 –20 PIN-Input power (dBm) –15 –70 –10 POUT, ACPR vs. VDD VDD=var., VPCTL=2.0V, VGG=const., IDD=160mA (@POUT=20.2dBm), PIN=–19.2dBm 22 –50 POUT-Output power (dBm) POUT 21 –55 20 –60 19 –65 ACPR 18 2.0 2.5 3.0 3.5 4.0 VDD-Supply voltage (V) 4.5 –70 5.0 Gain 40 –45 35 –50 30 –55 25 –60 20 –65 ACPR 15 0.0 0.5 1.0 1.5 2.0 2.5 VPCTL-Gain control voltage (V) –70 3.0 Gain, ACPR vs. IDD VDD=3.0V, VPCTL=2.0V, VGG=var., IDD=var., PIN=var., POUT=20.2dBm 45 –50 Gain —6— 40 –55 35 –60 ACPR 30 –65 110 120 130 140 150 160 170 180 190 200 210 220 230 IDD-Drain current (mA) ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset) –45 –40 ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset) 20 45 Gain-Power gain (dB) –40 Gain, ACPR vs.VPCTL VDD=3.0V, VPCTL=var., VGG=const., IDD=160mA (@VPCTL=2V), PIN=var., POUT=20.2dBm Gain-Power gain (dB) 25 ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset) POUT-Output power (dBm) POUT, ACPR vs. PIN VDD=3.0V, VPCTL=2.0V, VGG=const., IDD=160mA (@POUT=20.2dBm), PIN=var. ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset) Example of Representative Characteristics Power Amplifier + Antenna Switch Transfer Block CXG1015N Unit : mm 20PIN SSOP(PLASTIC) 0.1 ∗5.0 ± 0.05 1.25MAX A 20 S 6.4 ± 0.2 ∗4.4 ± 0.05 11 A 10 1 0.5 0.1 0.1 M S A 0.6 ± 0.15 0.25 0.1 ± 0.1 + 0.07 0.2 – 0.03 (0.2) 0° to 10° DETAIL A DETAIL B (0.15) + 0.05 0.15 – 0.01 B (0.5) Package Outline NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE SSOP-20P-L03 LEAD TREATMENT EIAJ CODE SSOP020-P-0044 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE —7—