CXP82200 CMOS 8-bit Single Chip Microcomputer Description The CXP82200 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP82220/82224. Piggyback/ evaluator type 100 pin PQFP (Ceramic) Features • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit operation/multiplication and division/ Boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation 122µs at 32kHz operation • Applicable EPROM LCC type 27C128, LCC type 27C256 (Maximum 24K bytes are available.) • Incorporated RAM capacity 704 bytes (Including fluorescent display data area) • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter 32kHz timer/counter — Fluorescent display panel controller/driver Maximum 384 segment display possible 1 to 16-digit dynamic display Dimmer function High voltage drive output (40V) On-chip pull-down resistor (Mask option) Hardware key scan function (Maximum 16 × 8 key matrix compatible) — Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO — PWM output 14 bits, 1 channel — CTL duty detection circuit — High-speed output circuit Four RTG outputs • Interruption 19 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin ceramic QFP Note) Mask option depends on the type of the CXP82200. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93847A78-PS CXP82200 T6 T5 T4 T3 T2 T1 T0 VFDP VDD NC Vss PG0/RTO0 PG1/RTO1 PG2/RTO2 PG3/RTO3 PG4 PG5 PG6 PG7 PE0/EC0/INT0 Pin Assignment in Piggyback Mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 T8/S31 PE3/INT3/NMI 78 T9/S30 PE4/RMC 4 77 T10/S29 PE5/CTL 5 76 T11/S28 PE6/PWM 6 75 T12/S27 PE7/T0/DD0/ADJ 7 74 T13/S26 PB0/CINT 8 73 T14/S25 72 T15/S24 71 PI7/S23 70 PI6/S22 69 PI5/S21 68 PI4/S20 PB1/CS0 9 PB2/SCK0 10 PB3/SI0 11 PB4/SO0 12 PB5/SCK1 13 PB6/SI1 14 PB7/SO1 15 PC0/KR0 16 PC1/KR1 17 PC2/KR2 18 PC3/KR3 19 PC4/KR4 20 4 3 2 NC A13 79 A14 2 3 VDD PE2/INT2 A15 T7 A12 80 A7 1 PE1/EC1/INT1 32 31 30 1 A6 5 29 A8 A5 6 28 A9 A4 7 27 A11 A3 8 26 NC A2 9 25 OE A1 10 24 A10 A0 11 23 CE NC 12 22 D7 D0 13 21 D6 14 15 16 17 18 19 20 67 PI3/S19 66 PI2/S18 65 PI1/S17 64 PI0/S16 63 PF7/S15 62 PF6/S14 61 PF5/S13 D5 NC D4 PF3/S11 D3 PF4/S12 59 GND 60 22 D2 21 PC6/KR6 D1 PC5/KR5 PC7/KR7 23 58 PF2/S10 PH0 24 57 PF1/S9 PH1 25 56 PF0/S8 PH2 26 55 PD7/S7 PH3 27 54 PD6/S6 PH4 28 53 PD5/S5 PH5 29 52 PD4/S4 PH6 30 51 PD3/S3 PD2/S2 PD1/S1 PD0/S0 Vss AVREF PA7/AN7 TEX PA6/AN6 TX Vss XTAL EXTAL RST PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 91) are both connected to GND. –2– CXP82200 T6 T5 T4 T3 T2 T1 T0 VDD VFDP NC Vss PG0/RTO0 PG1/RTO1 PG2/RTO2 PG3/RTO3 PG4 PG5 PG6 PG7 PE0/EC0/INT0 Pin Assignment in Evaluator Mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PE1/EC1/INT1 1 80 T7 PE2/INT2 2 79 T8/S31 PE3/INT3/NMI 3 78 T9/S30 PE4/RMC 4 77 T10/S29 74 T13/S26 8 73 T14/S25 PB1/CS0 9 72 T15/S24 PB2/SCK0 10 PB3/SI0 11 PB4/SO0 12 PB5/SCK1 13 4 3 2 A13 7 PB0/CINT A14 PE7/T0/DD0/ADJ VDD T12/S27 NC T11/S28 A15 76 75 A12 5 6 A7/D7 PE5/CTL PE6/PWM 1 32 31 30 71 PI7/S23 PI6/S22 A6/D6 5 29 A8 70 A5/D5 6 28 A9 69 PI5/S21 PI4/S20 A4/D4 7 27 A11 68 PB6/SI1 14 A3/D3 8 26 NC 67 PI3/S19 PB7/SO1 15 A2/D2 9 25 HALT 66 PI2/S18 PC0/KR0 16 A1/D1 10 24 A10 65 PI1/S17 PC1/KR1 17 A0/D0 11 23 E/P 64 PI0/S16 PC2/KR2 18 NC 12 22 I/T 63 PF7/S15 PC3/KR3 19 RD 13 21 MON 62 PF6/S14 PC4/KR4 20 61 PF5/S13 PC5/KR5 21 60 PF4/S12 PC6/KR6 22 59 PF3/S11 PC7/KR7 23 58 PF2/S10 PH0 24 57 PF1/S9 PH1 25 56 PF0/S8 PH2 26 55 PD7/S7 PH3 27 54 PD6/S6 PH4 28 53 PD5/S5 PH5 29 52 PD4/S4 PH6 30 51 PD3/S3 RST C1 C2 NC GND SYNC WR 14 15 16 17 18 19 20 Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 91) are both connected to GND. –3– PD2/S2 PD1/S1 PD0/S0 Vss AVREF PA7/AN7 PA6/AN6 TX TEX Vss XTAL EXTAL RST PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP82200 EPROM Read Timing (Ta = –20 to +75°C, Vcc = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Address → Data Input delay time tACC A0 to A15 D0 to D7 Address → Data Hold time tIH A0 to A15 D0 to D7 Min. Max. Unit 120 ns 0 ns 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Products List Products Option item Mask CXP82220 Package ROM capacitance Pull-up resistance for reset pin 100-pin plastic QFP 20K bytes 24K bytes CXP82200-U01Q 100-pin ceramic PQFP EPROM 24K bytes Existent/Non-existent Existent Non-existent Non-existent Existent/Non-existent Only port for display Power-on reset circuit Pull-down resistance for high voltage drive pin CXP82224 Piggyback/evaluator –4– CXP82200 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Evaluator mode Piggyback/evaluator product Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU Probe Note) Evaluation cap should be connected to CPU probe. –5– 24.7 INDEX PIN NO. 1 INDEX 22.3 ± 0.25 3.57 ± 0.36 30 1 31 100 15.58 ± 0.2 11.66 9.48 4.5 16.3 ± 0.2 18.7 50 81 51 80 100PIN PQFP (CERAMIC) 14.22 10.44 MAX Unit: mm 12.02 0.50 ± 0.25 1.27 ± 0.13 0.3 + 0.05 0.15 – 0.02 –6– 1.0 0.45 JEDEC CODE AQFP100-C-0000-A 50 EIAJ CODE 51 80 81 PQFP-100C-L01 0.7 SONY CODE 1.3 ± 0.3 30 1 PIN No. 1 INDEX GOLD PLATING PACKAGE WEIGHT 5.7g 42 ALLOY LEAD TREATMENT LEAD MATERIAL CERAMIC PACKAGE MATERIAL PACKAGE STRUCTURE 31 100 0.65 ± 0.05 0.3 ± 0.08 18.12 ± 0.2 6.0 Package Outline CXP82200