ICX267AK Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras Description The ICX267AK is a diagonal 8mm (Type 1/2) interline CCD solid-state image sensor with a square pixel array and 1.45M effective pixels. Progressive scan allows all pixels' signals to be output independently. Also, the adoption of high frame rate readout mode supports 30 frames per second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without a mechanical shutter. High resolution and high color reproductivity are achieved through the use of R, G, B primary color mosaic filters. Further, high sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as electronic still cameras, PC input cameras, etc. Features • Progressive scan allows individual readout of the image signals from all pixels. • High horizontal and vertical resolution (both approx. 800TV-lines) still image without a mechanical shutter. • Supports high frame rate readout mode (effective 512 lines output, 30 frames/s) • Square pixel • Horizontal drive frequency: 28.636MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • R, G, B primary color mosaic filters on chip • High resolution, high color reproductivity, high sensitivity, low dark current • Low smear, excellent antiblooming characteristics • Continuous variable-speed shutter 20 pin DIP (Plastic) Pin 1 2 V 8 2 Pin 11 H 40 Optical black position (Top view) Device Structure • Interline CCD image sensor • Image size: Diagonal 8mm (Type 1/2) • Total number of pixels: 1434 (H) × 1050 (V) approx. 1.50M pixels • Number of effective pixels: 1392 (H) × 1040 (V) approx. 1.45M pixels • Number of active pixels: 1360 (H) × 1024 (V) approx. 1.40M pixels (7.959mm diagonal) • Chip size: 7.60mm (H) × 6.20mm (V) • Unit cell size: 4.65µm (H) × 4.65µm (V) • Optical black: Horizontal (H) direction: Front 2 pixels, rear 40 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels • Number of dummy bits: Horizontal 20 Vertical 3 • Substrate material: Silicon ∗ Wfine CCD is a registered trademark of Sony Corporation. Represents a CCD adopting progressive scan, primary color filter and square pixel. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99947A33 ICX267AK GND NC NC Vφ3 Vφ2B Vφ2A Vφ1 8 7 6 5 4 3 2 1 ... ... ... NC 9 ... GND 10 Vertical register VOUT Block Diagram and Pin Configuration (Top View) Note) Note) : Photo sensor 17 NC VL 18 19 20 Hφ2 16 Hφ1 15 φRG 14 CSUB GND 13 NC 12 φSUB 11 VDD Horizontal register Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ1 Vertical register transfer clock 11 VDD Supply voltage 2 Vφ2A Vertical register transfer clock 12 GND GND 3 Vφ2B Vertical register transfer clock 13 φSUB Substrate clock 4 Vφ3 Vertical register transfer clock 14 NC 5 NC 15 CSUB 6 NC 16 NC 7 GND 17 VL Protective transistor bias 8 NC 18 φRG Reset gate clock 9 GND GND 19 Hφ1 Horizontal register transfer clock 10 VOUT Signal output 20 Hφ2 Horizontal register transfer clock GND Substrate bias∗1 ∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. –2– ICX267AK Absolute Maximum Ratings Item Against φSUB Against GND Against VL Ratings Unit VDD, VOUT, φRG – φSUB –40 to +10 V Vφ2A, Vφ2B – φSUB –50 to +15 V Vφ1, Vφ3, VL – φSUB –50 to +0.3 V Hφ1, Hφ2, GND – φSUB –40 to +0.3 V CSUB – φSUB –25 to V VDD, VOUT, φRG, CSUB – GND –0.3 to +18 V Vφ1, Vφ2A, Vφ2B, Vφ3 – GND –10 to +18 V Hφ1, Hφ2 – GND –10 to +15 V Vφ2A, Vφ2B – VL –0.3 to +28 V Vφ1, Vφ3, Hφ1, Hφ2, GND – VL –0.3 to +15 V Voltage difference between vertical clock input pins Between input Hφ1 – Hφ2 clock pins Hφ1, Hφ2 – Vφ3 to +15 V –16 to +16 V –16 to +16 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. –3– Remarks ∗1 ICX267AK Bias Conditions Symbol Item Min. Typ. Max. Unit 14.55 15.0 15.45 V Power Supply voltage VDD Protective transistor bias VL ∗1 Substrate clock φSUB ∗2 Reset gate clock φRG ∗2 Remarks ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Symbol Power supply current Min. IDD Typ. Max. Unit 7.7 Remarks mA Clock Voltage Conditions Min. Typ. Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 VVH02A –0.05 0 0.05 V 2 VVH1, VVH2A, VVH2B, VVH3 –0.2 0 0.05 V 2 VVL1, VVL2A, VVL2B, VVL3 –8.4 –8.0 –7.6 V 2 Vφ1, Vφ2A, Vφ2B, Vφ3 7.6 8.0 8.4 V 2 | VVL1 – VVL3 | 0.1 V 2 VVHH 0.9 V 2 High-level coupling VVHL 1.3 V 2 High-level coupling VVLH 1.0 V 2 Low-level coupling VVLL 0.9 V 2 Low-level coupling Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Symbol VVH = VVH02A VVL = (VVL1 + VVL3)/2 VφH 4.75 5.0 5.25 V 3 VHL –0.05 0 0.05 V 3 3.0 3.3 5.5 V 4 VRGLH – VRGLL 0.4 V 4 Low-level coupling VRGL – VRGLm 0.5 V 4 Low-level coupling 23.85 V 5 VφRG Reset gate clock voltage Remarks Substrate clock voltage VφSUB 22.15 23.0 –4– ICX267AK Clock Equivalent Circuit Constant Item Symbol Min. Max. Unit Remarks 2200 pF 3300 pF 3300 pF CφV3 3300 pF CφV12A, CφV2B1 1200 pF CφV2A3, CφV32B 1200 pF CφV13 2200 pF CφV1 Capacitance between vertical transfer clock and CφV2A GND CφV2B Capacitance between vertical transfer clocks Typ. Capacitance between horizontal transfer clock and GND CφH1, CφH2 47 pF Capacitance between horizontal transfer clocks CφHH 100 pF 8 pF CφSUB 680 pF R1 36 Ω R2A, R3 56 Ω R2B 56 Ω Vertical transfer clock ground resistor RGND 30 Ω Horizontal transfer clock series resistor RφH 15 Ω Reset gate clock series resistor RφRG 20 Ω Capacitance between reset gate clock and GND CφRG Capacitance between substrate clock and GND Vertical transfer clock series resistor Vφ2A Vφ1 CφV12A R1 R2A RφH RφH Hφ1 CφV1 Hφ2 CφHH CφV2A CφV2B1 CφV2A3 CφH1 CφH2 CφV13 CφV2B R2B RGND CφV3 R3 CφV32B Vφ2B Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit RφRG RGφ CφRG Reset gate clock equivalent circuit –5– ICX267AK Drive Clock Waveform Conditions (1) Readout clock waveform VT 100% 90% φM VVT φM 2 10% 0% tr twh 0V tf Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B. (2) Vertical transfer clock waveform Vφ1 VVH1 VVHH VVH VVHL VVLH VVL01 VVL1 VVL VVLL Vφ2A, Vφ2B VVH02A, VVH02B VVH2A, VVH2B VVHH VVH VVHL VVLH VVL2A, VVL2B VVL VVLL VVH3 Vφ3 VVHH VVH VVHL VVLH VVL03 VVL VVLL VVH = VVH02A VVL = (VVL01 + VVL03)/2 VVL3 = VVL03 VφV1 = VVH1 – VVL01 VφV2A = VVH02A – VVL2A VφV2B = VVH02B – VVL2B VφV3 = VVH3 – VVL03 –6– ICX267AK (3) Horizontal transfer clock waveform tr twh tf Hφ2 90% VCR VφH twl VφH 2 10% VHL Hφ1 two Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. (4) Reset gate clock waveform tr twh tf VRGH RG waveform twl VφRG Point A VRGLH VRGL VRGLL VRGLm VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VφRG = VRGH – VRGL. Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM VφSUB 10% VSUB 0% (A bias generated within the CCD) tr twh –7– φM 2 tf ICX267AK Clock Switching Characteristics Symbol twh twl tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock VT Vertical transfer clock Vφ1, Vφ2A, Vφ2B, Vφ3 Horizontal transfer clock Item Hφ1 10 12.5 10 12.5 5 7.5 5 7.5 Hφ2 10 12.5 10 12.5 5 7.5 5 7.5 During imaging 3.2 3.4 0.5 φRG Substrate clock φSUB µs 15 During Hφ1 parallel-serial Hφ2 conversion Reset gate clock 0.5 4 8 24 450 ns 0.01 0.01 0.01 0.01 2 3.9 ns Remarks During readout ∗1 ∗2 µs ns 2 0.5 Unit 0.5 µs During drain charge ∗1 When vertical transfer clock driver CXD1267AN × 2 is used. ∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be at least VφH/2 [V]. Symbol Item Horizontal transfer clock two Min. Typ. 8 10 Hφ1, Hφ2 Max. Unit Remarks ns Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 Relative Response 0.8 0.6 0.4 0.2 0 400 500 600 700 Wave Length [nm] –8– 800 900 1000 ICX267AK Image Sensor Characteristics Measurement method mV 1 Min. Typ. Sg 320 400 R Rr 0.4 0.55 0.7 1 B Rb 0.3 0.45 0.6 1 Vsat 450 mV 2 Vsat2 380 mV 2 Vsat4 380 mV 2 G sensitivity Saturation signal Max. Unit Symbol Item Sensitivity comparison (Ta = 25°C) Remarks 1/30s accumulation Progressive scan readout mode High frame rate Ta = 60°C readout mode High frame rate readout two pixels addition∗1 0.001 0.0025 % 3 Progressive scan readout, high frame rate readout two pixels addition 0.002 0.005 % 3 High frame rate readout mode 20 % 4 Zone 0 and I 25 % 4 Zone 0 to I ' ∆Srg Uniformity between video signal channels ∆Sbg 8 % 5 8 % 5 Dark signal Ydt 8 mV 6 Dark signal shading ∆Ydt 2 mV 7 Line crawl G Lcg 3.8 % 8 Line crawl R Lcr 3.8 % 8 Line crawl B Lcb 3.8 % 8 Lag Lag 0.5 % 9 Smear Sm Video signal shading SHg Ta = 60°C, 15 frames/s Ta = 60°C, 15 frames/s∗2 ∗1 Vsat4 is the saturation signal amount at two pixels addition, and it is 190mV per one pixel. VSUB internal generation value ensures 190mV per one pixel of the saturation signal amount in high frame rate two pixels addition mode. ∗2 Eliminates the dark signal shading in the vertical direction by the high-speed transfer of the vertical register. –9– ICX267AK Zone Definition of Video Signal Shading 1392 (H) 16 16 8 V 10 H 8 H 8 Zone 0, I 1040 (V) 8 Zone II, II' Ignored region Effective pixel region V 10 Measurement System CCD signal output [∗A] Gr/Gb CCD C.D.S AMP Gr/Gb channel signal output [∗B] S/H R/B R/B channel signal output [∗C] S/H Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1. Image Sensor Characteristics Measurement Method Color coding and readout of this image sensor Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. Horizontal register Color Coding Diagram All pixel signals are output successively in a 1/15s period. The R signal and Gr signal lines and the Gb signal and B signal lines are output successively. – 10 – ICX267AK Readout modes The diagram below shows the output methods for the following three readout modes. Progressive scan mode High frame rate readout mode 9 (V2A) 9 (V2A) 9 (V2A) 8 (V2B) 8 (V2B) 8 (V2B) 7 (V2B) 7 (V2B) 7 (V2B) 6 (V2A) 6 (V2A) 6 (V2A) 5 (V2A) 5 (V2A) 5 (V2A) 4 (V2B) 4 (V2B) 4 (V2B) 3 (V2B) 3 (V2B) 3 (V2B) 2 (V2A) 2 (V2A) 2 (V2A) 1 (V2A) VOUT High frame rate readout two pixels addition mode 1 (V2A) 1 (V2A) VOUT VOUT 1. Progressive scan mode In this mode, all pixels signals are output in non-interlace format in 1/15s. The vertical resolution is approximately 800 TV-lines and all pixels signals within the same exposure period are read out simultaneously, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode All effective areas are scanned in approximately 1/30s by reading out two out of four lines (3rd and 4th lines, 7th and 8th lines). The vertical resolution is approximately 400 TV-lines. This readout mode emphasizes processing speed over vertical resolution. 3. High frame rate readout two pixels addition mode All effective areas are scanned in approximately 1/30s by reading out two out of four lines (3rd and 4th lines, 7th and 8th lines), and by reading out two out of the remaining four lines (1st and 2nd lines, 5th and 6th lines) after shifting the vertical register by 2 bits, and adding them in the vertical register. – 11 – ICX267AK Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the progressive scan mode, bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb signal output or the R/B signal output of the measurement system. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition I : Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. G sensitivity, sensitivity comparison Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb)/2 100 Sg = VG × [mV] 30 Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to standard imaging condition I . After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to standard imaging condition I . With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. Sm = Vsm ÷ Gra + Gba + Ra + Ba × 1 × 1 × 100 [%] (1/10V method conversion value) 4 500 10 – 12 – ICX267AK 4. Video signal shading Set to standard imaging condition I . With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula. SHg = (Grmax – Grmin)/150 × 100 [%] 5. Uniformity between video signal channels After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values into the following formulas. ∆Srg = (Rmax – Rmin)/150 × 100 [%] ∆Sbg = (Bmax – Bmin)/150 × 100 [%] 6. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 7. Dark signal shading After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 8. Line crawl Set to standard imaging condition I . Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = ∆Gli × 100 [%] (i = r, g, b) Gai 9. Lag Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) × 100 [%] VD V2A Light Strobe light timing signal output 150mV Output – 13 – Vlag (lag) Drive Circuit 15V –8.0V 1 20 2 19 3 18 4 17 5 XV2A XSG1 16 CXD1267AN 15 7 14 8 13 9 12 10 11 2SK523 1 2 3 4 5 6 7 8 9 10 6 CCD OUT Vφ1 Vφ2A Vφ2B Vφ3 NC NC GND NC GND VOUT XV1 100 3.9k – 14 – XSUB XV3 20 2 19 3 18 4 17 5 16 6 XV2B XSG2 22/20V CXD1267AN 100k 20 19 18 17 16 15 14 13 12 11 1 Hφ2 Hφ1 φRG VL NC CSUB NC φSUB GND VDD ICX267 (Bottom View) 1/35V 22/20V 15 7 14 8 13 9 12 10 11 22/16V 0.01 VR1 (1.3K) VSUB CONT. 0.1 1M 0.1 2200P H2 H1 RG 0.1 Substrate bias adjustment control signal VSUB Cont. Substrate bias φSUB pin voltage ← GND tf ≈ 45ms tr ≈ 1ms ← Internal generation value VSUB (VSUB in high frame rate readout two pixels addition mode) ICX267AK Note) Substrate bias control 1. Connect the ground resistor (VR1) shown below to the CSUB pin by each readout mode in order to secure the saturation signal described on the image sensor characteristics. ・Progressive scan readout mode : 2.0kΩ ・High frame rate readout mode : 3.8kΩ ・High frame rate 2 pixels addition mode: Ground resistor should not be connected. 2. If the substrate bias control signal is set to high level, and the ground resistor (VR1) connected to CSUB pin is not grounded at 55ms before the exposure time starts because tf is late, the internal generation voltage (VSUB) may not fall enough.Substrate bias adjustment control signal VSUB Cont. Sensor Readout Clock Timing Chart Progressive Scan Mode Progressive Scan Mode (With high-speed sweep) XV1 XV2A/XV2B XV3 XSG1 XSG2 The sensor readout clocks XSG1 and XSG2 are added to each XV2A and XV2B. – 15 – HD 69.5ns (2 bits) 27.9µs (800 bits) V1 3.49µs (100 bits) V2A V2B V3 ICX267AK Sensor Readout Clock Timing Chart High Frame Rate Readout Mode XV1 XV2A/XV2B XV3 XSG1 XSG2 The sensor readout clock XSG2 is added to XV2B. – 16 – HD 69.5ns (2 bits) 5.86µs (168 bits) 27.9µs (800 bits) V1 3.49µs (100 bits) V2A V2B V3 ICX267AK Sensor Readout Clock Timing Chart High Frame Rate Readout Two Pixels Addition Mode XV1 XV2A/XV2B XV3 XSG1 XSG2 17.15µs (492 bits) The sensor readout clocks XSG1 and XSG2 are added to each XV2A and XV2B. – 17 – 69.5ns (2 bits) HD 3.49µs (100 bits) 5.86µs (168 bits) 27.9µs (800 bits) V1 V2A V2B V3 98 28 28 28 28 28 28 28 28 28 28 28 28 28 28 2 98 ICX267AK 2 Drive Timing Chart (Vertical Sync) Progressive Scan Mode 1068 1 1063 1052 1044 21 12 13 9 11 10 7 8 5 6 3 4 2 1068 HD 1 1063 VD V1 V2B CCD OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 1038 1039 1040 V3 1040 – 18 – V2A 1 2 3 4 5 6 7 8 1 2 3 4 5 ICX267AK Vφ3 1/30s 3 4 7 8 3 4 7 8 11 12 15 16 3 4 7 8 3 4 7 8 11 12 15 16 523 524 525 526 527 528 529 530 531 532 533 534 1 2 3 4 5 6 7 8 Vφ2B 1035 1036 1039 1040 Vφ2A 523 524 525 526 527 528 529 530 531 532 533 534 1 2 3 4 5 6 7 8 Vφ1 1035 1036 1039 1040 – 19 – CCD OUT 3 4 7 8 3 4 7 8 11 12 15 16 531 532 533 534 1 2 3 4 5 6 7 8 Drive Timing Chart (Vertical Sync) High Frame Rate Readout Mode 1/30s VD HD ICX267AK 3 4 7 8 3 4 7 8 11 12 15 16 1035 1036 1039 1040 3 4 7 8 3 4 7 8 11 12 15 16 1035 1036 1039 1040 3 4 7 8 3 4 7 8 11 12 15 16 1033 1034 1037 1038 1 2 5 6 1 2 5 6 9 10 13 14 1033 1034 1037 1038 1 2 5 6 1 2 5 6 9 10 13 14 – 20 – CCD OUT 1 2 5 6 1 2 5 6 9 10 13 14 1/30s 523 524 525 526 527 528 529 530 531 532 533 534 1 2 3 4 5 6 7 8 523 524 525 526 527 528 529 530 531 532 533 534 1 2 3 4 5 6 7 8 531 532 533 534 1 2 3 4 5 6 7 8 Drive Timing Chart (Vertical Sync) High Frame Rate Readout Two Pixels Addition Mode 1/30s VD HD Vφ1 Vφ2A Vφ2B Vφ3 ICX267AK Drive Timing Chart (Vertical Sync) 412 392 56 430 2 96 16 1 1790 1 HD Progressive Scan Mode (With high-speed sweep) CLK Hφ1 Hφ2 – 21 – Vφ1 1 1 168 1 56 Vφ2A 1 Vφ2B Vφ3 1 SUB 1 168 1 168 1 112 1 168 1 112 56 112 1 1 188 1 56 112 1 36 RGφ ICX267AK 2 412 56 392 96 16 1 1790 1 HD Progressive Scan Mode 430 Drive Timing Chart (Horizontal Sync) CLK Hφ1 Hφ2 1 – 22 – 1 1 Vφ2B 1 84 1 84 84 1 28 56 1 1 84 1 84 84 1 56 1 56 1 84 1 84 84 1 SUB 84 1 1 28 1 1 84 84 1 Vφ2A Vφ3 1 84 Vφ1 188 1 28 112 1 36 RGφ ICX267AK 2 412 56 392 96 16 1 1790 1 HD High Frame Rate Readout Mode 430 Drive Timing Chart (Horizontal Sync) CLK Hφ1 Hφ2 1 – 23 – 1 Vφ2B 1 1 1 56 1 1 56 1 56 84 1 84 1 84 84 1 SUB 1 84 84 84 1 1 84 84 28 84 1 1 28 1 1 84 84 1 Vφ2A Vφ3 1 84 Vφ1 188 1 28 112 1 36 RGφ ICX267AK 2 412 56 392 96 16 1 1790 1 HD High Frame Rate Readout Two Pixels Addition Mode 430 Drive Timing Chart (Horizontal Sync) CLK Hφ1 Hφ2 1 – 24 – 1 1 1 Vφ2B 1 1 56 1 84 1 84 1 56 1 56 1 84 1 84 84 1 SUB 1 84 84 1 1 84 84 28 84 1 1 28 Vφ2A 84 84 1 Vφ1 Vφ3 1 84 188 1 28 112 1 36 RGφ ICX267AK 2 412 56 392 96 16 1 1790 1 HD Progressive Scan Mode (With high-speed sweep) (Refer to "a" on page 21.) 430 Drive Timing Chart (Horizontal Sync) CLK Hφ1 Hφ2 Vφ1 1 168 1 – 25 – 1 56 1 56 Vφ2A Vφ2B Vφ3 1 SUB 1 168 1 168 1 112 1 168 1 112 112 1 1 188 1 56 112 1 36 RGφ ICX267AK Drive Timing Chart (Horizontal Sync) Progressive Scan Mode (With high-speed sweep) (Refer to "b" on page 21.) 56 96 0/1790 96 1 392 1 56 HD 0/1790 247020 bits = 138 lines 56 392 CLK 392 Hφ1 Hφ2 – 26 – Vφ1 Vφ2A Vφ2B Vφ3 RGφ 28 28 28 28 28 28 28 28 28 28 28 28 #1 #1470 ICX267AK ICX267AK Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Cover glass 50N 50N 1.2Nm Plastic package Compressive strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. – 27 – ICX267AK c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to the other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the poweroff mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength are the same. Structure A Structure B Package Chip Metal plate (lead frame) Cross section of lead frame The cross section of lead frame can be seen on the side of the package for structure A. – 28 – Package Outline Unit: mm 20 pin DIP D 20 ~ 11 12.2 12.0 ± 0.1 10.9 1.7 6.0 H 1 1.7 1.7 12.7 10 0.25 0.8 V 0.5 ~ 9.0 C 2.5 B 20 11 1.7 2.5 0˚ to 9˚ A 6.9 10 1 2.5 0.8 – 29 – 10.0 0.5 B' 2.9 ± 0.15 13.8 ± 0.1 ~ 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 0.3 0.3 M PACKAGE STRUCTURE 3.5 ± 0.3 2.4 1.27 1. “A” is the center of the effective image area. 3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference. 4. The center of the effective image area relative to “B” and “B'” is (H, V) = (6.9, 6.0) ± 0.075mm. 5. The rotation angle of the effective image area relative to H and V is ± 1˚. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm. The height from the top of the cover glass “D” to the effective image area is 1.49 ± 0.15mm. Plastic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY 7. The tilt of the effective image area relative to the bottom “C” is less than 50µm. The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm. PACKAGE MASS 0.95g 8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. DRAWING NUMBER AS-B6-04(E) 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. ICX267AK Sony Corporation PACKAGE MATERIAL