ICX432DQ Diagonal 6.67mm (Type 1/2.7) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras Description The ICX432DQ is a diagonal 6.67mm (Type 1/2.7) interline CCD solid-state image sensor with a square pixel array and 3.24M effective pixels. Adoption of a 3-field readout system ensures small size and high performance. This chip features an electronic shutter with variable charge-storage time. R, G, B primary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, etc. 18 pin DIP (Plastic) Pin 1 Features • Supports frame readout system • High horizontal and vertical resolution • Supports high frame rate readout mode : 30 frames/s, AF mode : 60 frames/s, 50 frames/s • Square pixel • Horizontal drive frequency: 24.3MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • R, G, B primary color mosaic filters on chip • High sensitivity, low dark current • Continuous variable-speed shutter • Excellent anti-blooming characteristics • 18-pin high-precision plastic package 2 V 8 4 Pin 11 H 48 Optical black position (Top View) Device Structure • Interline CCD image sensor • Total number of pixels: 2140 (H) × 1560 (V) approx. 3.34M pixels • Number of effective pixels: 2088 (H) × 1550 (V) approx. 3.24M pixels • Number of active pixels: 2080 (H) × 1542 (V) approx. 3.21M pixels diagonal 6.667mm • Number of recommended recording pixels: 2048 (H) × 1536 (V) approx. 3.15M pixels diagonal 6.592mm aspect ratio 4:3 • Chip size: 6.10mm (H) × 4.95mm (V) • Unit cell size: 2.575µm (H) × 2.575µm (V) • Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels • Number of dummy bits: Horizontal 28 Vertical 1 (3rd field only) • Substrate material: Silicon ∗ Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (HoleAccumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony Corporation. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02122A27 ICX432DQ Vφ1 Vφ2 Vφ3A Vφ3B Vφ4 Vφ5A Vφ5B Vφ6 9 8 7 6 5 4 3 2 1 Vertical register GND Block Diagram and Pin Configuration (Top View) Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr Note) Horizontal register 14 VDD φRG GND φSUB 15 16 17 18 Hφ2 13 Hφ1 12 VL 11 CSUB 10 VOUT Note) : Photo sensor Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ6 Vertical register transfer clock 10 VOUT Signal output 2 Vφ5B Vertical register transfer clock 11 VDD Supply voltage 3 Vφ5A Vertical register transfer clock 12 φRG Reset gate clock 4 Vφ4 Vertical register transfer clock 13 GND GND 5 Vφ3B Vertical register transfer clock 14 φSUB 6 Vφ3A Vertical register transfer clock 15 CSUB Substrate clock Substrate bias ∗1 7 Vφ2 Vertical register transfer clock 16 VL Protective transistor bias 8 Vφ1 Vertical register transfer clock 17 Hφ1 Horizontal register transfer clock 9 GND GND 18 Hφ2 Horizontal register transfer clock ∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. –2– ICX432DQ Absolute Maximum Ratings Item Ratings Unit VDD, VOUT, φRG – φSUB –40 to +12 V Vφ1, Vφ3A, Vφ3B, Vφ5A, Vφ5B – φSUB –50 to +15 V Vφ2, Vφ4, Vφ6, VL – φSUB –50 to +0.3 V Hφ1, Hφ2, GND – φSUB –40 to +0.3 V CSUB – φSUB –25 to V VDD, VOUT, φRG, CSUB – GND –0.3 to +22 V Vφ1, Vφ2, Vφ3A, Vφ3B, Vφ4, Vφ5A, Vφ5B, Vφ6 – GND –10 to +18 V Hφ1, Hφ2 – GND –10 to +6.5 V Vφ1, Vφ3A, Vφ3B, Vφ5A, Vφ5B – VL –0.3 to +28 V Vφ2, Vφ4, Vφ6, Hφ1, Hφ2, GND – VL –0.3 to +15 V to +15 V Hφ1 – Hφ2 –6.5 to +6.5 V Hφ1, Hφ2 – Vφ6 –10 to +16 V Storage temperature –30 to +80 °C Guaranteed temperature of performance –10 to +60 °C Operating temperature –10 to +75 °C Against φSUB Against φGND Against φVL Voltage difference between vertical clock input pins Between input clock pins ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. –3– Remarks ∗1 ICX432DQ Bias Conditions Symbol Min. Typ. Max. Unit Supply voltage VDD 14.55 15.0 15.45 V Protective transistor bias VL ∗1 Substrate clock φSUB ∗2 Reset gate clock φRG ∗2 Item Remarks ∗1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Symbol Min. Typ. Max. Unit IDD 5.0 7.0 9.0 mA Supply current Remarks Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Reset gate clock voltage Waveform Diagram Min. Typ. Max. Unit VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 VVH3, VVH4 –0.05 0 0.05 V 2 VVH5, VVH6 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4, VVL5, VVL6 –8.0 –7.5 –7.0 V 2 VVL = (VVL5 + VVL6)/2 VφV 6.8 7.5 8.05 V 2 VφV = VVHn – VVLn (n = 1 to 6) Symbol Remarks VVH = (VVH1 + VVH2 + VVH3 + VVH4)/2 VVH5 – VVH –0.25 0.1 V 2 VVH6 – VVH –0.25 0.1 V 2 VVHH 0.8 V 2 High-level coupling VVHL 0.9 V 2 High-level coupling VVLH 0.9 V 2 Low-level coupling VVLL 0.8 V 2 Low-level coupling VφH 3.0 3.3 3.6 V 3 VHL –0.05 0 0.05 V 3 VCR 0.5 1.65 V 3 VφRG 3.0 3.3 3.6 V 4 VRGLH – VRGLL 0.4 V 4 Low-level coupling VRGL – VRGLm 0.5 V 4 Low-level coupling 23.5 V 5 Substrate clock voltage VφSUB 21.5 22.5 –4– Cross-point voltage ICX432DQ Clock Equivalent Circuit Constants Item Symbol Min. Typ. Max. Unit Remarks CφV1 1280 pF CφV3A, CφV3B, CφV5A, CφV5B 640 pF CφV2, CφV4, CφV6 400 pF CφV12 510 pF CφV23A, CφV23B, CφV45A, CφV45B 50 pF CφV3A4, CφV3B4, CφV5A6, CφV5B6 260 pF CφV61 100 pF Capacitance between horizontal transfer clock and GND CφH1, CφH2 40 pF Capacitance between horizontal transfer clocks CφHH 70 pF Capacitance between reset gate clock and GND CφRG 8 pF Capacitance between substrate clock and GND CφSUB 1000 pF R1, R2, R4, R6 60 Ω R3A, R5A 240 Ω R3B, R5B 80 Ω Vertical transfer clock ground resistor RGND 18 Ω Horizontal transfer clock series resistor RφH 13 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vertical transfer clock series resistor Vφ2 Vφ1 R1 CφV12 R2 CφV61 R6 CφV1 CφV6 Vφ6 R5B CφV5B RφH RφH CφHH Hφ1 Vφ3A CφV3A Hφ2 CφV23B CφV5A6 CφV5B6 Vφ5B CφV23A R3A CφV2 CφV3B RGND CφV4 CφH1 CφH2 R3B Vφ3B CφV5A CφV45B CφV3B4 CφV45A R5A Vφ5A CφV3A4 R4 Vφ4 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –5– ICX432DQ Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% φM VVT φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ2 VVH1 VVHH VVH VVH2 VVH VVHH VVHH VVHL VVHH VVHH VVHL VVHL VVHL VVHL VVL1 VVLH VVL2 VVLH VVLL VVLL VVL VVL Vφ3A, Vφ3B Vφ4 VVH3 VVHH VVH VVHH VVHH VVHH VVHL VVHL VVH VVHL VVH4 VVHL VVHL VVL3 VVLH VVL4 VVLH VVLL VVL VVL Vφ5A, Vφ5B VVLL Vφ6 VVHH VVHH VVHL VVH5 VVHH VVH VVHH VVHL VVHL VVH6 VVL5 VVLH VVH = (VVH1 + VVH2 + VVH3 + VVH4)/4 VVL = (VVL5 + VVL6)/2 VφV = VVHn – VVLn (n = 1 to 6) VVLL –6– VVHL VVL6 VVLH VVLL VVL VVH VVL ICX432DQ (3) Horizontal transfer clock waveform tr tf twh Hφ2 90% VCR VφH twl VφH 2 10% Hφ1 VHL two Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. (4) Reset gate clock waveform tr twh tf VRGH RG waveform twl VφRG Point A VRGLH VRGL VRGLL VRGLm VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval with twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM VφSUB 10% VSUB 0% (A bias generated within the CCD) tr twh –7– φM 2 tf ICX432DQ Clock Switching Characteristics (Horizontal drive frequency: 24.3MHz) twh Item Symbol 2.63 2.83 VT Vertical transfer clock Vφ1, Vφ2, Vφ3A, Vφ3B, Vφ4, Vφ5A, Vφ5B, Vφ6 tf 0.5 0.5 15 350 Hφ1 11 15 11 15 6.0 9.5 6.0 9.5 Hφ2 11 15 11 15 6.0 9.5 6.0 9.5 6 8 Reset gate clock φRG Substrate clock tr Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock Horizontal transfer clock twl φSUB 28 3 3 2.5 3.02 Item Symbol Horizontal transfer clock Hφ1, Hφ2 0.5 two Min. Typ. Max. 10 15 Unit Unit Remarks µs During readout ns When using CXD3400N ns tf ≥ tr – 2ns ns 0.5 µs During drain charge Remarks ns Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 G 0.9 R 0.8 Relative Response 0.7 B 0.6 0.5 0.4 0.3 0.2 0.1 0 400 450 500 550 Wave Length [nm] –8– 600 650 700 ICX432DQ Image Sensor Characteristics (horizontal drive frequency: 24.3MHz) (Ta = 25°C) Symbol Min. Typ. Max. Unit Measurement method G Sensitivity Sg 165 220 275 mV 1 Sensitivity comparison Rr 0.46 0.72 1 Rb 0.33 0.59 1 Saturation signal Vsat 420 Smear Sm Video signal shading SHg Dark signal Vdt Dark signal shading Item Remarks 1/30s accumulation mV 2 dB 3 % 4 10 mV 5 Ta = 60°C, 5.0 frame/s ∆Vdt 8 mV 6 Ta = 60°C, 5.0 frame/s, ∗2 Line crawl G Lcg 3.8 % 7 Line crawl R Lcr 3.8 % 7 Line crawl B Lcb 3.8 % 7 Lag Lag 0.5 % 8 –87.5 –80 –78 –70.5 20 25 Ta = 60°C Frame readout mode∗1 High frame rate readout mode Zone 0 and I Zone 0 to II' ∗1 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation. ∗2 Excludes vertical dark signal shading caused by vertical register high-speed transfer. Zone Definition of Video Signal Shading 2088 (H) 4 4 4 V 10 H 8 H 8 Zone 0, I 1550 (V) 4 Zone II, II' Ignored region Effective pixel region V 10 Measurement System CCD signal output [∗A] CCD C.D.S AMP S/H Gr/Gb channel signal output [∗B] S/H R/B channel signal output [∗C] Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1. –9– ICX432DQ Image Sensor Characteristics Measurement Method Measurement conditions (1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the frame readout mode is used. In addition, VSUB Cont. is turned off. (2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output or the R/B channel signal output of the measurement system. Color coding of this image sensor & Readout B2 B1 C2 Gb B Gb B R Gr R Gr Gb B Gb B A2 R Gr R Gr C1 Gb B Gb B R Gr R Gr The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. For three frames readout, the A1 and A2 lines are output as signals in the A field, the B1 and B2 lines in the B field, and the C1 and C2 lines in the C field. A1 Horizontal register Color Coding Diagram – 10 – ICX432DQ Readout modes 1. Readout modes list The following readout modes are possible by driving the image sensor at the timing specifications noted in this Data Sheet. Mode name Frame readout mode High frame rate readout mode AF mode Frame rate Number of effective output lines NTSC mode 5.0 frame/s 1550 (1st 517, 2nd 516, 3nd 517) PAL mode 5.0 frame/s 1550 (1st 517, 2nd 516, 3nd 517) NTSC mode 30 frame/s 258 PAL mode 25 frame/s 258 NTSC mode 60 frame/s 96 PAL mode 50 frame/s 123 2. Frame readout mode, high frame rate readout mode Frame readout mode 1st field VOUT 2nd field High frame rate readout mode 3rd field Gr 13 R Gr 13 R Gr 13 R Gr 13 R 12 Gb B 12 Gb B 12 Gb B 12 Gb B 11 R Gr 11 R Gr 11 R Gr 11 R Gr 10 Gb B 10 Gb B 10 Gb B 10 Gb B 9 R Gr 9 R Gr 9 R Gr 9 R Gr 8 Gb B 8 Gb B 8 Gb B 8 Gb B 7 R Gr 7 R Gr 7 R Gr 7 R Gr 6 Gb B 6 Gb B 6 Gb B 6 Gb B 5 R Gr 5 R Gr 5 R Gr 5 R Gr 4 Gb B 4 Gb B 4 Gb B 4 Gb B 3 R Gr 3 R Gr 3 R Gr 3 R Gr 2 Gb B 2 Gb B 2 Gb B 2 Gb B 1 R Gr 1 R Gr 1 R Gr 1 R Gr VOUT VOUT VOUT Note) Blacked out portions in the diagram indicate pixels which are not read out. 1. Frame readout mode In this mode, all pixel signals are divided into three fields and output. All pixel signals are read out independently, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode Output is performed at 30 frames per second by reading out 4 pixels for every 12 vertical pixels and adding 2 pixels in the horizontal CCD. The number of output lines is 258 lines. This readout mode emphasizes processing speed over vertical resolution. – 11 – ICX432DQ 3. AF The AF mode increases the frame rate by cutting out a portion of the picture through high-speed elimination of the top and bottom of the picture in high frame rate readout mode. This mode allows 1/60s and 1/50s output, so it is effective for raising the auto focus (AF) speed. In addition, the output line position and number of output lines are fixed. See the timing specifications for the cut-out region. Top frame shift region Cut-out region Bottom high-speed sweep region – 12 – Number of effective lines in high frame rate readout mode 258 ICX432DQ Definition of standard imaging conditions (1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. (3) Standard imaging condition III: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens (exit pupil distance –33mm) with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. G Sensitivity, sensitivity comparison Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGR, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb)/2 Sg = VG × 100 [mV] 30 Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. ( Sm = 20 × log Vsm ÷ Gra + Gba + Ra + Ba 1 1 × 500 × 4 10 – 13 – ) [dB] (1/10V method conversion value) ICX432DQ 4. Video signal shading Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjusting the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum value (Grmax [mV]) and minimum value (Grmin [mV]) of the Gr signal output and substitute the values into the following formula. SHg = (Grmax – Grmin)/150 × 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Line crawl Set to the standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = ∆Gli × 100 [%] (i = r, g, b) Gai 8. Lag Adjust the Gr signal output value generated by the strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) × 100 [%] VD V3A/V3B Light Strobe light timing Gr signal output 150mV Output – 14 – Vlag (lag) ICX432DQ Drive Circuit –7.5V 15V 3.3V 0.1 1/35V 1 20 XSUB 2 19 XV3 3 18 XSG3B 4 17 XSG3A 5 100k 0.1 16 CXD3400N XV5 6 15 XSG5B 7 14 XSG5A 8 13 XV4 9 12 XV2 10 11 1 20 2 19 3 18 4 17 0.1 3.3V 0.1 0.1 16 5 2SC4250 10 11 6 7 8 9 Vφ1 12 5 GND 13 9 4 Vφ2 8 XV6 3 Vφ3A XSG1 2 Vφ4 14 1 Vφ3B 7 0.1 Vφ5A 15 Vφ6 6 Vφ5B CXD3400N XV1 CCD OUT 4.7k ICX432DQ (BOTTOM VIEW) VOUT VDD φRG GND φSUB CSUB VL VR1 ( 3.9kΩ ) Hφ1 Hφ2 3.3/20V 0.01 18 17 16 15 14 13 12 11 10 VSUB Cont. Hφ2 Hφ1 φRG 0.1 Substrate bias control signal VSUB Cont. Substrate bias φSUB pin voltage 0.1 1M Mechanical shutter mode tf ≈ 17ms 3.3/16V 0.1 GND tr ≈ 2ms Internally generated value VSUB Notes) Substrate bias control 1. The saturation signal level decreases when exposure is performed using the mechanical shutter, so control the substrate bias. 2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting a VR1 grounding registor to the CCD CSUB pin. Drive timing precautions 1. Blooming occurs in modes (high frame rate readout, etc.) that do not use the mechanical shutter, so do not ground the connected VR1 resistor. 2. tf is slow, so the internally generated voltage VSUB may not drop to a sufficiently low level if the substrate bias control signal is not set to high level 30ms before entering the exposure period and the VR1 resistor connected to the CSUB pin is not grounded. 3. The blooming signal generated during exposure in mechanical shutter mode is swept by providing two fields or more of idle transfer through vertical register high-speed sweep transfer from the time the mechanical shutter closes until sensor readout is performed. However, note that the VL potential and the φSUB pin DC voltage sag at this time. – 15 – – 16 – A signal output B B signal output OPEN B B signal output C Exposure operation C signal output (1st) CLOSE C signal output (2nd) Frame readout mode C signal output (3rd) Output after frame readout E E signal output High frame rate readout mode High Frame Rate Readout Mode → Frame Readout Mode/Electronic Shutter Normal Operation Note) High frame rate readout mode out signals of VSUB Cont. high period contain a blooming component and should therefore not be used. Apply 20 or more electronic shutter pulses at the start of exposure for the recording image. If less than 20 pulses are applied, the electronic shutter may occur a discharge error. CCD OUT VSUB Cont. Mechanical shutter TRG SUB V6 V5B V5A V4 V3B V3A V2 V1 VD High frame rate readout mode Drive Timing Chart (Vertical Sequence) ICX432DQ – 17 – PAL CLOSE 1 1 OPEN 9 9 "a" 41 41 "b" 44 44 NTSC 1410 1176 Note) 2760fH, however, 588H, 1176H and 1764H in NTSC mode are 1500clk, 705H, 1410H and 2115H in PAL mode are 960clk. CCD OUT VSUB Cont. Mechanical shutter TRG SUB V6 V5B V5A V4 V3B V3A V2 V1 564 564 HD Exposure period 588 705 1 4 7 2 5 8 629 746 1547 1550 632 749 2 5 8 3 6 9 VD 1269 1152 1545 1548 NTSC/PAL Frame Readout Mode NTSC: 5.0 frame/s, PAL: 5.0 frame/s 1451 1217 "c" 1975 1741 1546 1549 Drive Timing Chart (Vertical Sync) ICX432DQ 2115 1764 3 6 1 4 1454 1220 – 18 – V2 V1 H1 V6 V5A/V5B V4 V3A/V3B NTSC 632H PAL 749H "b" Enlarged V6 V5A/V5B V4 V3A/V3B V2 V1 644 644 2760 1 2760 1 H1 1420 1380 1460 1338 1420 1546 1502 1380 1460 1338 1254 1296 1 1 NTSC 44H PAL 44H 2760 2760 "a" Enlarged 52 52 NTSC/PAL Frame Readout Mode 224 266 392 602 518 434 560 350 476 308 602 518 434 560 350 476 392 308 644 644 Drive Timing Chart (Readout) ICX432DQ 52 V2 V1 H1 – 19 – V6 V5A/V5B V4 V3A/V3B NTSC 1220H PAL 1454H "c" Enlarged 1170 1086 1296 1212 1338 1128 1254 NTSC/PAL Frame Readout Mode 644 2760 1 Drive Timing Chart (Readout) 1380 1460 1420 644 602 518 560 476 ICX432DQ 52 2760 1 52 – 20 – #1 #2 #3 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 #1040 18 18 18 18 18 18 NTSC/PAL Frame Readout Mode 52 1 52 1 Note) In the period of high-speed sweep operation, the rising of input clocks XV1, XV2, XV3, XV4, XV5 and XV6 to vertical transfer clock driver CD3400N should be delayed by 1 clock against the above timing chart. V6 V5A/V5B V4 V3A/V3B V2 V1 HD 140 Drive Timing Chart (High-speed Sweep Operation) ICX432DQ – 21 – 2760 SUB 1 1 V6 1 1 1 Ignored pixel 4 bits 1 V5A/V5B H2 88 1 172 1 214 1 126 1 298 1 126 1 382 1 126 1 378 1 126 1 378 1 83 42 126 84 168 252 336 5 1 1 52 48 1 H1 88 1 130 NTSC/PAL Frame Readout Mode 644 592 V4 V3A/V3B V2 V1 SHD SHP RG CLK 1 Drive Timing Chart (Horizontal Sync) 4 28 4 Ignored pixel 4 bits ICX432DQ 1 CCD OUT V6 V5B V5A V4 324 270 1549 Note) 3004fH, however, 270H in NTSC mode is 2734fH, 324H in PAL mode is 1708fH. 1534 1532 V3B 1541 1537 263 263 1546 1544 V3A 6 4 V2 5 1 V1 10 8 PAL 17 13 NTSC 22 20 HD 29 25 VD 34 32 1 1529 1525 1 1534 1532 9 1541 1537 263 263 1546 1544 9 NTSC/PAL High Frame Rate Readout Mode NTSC: 30 frame/s, PAL: 25 frame/s 6 4 1 5 1 1 10 8 4 17 4 22 13 9 29 20 9 34 25 – 22 – 32 Drive Timing Chart (Vertical Sync) ICX432DQ 324 270 1549 – 23 – V6 V5B V5A V4 V3B V3A V2 V1 H1 1704 1784 1744 1877 1815 1815 1469 1908 1846 1642 1642 1407 1580 1673 1846 1500 1540 1611 1407 1438 NTSC/PAL High Frame Rate Readout Mode/AF Mode 888 52 1 Drive Timing Chart (Readout Portion) 1 1 1 1 1 1 1 1 ICX432DQ 888 52 3004 1 SUB H2 H1 V6 V5A/V5B V4 V3A/V3B V2 V1 SHD SHP RG 88 119 1 181 93 1 93 1 93 1 93 1 279 1 279 93 1 1 Ignored pixel 4 bits 1 1 1 1 1 1 83 88 1 150 1 1 243 1 305 1 279 1 279 1 93 1 93 1 1 93 1 279 1 93 1 279 1 93 1 279 1 279 35 97 66 128 190 252 5 1 1 52 48 5 CLK 3004 3004 NTSC/PAL High Frame Rate Readout Mode/AF Mode 888 836 52 – 24 – 1 1 Drive Timing Chart (Horizontal Sync) 4 28 4 Ignored pixel 4 bits ICX432DQ 1 1 1 162 135 150 123 High-speed sweep period AF mode output signal NTSC 96 lines PAL 123 lines Note) 3004fH, however, 135H in NTSC mode is 2869clk, and 162H in PAL mode is 2356clk. CCD OUT V6 V5B V5A V4 V3B 4 4 Frame shift period 6 V3A 9 9 Frame shift period 25 25 High-speed sweep period 28 28 4 V2 PAL 150 123 485 490 V1 162 135 481 488 NTSC 1 1 HD 4 4 6 – 25 – 4 VD 9 9 AF Mode NTSC: 60 frame/s, PAL: 50 frame/s 25 25 Drive Timing Chart (Vertical Sync) ICX432DQ – 26 – V6 V5A/V5B V4 V3A/V3B V2 V1 HD 1 140 62 62 #1 279 93 279 31 279 93 279 93 217 93 279 93 155 93 279 93 124 93 279 93 186 93 93 279 93 248 31 #2 Drive Timing Chart (High-speed Frame Shift Operation) AF mode 20H NTSC/PAL AF Mode AF: #78 1 140 ICX432DQ – 27 – V6 V5A/V5B V4 V3A/V3B V2 V1 HD 1 140 24 24 #1 108 36 108 12 108 36 108 36 84 36 108 36 60 36 108 36 48 36 108 36 72 36 36 108 36 96 12 #2 AF mode 11H Drive Timing Chart (High-speed Frame Sweep Operation) NTSC/PAL AF Mode AF: #114 1 140 ICX432DQ ICX432DQ Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Cover glass 50N 50N 1.2Nm Plactic package Compressive strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. – 28 – ICX432DQ c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. – 29 – – 30 – 0.5g PACKAGE MASS AS-C14-02(E) 42 ALLOY LEAD MATERIAL DRAWING NUMBER GOLD PLATING M 0.30 ± 0.15 0.38 0.46 7.0 9 10 2.5 8.9 10.0 ± 0.10 H LEAD TREATMENT 0.3 1.11 1 V Plastic 0.6 5.0 PACKAGE MATERIAL B 18 5.0 A B' 10.0 ± 0.10 Unit: mm 8.9 0.6 2.5 2.5 7.0 2.3 9 1.7 1 18 9. The notch of the package is used only for directional index, that must not be used for reference of fixing. 8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 25µm. The tilt of the effective image area relative to the top “D” of the cover glass is less than 25µm. 6. The height from the bottom “C” to the effective image area is 1.20 ± 0.10mm. The height from the top of the cover glass “D” to the effective image area is 1.30 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 0.8˚ 4. The center of the effective image area relative to “B” and “B'” is (H, V) = (5.0, 5.0) ± 0.07mm. 3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference. 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 1. “A” is the center of the effective image area. D C 1.7 10 18 pin DIP (400mil) ˚ 2.0 o9 2.50 ± 0.15 3.50 ± 0.3 0 ˚t 0.25 Package Outline ICX432DQ Sony Corporation 10.16