ICX267AL
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras
Description
The ICX267AL is a diagonal 8mm (Type 1/2) interline
CCD solid-state image sensor with a square pixel array
and 1.45M effective pixels. Progressive scan allows all
pixels' signals to be output independently. Also, the
adoption of high frame rate readout mode supports
30 frames per second. This chip features an electronic
shutter with variable charge-storage time which
makes it possible to realize full-frame still image
without a mechanical shutter. High resolution and
high low dark current are achieved through the
adoption of HAD (Hole-Accumulation Diode)
sensors.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
Features
• Progressive scan allows individual readout of the
image signals from all pixels.
• High horizontal and vertical resolution (both approx.
1024TV-lines) still image without a mechanical
shutter.
• Supports high frame rate readout mode
(effective 512 lines output, 30 frames/s)
• Square pixel
• Horizontal drive frequency: 28.636MHz
• No voltage adjustments
(reset gate and substrate bias are not adjusted.)
• High resolution, high color reproductivity,
high sensitivity, low dark current
• Low smear, excellent antiblooming characteristics
• Continuous variable-speed shutter
20 pin DIP (Plastic)
Pin 1
2
V
8
2
Pin 11
H
40
Optical black position
(Top view)
Device Structure
• Interline CCD image sensor
• Image size:
Diagonal 8mm (Type 1/2)
• Total number of pixels:
1434 (H) × 1050 (V) approx. 1.50M pixels
• Number of effective pixels: 1392 (H) × 1040 (V) approx. 1.45M pixels
• Number of active pixels: 1360 (H) × 1024 (V) approx. 1.40M pixels (7.959mm diagonal)
• Chip size:
7.60mm (H) × 6.20mm (V)
• Unit cell size:
4.65µm (H) × 4.65µm (V)
• Optical black:
Horizontal (H) direction: Front 2 pixels, rear 40 pixels
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
• Number of dummy bits:
Horizontal 20
Vertical 3
• Substrate material:
Silicon
∗ Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01Y03B43
ICX267AL
USE RESTRICTION NOTICE (December 1, 2003 ver.)
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD
products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify
this Notice which will be available to you in the latest specifications book for the Products. You should abide by
the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the
Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You
should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice
when you consider using the Products.
Use Restrictions
• The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with the
terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time.
• You should not use the Products for critical applications which may pose a life- or injury- threatening risk or
are highly likely to cause significant property damage in the event of failure of the Products. You should
consult your Sony sales representative beforehand when you consider using the Products for such critical
applications. In addition, you should not use the Products in weapon or military equipment.
• Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
Design for Safety
• Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to
ensure the safe design of your products such as component redundancy, anti-conflagration features, and
features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social
damage as a result of such failure.
Export Control
• If the Products are controlled items under the export control laws or regulations of various countries, approval
may be required for the export of the Products under the said laws or regulations. You should be responsible
for compliance with the said laws or regulations.
No License Implied
• The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise. Sony
will not assume responsibility for any problems in connection with your use of such information or for any
infringement of third-party rights due to the same. It is therefore your sole legal and financial responsibility to
resolve any such problems and infringement.
Governing Law
• This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to
principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this
Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the court of first
instance.
Other Applicable Terms and Conditions
• The terms and conditions in the Sony additional specifications, which will be made available to you when you
order the Products, shall also be applicable to your use of the Products as well as to this specifications book.
You should review those terms and conditions when you consider purchasing and/or using the Products.
–2–
ICX267AL
GND
NC
NC
Vφ3
Vφ2B
Vφ2A
Vφ1
8
7
6
5
4
3
2
1
...
...
...
NC
9
...
GND
10
Vertical register
VOUT
Block Diagram and Pin Configuration
(Top View)
Note)
Note)
: Photo sensor
17
NC
VL
18
19
20
Hφ2
16
Hφ1
15
φRG
14
CSUB
GND
13
NC
12
φSUB
11
VDD
Horizontal register
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
Vφ1
Vertical register transfer clock
11
VDD
Supply voltage
2
Vφ2A
Vertical register transfer clock
12
GND
GND
3
Vφ2B
Vertical register transfer clock
13
φSUB
Substrate clock
4
Vφ3
Vertical register transfer clock
14
NC
5
NC
15
CSUB
6
NC
16
NC
7
GND
17
VL
Protective transistor bias
8
NC
18
φRG
Reset gate clock
9
GND
GND
19
Hφ1
Horizontal register transfer clock
10
VOUT
Signal output
20
Hφ2
Horizontal register transfer clock
GND
Substrate bias∗1
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
–3–
ICX267AL
Absolute Maximum Ratings
Item
Against φSUB
Against GND
Against VL
Ratings
Unit
VDD, VOUT, φRG – φSUB
–40 to +10
V
Vφ2A, Vφ2B – φSUB
–50 to +15
V
Vφ1, Vφ3, VL – φSUB
–50 to +0.3
V
Hφ1, Hφ2, GND – φSUB
–40 to +0.3
V
CSUB – φSUB
–25 to
V
VDD, VOUT, φRG, CSUB – GND
–0.3 to +18
V
Vφ1, Vφ2A, Vφ2B, Vφ3 – GND
–10 to +18
V
Hφ1, Hφ2 – GND
–10 to +15
V
Vφ2A, Vφ2B – VL
–0.3 to +28
V
Vφ1, Vφ3, Hφ1, Hφ2, GND – VL
–0.3 to +15
V
Voltage difference between vertical clock input pins
Between input
Hφ1 – Hφ2
clock pins
Hφ1, Hφ2 – Vφ3
to +15
V
–16 to +16
V
–16 to +16
V
Storage temperature
–30 to +80
°C
Operating temperature
–10 to +60
°C
∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed for turning on or off power supply.
–4–
Remarks
∗1
ICX267AL
Bias Conditions
Symbol
Item
Min.
Typ.
Max.
Unit
14.55
15.0
15.45
V
Power Supply voltage
VDD
Protective transistor bias
VL
∗1
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
Remarks
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Symbol
Power supply current
Min.
IDD
Typ.
Max.
Unit
7.7
Remarks
mA
Clock Voltage Conditions
Min.
Typ.
Max.
Unit
Waveform
diagram
VVT
14.55
15.0
15.45
V
1
VVH02A
–0.05
0
0.05
V
2
VVH1, VVH2A,
VVH2B, VVH3
–0.2
0
0.05
V
2
VVL1, VVL2A,
VVL2B, VVL3
–8.4
–8.0
–7.6
V
2
Vφ1, Vφ2A,
Vφ2B, Vφ3
7.6
8.0
8.4
V
2
| VVL1 – VVL3 |
0.1
V
2
VVHH
0.9
V
2
High-level coupling
VVHL
1.3
V
2
High-level coupling
VVLH
1.0
V
2
Low-level coupling
VVLL
0.9
V
2
Low-level coupling
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Symbol
VVH = VVH02A
VVL = (VVL1 + VVL3)/2
VφH
4.75
5.0
5.25
V
3
VHL
–0.05
0
0.05
V
3
3.0
3.3
5.5
V
4
VRGLH – VRGLL
0.4
V
4
Low-level coupling
VRGL – VRGLm
0.5
V
4
Low-level coupling
23.85
V
5
VφRG
Reset gate clock
voltage
Remarks
Substrate clock voltage VφSUB
22.15
23.0
–5–
ICX267AL
Clock Equivalent Circuit Constant
Item
Symbol
Min.
Max.
Unit Remarks
2200
pF
3300
pF
3300
pF
CφV3
3300
pF
CφV12A, CφV2B1
1200
pF
CφV2A3, CφV32B
1200
pF
CφV13
2200
pF
CφV1
Capacitance between vertical transfer clock and CφV2A
GND
CφV2B
Capacitance between vertical transfer clocks
Typ.
Capacitance between horizontal transfer clock
and GND
CφH1, CφH2
47
pF
Capacitance between horizontal transfer clocks
CφHH
100
pF
8
pF
CφSUB
680
pF
R1
36
Ω
R2A, R3
56
Ω
R2B
56
Ω
Vertical transfer clock ground resistor
RGND
30
Ω
Horizontal transfer clock series resistor
RφH
15
Ω
Reset gate clock series resistor
RφRG
20
Ω
Capacitance between reset gate clock and GND CφRG
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vφ2A
Vφ1
CφV12A
R1
R2A
RφH
RφH
Hφ1
CφV1
Hφ2
CφHH
CφV2A
CφV2B1
CφV2A3
CφH1
CφH2
CφV13
CφV2B
R2B
RGND
CφV3
R3
CφV32B
Vφ2B
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
RφRG
RGφ
CφRG
Reset gate clock equivalent circuit
–6–
ICX267AL
Drive Clock Waveform Conditions
(1) Readout clock waveform
VT
100%
90%
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B.
(2) Vertical transfer clock waveform
Vφ1
VVH1
VVHH
VVH
VVHL
VVLH
VVL01
VVL1
VVL
VVLL
Vφ2A, Vφ2B
VVH02A, VVH02B
VVH2A, VVH2B
VVHH
VVH
VVHL
VVLH
VVL2A, VVL2B
VVL
VVLL
VVH3
Vφ3
VVHH
VVH
VVHL
VVLH
VVL03
VVL
VVLL
VVH = VVH02A
VVL = (VVL01 + VVL03)/2
VVL3 = VVL03
VφV1 = VVH1 – VVL01
VφV2A = VVH02A – VVL2A
VφV2B = VVH02B – VVL2B
VφV3 = VVH3 – VVL03
–7–
ICX267AL
(3) Horizontal transfer clock waveform
tr
twh
tf
Hφ2
90%
VCR
VφH
twl
VφH
2
10%
VHL
Hφ1
two
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr
twh
tf
VRGH
RG waveform
twl
VφRG
Point A
VRGLH
VRGL
VRGLL
VRGLm
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL.
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
VφSUB
10%
VSUB
0%
(A bias generated within the CCD)
tr
twh
–8–
φM
2
tf
ICX267AL
Clock Switching Characteristics
twh
Symbol
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Readout clock
VT
Vertical transfer
clock
Vφ1, Vφ2A,
Vφ2B, Vφ3
Horizontal
transfer clock
Item
Hφ1
10 12.5
10 12.5
5
7.5
5
7.5
Hφ2
10 12.5
10 12.5
5
7.5
5
7.5
During
imaging
3.2 3.4
0.5
15
During
Hφ1
parallel-serial
Hφ2
conversion
Reset gate clock
φRG
Substrate clock
φSUB
0.5
4
8
24
0.01
0.01
0.01
3.9
µs
450 ns
0.01
2
ns
Remarks
During
readout
∗1
∗2
µs
ns
2
0.5
Unit
0.5
µs
When draining
charge
∗1 When vertical transfer clock driver CXD1267AN × 2 is used.
∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must
be at least VφH/2 [V].
two
Symbol
Item
Horizontal transfer clock
Hφ1, Hφ2
Min.
Typ.
8
10
Max.
Unit Remarks
ns
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
1.0
Relative Response
0.8
0.6
0.4
0.2
0
400
500
600
700
Wave Length [nm]
–9–
800
900
1000
ICX267AL
Image Sensor Characteristics
Item
Sensitivity
Saturation signal
(Ta = 25°C)
Unit
Measurement
method
mV
1
450
mV
2
Vsat2
380
mV
2
Vsat4
380
mV
2
Symbol
Min.
Typ.
S
360
450
Vsat
Sm
Smear
Max.
Remarks
1/30s accumulation
Progressive scan
readout mode
High frame rate
Ta = 60°C readout mode
High frame rate
readout two pixels
addition∗1
0.001
0.0025
%
3
Progressive scan readout,
high frame rate readout two
pixels addition
0.002
0.005
%
3
High frame rate readout mode
20
%
4
Zone 0 and I
25
%
4
Zone 0 to I '
Ta = 60°C, 15 frames/s
Ta = 60°C, 15 frames/s∗2
Video signal shading SHg
Dark signal
Vdt
8
mV
5
Dark signal shading
∆Vdt
2
mV
6
Lag
Lag
0.5
%
7
∗1 Vsat4 is the saturation signal amount at two pixels addition, and it is 190mV per one pixel. VSUB internal
generation value ensures 190mV per one pixel of the saturation signal amount in high frame rate two pixels
addition mode.
∗2 Eliminates the dark signal shading in the vertical direction by the high-speed transfer of the vertical
register.
Zone Definition of Video Signal Shading
1392 (H)
16
16
8
H
8
V
10
H
8
Zone 0, I
1040 (V)
8
Zone II, II'
V
10
Ignored region
Effective pixel region
Measurement System
CCD signal output [∗A]
CCD
C.D.S
AMP
S/H
Signal output [∗B]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B] equals 1.
– 10 –
ICX267AL
Image Sensor Characteristics Measurement Method
Readout modes
The diagram below shows the output methods for the following three readout modes.
Progressive scan mode
High frame rate readout mode
9 (V2A)
9 (V2A)
9 (V2A)
8 (V2B)
8 (V2B)
8 (V2B)
7 (V2B)
7 (V2B)
7 (V2B)
6 (V2A)
6 (V2A)
6 (V2A)
5 (V2A)
5 (V2A)
5 (V2A)
4 (V2B)
4 (V2B)
4 (V2B)
3 (V2B)
3 (V2B)
3 (V2B)
2 (V2A)
2 (V2A)
2 (V2A)
1 (V2A)
VOUT
High frame rate readout two pixels
addition mode
1 (V2A)
1 (V2A)
VOUT
VOUT
1. Progressive scan mode
In this mode, all pixels signals are output in non-interlace format in 1/15s.
The vertical resolution is approximately 800 TV-lines and all pixels signals within the same exposure period
are read out simultaneously, making this mode suitable for high resolution image capturing.
2. High frame rate readout mode
All effective areas are scanned in approximately 1/30s by reading out two out of four lines (3rd and 4th
lines, 7th and 8th lines). The vertical resolution is approximately 400 TV-lines.
This readout mode emphasizes processing speed over vertical resolution.
3. High frame rate readout two pixels addition mode
All effective areas are scanned in approximately 1/30s by reading out two out of four lines (3rd and 4th
lines, 7th and 8th lines), and by reading out two out of the remaining four lines (1st and 2nd lines, 5th and
6th lines) after shifting the vertical register by 2 bits, and adding them in the vertical register.
– 11 –
ICX267AL
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the progressive scan
mode, bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black (OB) level is used as the reference for the signal output, and the value measured at point [*B] in the
measurement system is used.
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut
filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the
standard sensitivity testing luminous intensity.
2) Standard imaging condition I :
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s,
measure the signal output (Vs) at the center of the screen, and substitute the values into the following
formulas.
S = Vs × 250 [mV]
30
2. Saturation signal
Set to standard imaging condition I . After adjusting the luminous intensity to 10 times the intensity with the
average value of the signal output, 150mV, measure the minimum value of the signal output.
3. Smear
Set to standard imaging condition I . With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with the average value of the signal output, 150mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value (Vsm [mV]) of the signal output and substitute the value into the following formula.
Sm = 20 × log
1
1
VSm
×
×
500
10
150
[dB] (1/10V method conversion value)
4. Video signal shading
Set to standard imaging condition I . With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the signal output is 150mV. Then measure the maximum (Vrmax [mV]) and
minimum (Vrmin [mV]) values of the signal output and substitute the values into the following formula.
SH = (Vrmax – Vrmin)/150 × 100 [%]
– 12 –
ICX267AL
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
7. Lag
Adjust the signal output value generated by strobe light to 150mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/150) × 100 [%]
VD
V2A
Light
Strobe light timing
signal output 150mV
Output
– 13 –
Vlag (lag)
– 14 –
22/20V
5
12
11
20
19
18
17
16
9
10
1
2
3
4
5
14
13
12
11
7
8
9
10
15
13
8
6
14
7
CXD1267AN
16
4
15
17
3
CXD1267AN
18
2
6
20
19
1
1/35V
100k
0.1
0.1
Note) Substrate bias control
1. Connect the ground resistor (VR1) shown below to the CSUB pin by each readout mode
in order to secure the saturation signal described on the image sensor characteristics.
・Progressive scan readout mode
: 2.0kΩ
・High frame rate readout mode
: 3.8kΩ
・High frame rate 2 pixels addition mode: Ground resistor should not be connected.
2. If the substrate bias control signal is set to high level, and the ground resistor (VR1) connected
to CSUB pin is not grounded at 55ms before the exposure time starts because tf is late, the internal
generation voltage (VSUB) may not fall enough.Substrate bias adjustment control signal VSUB Cont.
RG
H1
H2
XV2B
XSG2
XV3
XSUB
XSG1
XV2A
XV1
15V
–8.0V
Substrate bias
φSUB pin voltage
Substrate bias
adjustment control
signal VSUB Cont.
tf ≈ 45ms
22/16V
1
2
3
4
5
6
7
8
9
10
ICX267
(Bottom View)
Vφ1
Vφ2A
Vφ2B
Vφ3
NC
NC
GND
NC
GND
VOUT
tr ≈ 1ms
3.9k
VSUB CONT.
0.01
CCD OUT
2SK523
100
← Internal generation value VSUB
(VSUB in high frame rate readout
two pixels addition mode)
← GND
1M 0.1 2200P
VR1 (1.3K)
22/20V
Hφ2
Hφ1
φRG
VL
NC
CSUB
NC
φSUB
GND
VDD
20
19
18
17
16
15
14
13
12
11
Drive Circuit
ICX267AL
– 15 –
V3
V2B
V2A
V1
HD
XSG2
XSG1
XV3
XV2A/XV2B
XV1
69.5ns (2 bits)
3.49µs (100 bits)
The sensor readout clocks XSG1 and XSG2 are added to each XV2A and XV2B.
Progressive Scan Mode
27.9µs (800 bits)
Sensor Readout Clock Timing Chart
ICX267AL
– 16 –
V3
V2B
V2A
V1
HD
XSG2
XSG1
XV3
XV2A/XV2B
XV1
69.5ns (2 bits)
3.49µs (100 bits)
The sensor readout clock XSG2 is added to XV2B.
High Frame Rate Readout Mode
27.9µs (800 bits)
Sensor Readout Clock Timing Chart
5.86µs (168 bits)
ICX267AL
– 17 –
V3
V2B
V2A
V1
HD
XSG2
XSG1
XV3
XV2A/XV2B
XV1
69.5ns (2 bits)
2
98 28 28 28 28 28 28 28 28 28 28 28 28 28 28 2
3.49µs (100 bits)
98
5.86µs (168 bits)
The sensor readout clocks XSG1 and XSG2 are added to each XV2A and XV2B.
17.15µs (492 bits)
High Frame Rate Readout Two Pixels Addition Mode
27.9µs (800 bits)
Sensor Readout Clock Timing Chart
ICX267AL
– 18 –
CCD
OUT
V3
V2B
V2A
V1
HD
VD
Progressive Scan Mode
21
13
12
10
11
8
9
6
7
5
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10
1052
1038
1039
1040
4
1063
1040
Drive Timing Chart (Vertical Sync)
1 2 3 4 5 6 7 8 1 2 3 4 5
ICX267AL
1
1068
1063
1044
2
3
1
1068
– 19 –
CCD
OUT
Vφ3
Vφ2B
Vφ2A
Vφ1
HD
VD
1/30s
Drive Timing Chart (Vertical Sync)
531
532
533
534
1
2
3
4
5
6
7
8
3
4
7
8
3
4
7
8
11
12
15
16
High Frame Rate Readout Mode
1035
1036
1039
1040
523
524
525
526
527
528
529
530
531
532
533
534
1
2
3
4
5
6
7
8
3
4
7
8
3
4
7
8
11
12
15
16
1/30s
523
524
525
526
527
528
529
530
531
532
533
534
1
2
3
4
5
6
7
8
1035
1036
1039
1040
3
4
7
8
3
4
7
8
11
12
15
16
ICX267AL
CCD
OUT
Vφ3
Vφ2B
Vφ2A
Vφ1
HD
3
4
7
8
3
4
7
8
11
12
15
16
1
2
5
6
1
2
5
6
9
10
13
14
VD
1035
1036
1039
1040
1033
1034
1037
1038
531
532
533
534
1
2
3
4
5
6
7
8
1/30s
3
4
7
8
3
4
7
8
11
12
15
16
1
2
5
6
1
2
5
6
9
10
13
14
523
524
525
526
527
528
529
530
531
532
533
534
1
2
3
4
5
6
7
8
1/30s
High Frame Rate Readout Two Pixels Addition Mode
1035
1036
1039
1040
1033
1034
1037
1038
Drive Timing Chart (Vertical Sync)
3
4
7
8
3
4
7
8
11
12
15
16
1
2
5
6
1
2
5
6
9
10
13
14
– 20 –
523
524
525
526
527
528
529
530
531
532
533
534
1
2
3
4
5
6
7
8
ICX267AL
– 21 –
RGφ
1
1
1
1
SUB
16
1
56
Vφ3
Vφ2B
Vφ2A
Vφ1
Hφ2
Hφ1
CLK
1
1790
1
HD
96
56
56
1
1
112 1
Progressive Scan Mode
168 1
188 1
168 1
168 1
1
112 1
392
36
56
112
112
168
2
430
Drive Timing Chart (Horizontal Sync)
ICX267AL
412
– 22 –
RGφ
1
1
1
1
SUB
16
1
56
Vφ3
Vφ2B
Vφ2A
Vφ1
Hφ2
Hφ1
CLK
1
1790
1
HD
28
28
1
1
96
56
1
84
1
84
84
1
1
84
1
84
High Frame Rate Readout Mode
1
188
1
84
84
1
1
84
1
84
1
84
84
1
1
112
1
84
1
392
36
28
56
56
84
2
430
Drive Timing Chart (Horizontal Sync)
ICX267AL
412
– 23 –
RGφ
1
1
1
1
SUB
16
1
56
Vφ3
Vφ2B
Vφ2A
Vφ1
Hφ2
Hφ1
CLK
1
1790
1
HD
28
28
1
1
96
56
1
84
1
84
84
1
1
84
1
84
1
188
1
84
84
1
1
84
1
High Frame Rate Readout Two Pixels Addition Mode
84
1
84
84
1
1
112
1
84
1
392
36
28
56
56
84
2
430
Drive Timing Chart (Horizontal Sync)
ICX267AL
412
ICX267AL
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load
more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to
limited portions. (This may cause cracks in the package.)
Cover glass
50N
50N
1.2Nm
Plastic package
Compressive strength
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and
the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 24 –
ICX267AL
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to the other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-acrylate
instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition
exceeding the normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
– 25 –
B
– 26 –
2.5
0.5
1.27
~
~
12.7
0.95g
AS-B6-04(E)
DRAWING NUMBER
42 ALLOY
PACKAGE MASS
LEAD MATERIAL
GOLD PLATING
LEAD TREATMENT
M
Plastic
0.3
10.0
13.8 ± 0.1
H
PACKAGE MATERIAL
1
V
20
6.9
~
2.5
10
11
A
10.9
0.3
0.8
2.5
9.0
PACKAGE STRUCTURE
0.8
6.0
D
20 pin DIP
B'
12.0 ± 0.1
0.5
2.4
Unit: mm
2.9 ± 0.15
3.5 ± 0.3
C
0˚ to 9˚
1.7
10
11
1.7
1.7
12.2
1
20
1.7
9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.49 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1˚.
4. The center of the effective image area relative to “B” and “B'”
is (H, V) = (6.9, 6.0) ± 0.075mm.
3. The bottom “C” of the package, and the top of the cover glass “D”
are the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
0.25
Package Outline
ICX267AL
Sony Corporation