ILX505A
2592-pixel CCD Linear Image Sensor (B/W)
For the availability of this product, please contact the sales office.
Description
The ILX505A is a reduction type CCD linear sensor
designed for facsimile, image scanner and OCR use.
This sensor reads A3 size documents at a density of
200 DPI (Dot Per Inch). A built-in timing generator
and clock-drivers ensure direct drive at 5V logic for
easy use.
22 pin DIP (Ceramic)
Features
• Number of effective pixels: 2592 pixels
• Pixel size: 11µm × 11µm (11µm pitch)
• Built-in timing generator and clock-drivers
• Ultra low lag
• High sensitivity
• Maximum clock frequency: 5MHz
Absolute Maximum Ratings
• Supply voltage
VDD1
VDD2
• Operating temperature
• Storage temperature
11
6
–10 to +55
–30 to +80
V
V
°C
°C
Pin Configuration (Top View)
22 VDD2
VOUT
1
GND
2
21 NC
GND
3
20 VDD1
SHSW
4
19 RSSW
φCLK
5
18 VGG
VDD1
6
17 GND
GND
7
16 GND
VDD2
8
15 VDD1
T1
9
14 NC
1
13 NC
EXRS 10
φROG 11
2592
12 GND
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E92Y22D78-PS
D15
S2
11
4
10
19
5
9
8
7
6
VDD1
3
GND
2
GND
Read out gate
pulse generator
GND
Mode
selector
Clock-drivers
12
VDD2
Clock pulse generator
Sample-and-hold pulse
generator
S2591
CCD analog shift register
13
D34
T1
VGG 18
VDD2
AAAA
AA
14
VDD1
Read out gate
NC
15
D35
φCLK
Output amplifier
Sample-and-hold
circuit
16
17
D38
RSSW
1
20
NC
21
D37
EXRS
VOUT
VDD1
D14
GND
D33
GND
S1
NC
S2592
GND
D36
22
D39
SHSW
–2–
φROG
Block Diagram
ILX505A
ILX505A
Pin Description
Pin No.
Symbol
Description
1
VOUT
Signal output
2
GND
GND
3
GND
GND
4
SHSW
Switch
5
φCLK
Clock pulse
6
VDD1
9V power supply
7
GND
GND
8
VDD2
5V power supply
9
T1
Test pin (VDD2)
10
EXRS
External RS pulse input. Must be connected to
VDD2 when the internal RS pulse is used.
11
φROG
Clock pulse
12
GND
GND
13
NC
NC
14
NC
NC
15
VDD1
9V power supply
16
GND
GND
17
GND
GND
18
VGG
Output circuit gate bias
19
RSSW
Reset pulse switchover pin
20
VDD1
9V power supply
21
NC
NC
22
VDD2
5V power supply
{
with S/H → GND
without S/H → VDD2
–3–
ILX505A
Mode Description
Mode in Use
19 pin RSSW 10 pin EXRS
Internal RS
GND
VDD2
Externel RS
VDD2
φRS
Note) When the external RS mode is in use, operation of use internal S/H is not guaranteed. Pin 4 must be
connected to 5V DC power supply.
Recommended Voltage
Item
Min.
Typ.
Max.
Unit
VDD1
8.5
9.0
9.5
V
VDD2
4.75
5.0
5.25
V
Note) Rules for raising and lowering power supply voltage
To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
–4–
ILX505A
Electro-optical Characteristics
(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency: 1MHz,
Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)),
When Internal RS (Pin 19 = GND, Pin 10 = VDD2)
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Sensitivity 1
R1
16.8
21
25.2
V/(lx · s)
Note 1
Sensitivity 2
R2
—
53
—
V/(lx · s)
Note 2
Sensitivity nonuniformity
PRNU
—
2.0
8.0
%
Note 3
Saturation output voltage
VSAT
1.5
1.8
—
V
—
Dark voltage average
VDRK
—
0.3
2.0
mV
Note 4
Dark signal nonuniformity
DSNU
—
0.5
3.0
mV
Note 4
Image lag
IL
—
0.02
—
%
Note 5
Dynamic range
DR
—
6000
—
—
Note 6
Saturation exposure
SE
—
0.085
—
lx · s
Note 7
9V supply current
IVDD1
—
14.0
20.0
mA
—
5V supply current
IVDD2
—
5.0
10.0
mA
—
Total transfer efficiency
TTE
92.0
97.0
—
%
—
Output impedance
ZO
—
600
—
Ω
—
Offset level
VOS
—
4.5
—
V
Note 8
Notes)
1) For the sensitivity test light is applied with a uniform intensity of illumination.
2) W lamp (2854K)
3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.
PRNU =
(VMAX – VMIN)/2
× 100 [%]
VAVE
The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average
output to VAVE.
4) Integration time is 10ms.
5) VOUT = 500mV
6) DR = VSAT/VDRK
7) SE = VSAT/R1
8) VOS is defined as indicated below.
Signal is observed at PNP-type emitter follower out.
D31
D32
D33
S1
OS
VOS
GND
–5–
VOUT∗
φCLK
0
5
0
–6–
1-line output period (2631 pixels)
Effective picture
elements signal
(2592 pixels)
D31
D32
D33
S1
S2
S3
S4
Optical black
(18 pixels)
D11
D12
D13
D14
D15
Dummy signal (33 pixels)
1
D1
φROG
2
3
4
D2
D3
D4
D5
D6
5
2631
∗ Internal S/H is not in use
Dummy signal
(6 pixels)
S2589
S2590
S2591
S2592
D34
D35
D36
D37
D38
D39
Clock Timing Diagram (For internal RS mode)
ILX505A
2
1
VOUT
φRS
φCLK
φROG
0
5
0
5
0
2
3
4
–7–
1-line output period (2631 pixels)
Effective picture
elements signal
(2592 pixels)
D31
D32
D33
S1
S2
S3
S4
Optical black
(18 pixels)
D11
D12
D13
D14
D15
Dummy signal (33 pixels)
D2
D3
D4
D5
D6
5
2631
Dummy signal
(6 pixels)
S2589
S2590
S2591
S2592
D34
D35
D36
D37
D38
D39
1
Clock Timing Diagram (For external RS mode)
ILX505A
2
1
ILX505A
φCLK, VOUT Timing (For internal RS mode)
t1
t2
φCLK
t3
t4
t10
AAAA
AAAA
AAAA
VOUT
t17
Item
Symbol
AAAAAA
AAAAAA
AAAAAA
Min.
Typ.
Max.
Unit
0
10
—
ns
40
50
60
%
φCLK pulse rise/fall time
φCLK pulse duty∗1
t1, t2
φCLK – VOUT 1
t10
50
80
110
ns
φCLK – VOUT 2
t17
30
75
120
ns
—
∗1 100 × t3/(t3 + t4)
–8–
ILX505A
φCLK, φRS, VOUT Timing (For external RS mode)
t1
t2
φCLK
t3
t4
t5
φRS
t8
t9
t6
t7
t11
t10
AAAA
AAAA
AAAAAA
AAAAAA
VOUT
Item
Symbol
Min.
Typ.
Max.
Unit
φCLK, φRS pulse rise/fall time
φCLK pulse duty∗1
t1, t2, t8, t9
0
10
—
ns
—
40
50
60
%
φCLK – φRS pulse timing
t6
0
100
—
ns
φCLK – φRS pulse timing
t7
50
100
—
ns
φRS pulse period
t5
50
100
—
ns
φCLK – VOUT
t10
50
80
110
ns
φRS – VOUT
t11
30
50
70
ns
∗1 100 × t3/(t3 + t4)
–9–
ILX505A
φROG, φCLK Timing
φROG
t13
t14
t15
φCLK
t12
Item
Symbol
t16
Min.
Typ.
Max.
Unit
φROG, φCLK pulse timing
t12, t16
500
1000
—
ns
φROG pulse rise/fall time
t13, t15
0
10
—
ns
φROG pulse period
t14
500
1000
—
ns
– 10 –
ILX505A
Example of Representative Characteristics
Spectral sensitivity characteristics
(Standard characteristics)
10
Ta = 25°C
9
Relative sensitivity
8
7
6
5
4
3
2
1
0
400
500
600
700
800
Wavelength [nm]
MTF of main scanning direction
(Standard characteristics)
0
1000
MTF of sub scanning direction
(Standard characteristics)
45.5
0
1.0
λ = 560nm
0.8
0.8
0.6
0.6
Y-MTF
X-MTF
1.0
Spatial frequency [cycles/mm]
9.1
18.2
27.3
36.4
900
0.4
0.4
0.2
0.2
0
Spatial frequency [cycles/mm]
9.1
18.2
27.3
36.4
45.5
λ = 560nm
0
0
0.2
0.4
0.6
0.8
Normalized spatial frequency
0
1.0
– 11 –
0.2
0.4
0.6
0.8
Normalized spatial frequency
1.0
ILX505A
Application Circuit
5V
9V
10µ
10µ
1000p
1000p
1000p
22
21
(D)
10µ
10µ
20
19
18
17
16
15
14
13
12
(A)
(A)
(A)
(A)
(A)
(A)
(D)
(D)
(D)
(A)
(D)
(D)
(D)
(D)
6
7
8
9
10
(A)
(D)
(A)
(A)
1
2
3
4
5
11
9V
3k
100
10µ
1000p
VOUT
10µ
1000p
2SA1175
φCLK
5V
φROG
• Internal S/H is in use. Pin 4 must be connected to 5V DC power supply when S/H is not used.
• Internal RS mode is used. For the external RS mode, connect Pin 19 and Pin 4 to 5V DC power supply and
input a proper clock pulse into Pin 10.
• When noise influence into output signal is large, connect pins indicated by (A) to the analog power supply
and pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large
capacitance.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 12 –
ILX505A
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Regulation for raising and lowering the power supply voltage
When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and
then VDD1 (9V).
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, ground the controller. For the control system, use a zero cross type.
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air
is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
– 13 –
5.0 ± 0.5
– 14 –
V
7.6 ± 0.8
H
1
22
Cer-DIP
TIN PLATING
42 ALLOY
3.9g
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
2.54
40.2
11
12
0.51
22pin DIP (400mil)
41.6 ± 0.5
28.512 (11µm X 2592Pixels)
No.1 Pixel
PACKAGE MATERIAL
PACKAGE STRUCTURE
4.0 ± 0.5
Unit: mm
9.0
10.0 ± 0.5
0.3
2.6
3.3 ± 0.5
Package Outline
0.25
0° to 9°
(AT STAND OFF)
10.16
M
2. The thickness of the cover glass is 0.7mm, and the refractive
index is 1.5.
1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm.
ILX505A