TSM7104D 20V Dual P-Channel Enhancement Mode MOSFET Pin assignment: 1. Source 1 2. Gate 1 3. Source 2 4. Gate 2 5, 6. Drain 2 7, 8. Drain 1 VDS = - 20V RDS (on), Vgs @ - 4.5V, Ids @ - 2.3A =130mΩ RDS (on), Vgs @ - 2.5V, Ids @ - 2.0A =190mΩ Features Block Diagram Advanced trench process technology High density cell design for ultra low on-resistance Excellent thermal and electrical capabilities Surface mount Fast switching Ordering Information Part No. TSM7104DCS Packing Tape & Reel Package SOP-8 Absolute Maximum Rating (Ta = 25 oC unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage VDS - 20V V Gate-Source Voltage VGS ±8 V ID - 2.3 A IDM - 10 A PD 2 W 16 mW/ C Continuous Drain Current, VGS @4.5V. Pulsed Drain Current, VGS @4.5V Maximum Power Dissipation o Ta = 25 C o Ta > 25 C Operating Junction Temperature +150 o C TJ, TSTG - 55 to +150 o C Symbol Limit TJ Operating Junction and Storage Temperature Range o Thermal Performance Parameter Junction to Ambient Thermal Resistance (PCB mounted) Note: Surface mounted on FR4 board t<=5sec. TSM7104D 1-3 Rθja 62.5 2003/12 rev. A Unit o C/W Electrical Characteristics o Rate ID = - 2.3A, (Ta = 25 C unless otherwise noted) Parameter Conditions Symbol Min Typ Max Unit V Static Drain-Source Breakdown Voltage VGS = 0V, ID = - 250uA BVDSS - 20 -- -- Drain-Source On-State VGS = - 4.5V, ID = -2.3A RDS(ON) -- 90 130 mΩ Resistance Drain-Source On-State VGS = - 2.5V, ID = -2.0A RDS(ON) -- 120 190 Gate Threshold Voltage VDS = VGS, ID = - 250uA VGS(TH) - 0.45 -- -- Zero Gate Voltage Drain Current VDS = - 16V, VGS = 0V IDSS -- -- - 1.0 uA Gate Body Leakage VGS = ± 8V, VDS = 0V IGSS -- -- ± 100 nA Forward Transconductance VDS = - 5V, ID = - 2.3A gfs -- 6.5 -- S Total Gate Charge VDS = - 6V, ID = - 2.3A, Qg -- 5.4 10 Gate-Source Charge VGS = - 4.5V Qgs -- 0.8 -- Qgd -- 1.1 -- td(on) -- 5 25 tr -- 19 60 -- 95 110 Resistance V Dynamic Gate-Drain Charge nC Turn-On Delay Time VDD = - 6V, RL = 6Ω, Turn-On Rise Time ID = - 1A, VGEN = - 4.5V, Turn-Off Delay Time RG = 6Ω td(off) tf -- 65 80 Input Capacitance VDS = - 6V, VGS = 0V, Ciss -- 447 -- Output Capacitance f = 1.0MHz Coss -- 127 -- Crss -- 80 -- IS -- -- - 1.6 A VSD -- - 0.8 - 1.2 V Turn-Off Fall Time Reverse Transfer Capacitance nS pF Source-Drain Diode Max. Diode Forward Current Diode Forward Voltage IS = - 1.6A, VGS = 0V Note : pulse test: pulse width <=300uS, duty cycle <=2% TSM7104D 2-3 2003/12 rev. A SOP-8 Mechanical Drawing A SOP-8 DIMENSION DIM 9 16 B 1 P 8 G R C D TSM7104D M F K 3-3 MILLIMETERS INCHES A MIN 4.80 MAX 5.00 MIN 0.189 MAX 0.196 B 3.80 4.00 0.150 0.157 C D 1.35 0.35 1.75 0.49 0.054 0.014 0.068 0.019 F 0.40 1.25 0.016 0.049 G K 1.27 (typ) 0.10 0.25 0.05 (typ) 0.004 0.009 M 0o 7o 0o 7o P R 5.80 0.25 6.20 0.50 0.229 0.010 0.244 0.019 2003/12 rev. A