W78C801 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The W78C801 is an 8-bit microcontroller which can accommodate a wide frequency range with low power consumption. The instruction set for the W78C801 is fully compatible with the standard 8051. The W78C801 contains an 4K bytes Mask ROM; a 256 bytes RAM; four 8-bit bi-directional and bitaddressable I/O ports; an additional 6-bit I/O port P4; two 16-bit timer/counters; a hardware watchdog timer. These peripherals are supported by a twelve sources two-level interrupt capability. The W78C801 does not contain serial port. The W78C801 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. FEATURES • Fully static design 8-bit CMOS microcontroller • DC-40 MHz operation • 256 bytes of on-chip scratchpad RAM • 4 KB Mask-ROM • 64 KB program memory address space • 64 KB data memory address space • Four 8-bit bi-directional ports • Two 16-bit timer/counters • Watchdog Timer • Direct LED drive outputs • Twelve sources, two-level interrupt capability • Wake-up via external interrupts at Port 1 • EMI reduction mode • Built-in power management • Code protection mechanism • Packages: − DIP 40: W78C801-24/40 − PLCC 44: W78C801P-24/40 − PQFP 44: W78C801F-24/40 -1- Publication Release Date: February 1999 Revision A3 W78C801 PIN CONFIGURATIONS 40-Pin DIP (W78C801) INT2, P1.0 INT3, P1.1 INT4,P1.2 INT5,P1.3 INT6,P1.4 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST P3.0 P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 1 2 40 39 3 4 38 37 36 5 6 7 8 9 10 11 12 13 WR, P3.6 14 15 16 RD, P3.7 XTAL2 XTAL1 17 18 19 VSS 20 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE,P4.5 PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 44-Pin QFP (W78C801F) 44-Pin PLCC (W78C801P) I N T 6 , P 1 . 4 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST P3.0 P4.3 P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 I N T 5 , P 1 . 3 I N T 4 , P 1 . 2 I N T 3 , P 1 . 1 I N T 2 , P 1 . 0 A D 0 , P P 4 V 0 . D . 2 D 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 6 5 4 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 35 7 12 13 34 14 15 16 17 18 19 20 21 22 23 24 25 26 27 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X V P P P T S 4 2 2 A S . . . L 0 0 1 1 , , A A 8 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 I N T 6 , P 1 . 4 A D 3 , P 0 . 3 33 32 31 30 29 28 P0.4, AD4 INT7,P1.5 INT8,P1.6 P0.5, AD5 P0.6, AD6 P0.7, AD7 INT9,P1.7 RST P3.0 P4.3 EA P4.1 P3.1 ALE,P4.5 INT0, P3.2 PSEN,P4.6 P2.7, A15 P2.6, A14 INT1, P3.3 T0, P3.4 T1, P3.5 P2.5, A13 P 2 . 4 , A 1 2 I N T 4 , P 1 . 2 I N T 3 , P 1 . 1 I N T 2 , P 1 . 0 A D 0 , P P 4 V 0 . D . 2 D 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 1 2 28 27 6 7 8 9 26 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R -2- I N T 5 , P 1 . 3 P 3 . 7 , / R D X T A L 2 X V P P T S 4 2 A S . . L 0 0 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE,P4.5 PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 W78C801 PIN DESCRIPTION SYMBOL DESCRIPTIONS EA EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be presented on the bus if EA pin is high and the program counter is within on-chip ROM area. Otherwise they will be presented on the bus. PSEN PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/ data bus during fetch and MOVC operations. When internal ROM access is performed, no PSEN strobe signal outputs from this pin. This pin also serves the alternative function P4.6. ALE ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. This pin also serves the alternative function P4.5 RST RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. VSS GROUND: Ground potential VDD POWER SUPPLY: Supply voltage for operation. P0.0−P0.7 PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order address/data bus during accesses to external memory. The pins of Port 0 can be individually configured to open-drain or standard port with internal pull-ups. P1.0−P1.7 PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below: INT2−INT9(P1.0−P1.7): External interrupt 2 to 9 P2.0−P2.7 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. P3.0−P3.7 PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7 can be configured with high sink current which can drive LED displays directly. All bits have alternate functions, which are described below: INT0 (P3.2) : External Interrupt 0 INT1 (P3.3) : External Interrupt 1 T0(P3.4) : Timer 0 External Input T1(P3.5) : Timer 1 External Input WR (P3.6) : External Data Memory Write Strobe RD (P3.7) : External Data Memory Read Strobe P4.0−P4.6 PORT 4: A 6-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are available on 44-pin PLCC/QFP package. Pins P4.5 and P4.6 are the alternative function corresponding to ALE and PSEN . -3- Publication Release Date: February 1999 Revision A3 W78C801 BLOCK DIAGRAM P1.0 Port 1 Port 1 Latch P1.7 INT2~9 ACC B P0.0 Port 0 Interrupt T1 Latch T2 Port 0 P0.7 DPTR Timer 0 Stack Pointer PSW ALU Temp Reg. Timer 1 PC Incrementor Addr. Reg. P3.0 Port 3 Port 3 SFR RAM Address Instruction Decoder & Sequencer Latch P3.7 256 bytes RAM & SFR P2.0 Port 2 Latch Bus & Clock Controller P2.7 Port 4 Latch P4.0 Port 2 Watchdog Port 4 Timer Oscillator P4.6 XTAL1 XTAL2 Reset Block ALE PSEN RST Power control VCC Vss FUNCTIONAL DESCRIPTION The W78C801 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, two timer/counters. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. Timers 0, 1 Timers 0, 1 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1. The TCON and TMOD registers provide control functions for timers 0 and 1. The operations of Timer 0 and Timer 1 are the same as in the W78C51. I/O Port Options The Port 0 and Port 3 of W78C801 may be configured with different types by setting the bits of the Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When the PUP bit in the POR register is set, the pins of Port 0 will perform a quasi-bidirectional I/O port with internal pull-up that is structurally the same as Port 2. The high nibble of Port -4- W78C801 3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by setting the HDx bit in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink about 20mA current for driving LED display directly. After reset, the POR register is cleared and the pins of Ports 0 and 3 are the same as those of the standard 80C31. The POR register is shown below. Port Options Register Bit: 7 6 5 4 3 2 1 0 EP6 EP5 - HD7 HD6 HD5 HD4 PUP Mnemonic: POR Address: 86H PUP : Enable Port 0 weak pull-up. HD4-7: Enable pins P3.4 to P3.7 individually with High Drive outputs. EP5 : Enable P4.5. To set this bit shifts ALE pin to the alternate function P4.5. EP6 : Enable P4.6. To set this bit shifts PSEN pin to the alternate function P4.6 Port 4 The W78C801 has one additional bit-addressable I/O port P4 in which the port address is D8H. The Port 4 contains seven bits; P4.0 to P4.3 are only available on 44-pin PLCC/QFP package; P4.5 and P4.6 are the alternate function corresponding to pins ALE, PSEN . When program is running in the internal memory without any access to external memory, ALE and PSEN may be individually configured to the alternate functions P4.5 and P4.6 that serve as general purpose I/O pins. To enable I/O port P4.5 and P4.6, the bits EP5 and EP6 in the POR register must be set. During reset, the ALE and PSEN perform as in the standard 80C32. The alternate functions P4.5 and P4.6 must be enabled by software. Care must be taken with the ALE pins when configured as the alternate functions. The ALE will emit pulses until either the EP5 bit in POR register or AO bit in AUXR register is set to 1. i.e. User's applications should elude the ALE pulses before software configure it with I/O port P4.5. Port 4 Bit: 7 6 5 4 3 2 1 0 - P4.6 P4.5 - P4.3 P4.2 P4.1 P4.0 Mnemonic: P4 Address: D8H Interrupt System The W78C801 has twelve interrupt sources: INT0 and INT1 ; Timer 0,1; INT2 to INT9. Each interrupt vectors to a specific location in program memory for its interrupt service routine. Each of these sources can be individually enabled or disabled by setting or clearing the corresponding bit in Special Function Register IE0 and IE1. The individual interrupt priority level depends on the Interrupt Priority Register IP0 and IP1. Additional external interrupts INT2 to INT9 are level sensitive and may be used to awake the device from power down mode. The Port 1 interrupts can be initialized to either active HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ register contains the flags of Port 1 interrupts. Each flag in IRQ register will be set when an interrupt request is recognized but must be cleared by software. Note that the interrupt flags have to be cleared before the interrupt service routine is completed, or else another interrupt will be generated. -5- Publication Release Date: February 1999 Revision A3 W78C801 Interrupt Enable Register 0 Bit: 7 6 5 4 3 2 1 0 EA - - - ET1 EX1 ET0 EX0 Mnemonic: IE EA : ET1: EX1: ET0: EX0: Address: A8H Global enable. Enable/disable all interrupts. Enable Timer 1 interrupt Enable external interrupt 1 Enable Timer 0 interrupt Enable external interrupt 0 Interrupt Enable Register 1 Bit: 7 6 5 4 3 2 1 0 EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2 Mnemonic: IE1 EX9: EX8: EX7: EX6: EX5: EX4: EX3: EX2: Address: E8H Enable external interrupt 9 Enable external interrupt 8 Enable external interrupt 7 Enable external interrupt 6 Enable external interrupt 5 Enable external interrupt 4 Enable external interrupt 3 Enable external interrupt 2 Note: 0 = interrupt disabled, 1 = interrupt enabled. Interrupt Priority Register 0 Bit: 7 6 5 4 3 2 1 0 - PS1 PT2 PS PT1 PX1 PT0 PX0 Mnemonic: IP0 IP.7: PS1: PT2: PS : PT1: PX1: PT0: PX0: Address: B8h Unused. This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level. This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level. This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level. This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level. -6- W78C801 Interrupt Priority Register 1 Bit: 7 6 5 4 3 2 1 0 PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 Mnemonic: IP1 PX9: PX8: PX7: PX6: PX5: PX4: PX3: PX2: Address: F8h This bit defines the External interrupt 9 priority. PX9 = 1 sets it to higher priority level. This bit defines the External interrupt 8 priority. PX8 = 1 sets it to higher priority level. This bit defines the External interrupt 7 priority. PX7 = 1 sets it to higher priority level. This bit defines the External interrupt 6 priority. PX6 = 1 sets it to higher priority level. This bit defines the External interrupt 5 priority. PX5 = 1 sets it to higher priority level. This bit defines the External interrupt 4 priority. PX4 = 1 sets it to higher priority level. This bit defines the External interrupt 3 priority. PX3 = 1 sets it to higher priority level. This bit defines the External interrupt 2 priority. PX2 = 1 sets it to higher priority level. Interrupt Polarity Register Bit: 7 6 5 4 3 2 1 0 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 Mnemonic: IX IL9: IL8: IL7: IL6: IL5: IL4: IL3: IL2: Address: E9H External interrupt 9 polarity level. External interrupt 8 polarity level. External interrupt 7 polarity level. External interrupt 6 polarity level. External interrupt 5 polarity level. External interrupt 4 polarity level. External interrupt 3 polarity level. External interrupt 2 polarity level. Note: 0 = active LOW, 1 = active HIGH. Interrupt Request Flag Register Bit: IQ9: IQ8: IQ7: IQ6: IQ5: IQ4: IQ3: IQ2: 7 6 5 4 3 2 1 0 IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 Mnemonic: IRQ External interrupt 9 request flag. External interrupt 8 request flag. External interrupt 7 request flag. External interrupt 6 request flag. External interrupt 5 request flag. External interrupt 4 request flag. External interrupt 3 request flag. External interrupt 2 request flag. Address: C0H -7- Publication Release Date: February 1999 Revision A3 W78C801 Table.1 Priority level for simultaneous requests of the same priority interrupt sources Source Flag Priority level Vector Address External Interrupt 0 IE0 (highest) 0003H External Interrupt 5 IQ5 0053H Timer 0 Overflow TF0 000BH External Interrupt 6 IQ6 005BH External Interrupt 1 IE1 0013H External Interrupt 2 IQ2 003BH External Interrupt 7 IQ7 0063H Timer 1 Overflow TF1 001BH External Interrupt 3 IQ3 0043H External Interrupt 8 IQ8 006BH External Interrupt 4 IQ4 004BH External Interrupt 9 IQ9 (lowest) 0073H Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 6 5 4 3 2 1 0 ENW CLRW WIDL - - PS2 PS1 PS0 Mnemonic: WDTC Address: 8FH ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared. PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2−0 as follows: -8- W78C801 PS2 PS1 PS0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 PRESCALER SELECT 2 4 8 16 32 64 128 256 The time-out period is obtained using the following formula: 1 × 214 × PRESCALER × 1000 × 12 mS OSC Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset. ENW WIDL IDLE EXTERNAL RESET OSC PRESCALER 1/12 Watchdog Timer Block Diagram 14-BIT TIMER INTERNAL RESET CLEAR CLRW Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 WATCHDOG TIME-OUT PERIOD 19.66 mS 39.32 mS 78.64 mS 157.28 mS 314.57 mS 629.14 mS 1.25 S 2.50 S -9- Publication Release Date: February 1999 Revision A3 W78C801 Clock The W78C801 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78C801 relatively insensitive to duty cycle variations in the clock. The W78C801 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT2 to INT9 when enabled. AUXR - Auxiliary Register Bit: 7 6 5 4 3 2 1 0 - - - - - - - AO Mnemonic: AUXR AO: Address: 8Eh Turn off ALE signal. Reduce EMI Emission Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space. Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C801 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. - 10 - W78C801 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN. MAX. UNIT VDD−VSS -0.3 +6.0 V Input Voltage VIN VSS -0.3 VDD +0.3 V Operating Temperature TA 0 70 °C Storage Temperature TST -55 +150 °C DC Power Supply Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS Vss = 0V ; TA = 25° C; unless otherwise specified. PARAMETER SYM. SPECIFICATION MIN. MAX. UNIT TEST CONDITIONS Operating Voltage VDD 4.5 5.5 V Operating Current IDD - 20 mA VDD = 5.5V, 16 MHz, no load IIDLE - 6 mA VDD = 5.5V, 16 MHz, no load IPWDN - 50 µA VDD = 5.5V, no load -50 +10 µA VDD = 5.5V Idle Current Power Down Current Input Input Current IIN P1, P2, P3, P4 Input Leakage Current VIN = 0V or VDD ILK -10 +10 µA Vss < VIN < VDD P0, EA Input Current IIN2 -60 +300 µA RST Logic 1-to-0 Transition Current VDD = 5.5V 0 < VIN < VDD ITL -500 -200 µA P1, P2, P3, P4 Input Low Voltage VDD = 5.5V VDD = 5.5V VIN = 2V VIL1 0 0.8 V VDD = 5.5V VIL2 0 0.8 V VDD = 5.5V VIL3 0 0.8 P1, P2, P3, P4 Input Low Voltage RST Input Low Voltage VDD = 5.5V XTAL1 - 11 - Publication Release Date: February 1999 Revision A3 W78C801 DC Characteristics, continued PARAMETER Input High Voltage SYM. SPECIFICATION TEST CONDITIONS MIN. MAX. UNIT VIH1 2.4 VDD +0.2 V VDD = 5.5V VIH2 3.5 VDD +0.2 V VDD = 5.5V VIH3 3.5 VDD +0.2 V VDD = 5.5V - 0.45 V VDD = 4.5V P1, P2, P3, P4 Input High Voltage RST Input High Voltage [*4] XTAL1 Output Output Low Voltage VOL1 P1, P2, P3, P4 IOL = +2 mA Output Low Voltage P0, ALE, PSEN [*4] VOL2 Sink Current Isk1 [5] P1, P2, P3 - 0.45 V IOL = +4 mA 4 12 mA , P4<0:4> Isk2 Sink Current Isk3 10 20 mA 15 24 mA VOH1 2.4 - V VDD = 4.5V IOH = -100 µA VOH2 2.4 - V VDD = 4.5V IOH = -400 µA Isr1 -120 -250 µA P1, P2, P3, P4<0:4> Source Current P0, ALE, PSEN , P4<5:6> VDD = 4.5V VIN = 0.45V P1, P2, P3, P4 Source Current VDD = 4.5V VIN = 0.45V P3.4 to P3.7 in High-drive Mode Output High Voltage P0, ALE, PSEN [*4] VDD = 4.5V VIN = 0.45V Sink Current P0, ALE, PSEN , P4<5:6> Output High Voltage VDD = 4.5V VDD = 4.5V VIN = 2.4V Isr2 -10 -14 mA VDD = 4.5V VIN = 2.4V Notes: *1. RST pin has an internal pull-down. *2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0. *3. RST is a Schmitt trigger input and XTAL1 is a CMOS input. *4. P0, P2, ALE and PSEN are tested in the external access mode. *5. P3.4 to P3.7 are in normal mode. - 12 - W78C801 AC CHARACTERISTICS Clock Input Waveform XTAL1 T CH TCL F OP, PARAMETER TCP SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed FOP 0 - 16 MHz 1 Clock Period TCP 25 - - nS 2 Clock High TCH 10 - - nS 3 Clock Low TCL 10 - - nS 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low TAAS 1 TCP -∆ - - nS 4 Address Hold from ALE Low TAAH 1 TCP -∆ - - nS 1, 4 ALE Low to PSEN Low TAPL 1 TCP -∆ - - nS 4 PSEN Low to Data Valid TPDA - - 2 TCP nS 2 Data Hold after PSEN High TPDH 0 - 1 TCP nS 3 Data Float after PSEN High TPDZ 0 - 1 TCP nS ALE Pulse Width TALW 2 TCP -∆ 2 TCP - nS 4 PSEN Pulse Width TPSW 3 TCP -∆ 3 TCP - nS 4 Notes: 1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "∆" (due to buffer driving delay and wire loading) is 20 nS. - 13 - Publication Release Date: February 1999 Revision A3 W78C801 Data Read Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES ALE Low to RD Low TDAR 3 TCP -∆ - 3 TCP +∆ nS 1, 2 RD Low to Data Valid TDDA - - 4 TCP nS 1 Data Hold from RD High TDDH 0 - 2 TCP nS Data Float from RD High TDDZ 0 - 2 TCP nS RD Pulse Width TDRD 6 TCP -∆ 6 TCP - nS Notes: 1. Data memory access time is 8 TCP. 2. "∆" (due to buffer driving delay and wire loading) is 20 nS. Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP -∆ - 3 TCP +∆ nS Data Valid to WR Low TDAD 1 TCP -∆ - - nS Data Hold from WR High TDWD 1 TCP -∆ - - nS WR Pulse Width TDWR 6 TCP -∆ 6 TCP - nS Note: "∆" (due to buffer driving delay and wire loading) is 20 nS. Port Access Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. - 14 - 2 W78C801 TIMING WAVEFORMS Program Fetch Cycle S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 XTAL1 TALW ALE TAPL PSEN TPSW TAAS PORT 2 TPDA TAAH TPDH, TPDZ PORT 0 A0-A7 Code Data A0-A7 A0-A7 Code Data A0-A7 Data Read Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 A8-A15 DATA A0-A7 PORT 0 T DAR T DDA T DDH, T DDZ RD T DRD - 15 - Publication Release Date: February 1999 Revision A3 W78C801 Timing Waveforms, continued Data Write Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 XTAL1 ALE PSEN A8-A15 PORT 2 PORT 0 A0-A7 DATA OUT T DWD TDAD WR T DWR T DAW Port Access Cycle S5 S6 S1 XTAL1 ALE TPDS T PDA T PDH DATA OUT PORT INPUT SAMPLE - 16 - S3 W78C801 PACKAGE DIMENSIONS 40-pin DIP Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. Symbol D 40 21 E1 0.010 0.150 0.155 0.160 3.81 3.937 4.064 0.016 0.018 0.022 0.406 0.457 0.559 0.048 0.050 0.054 1.219 1.27 1.372 0.008 0.010 0.014 0.203 0.254 0.356 2.055 2.070 52.20 52.58 0.600 0.610 14.986 15.24 15.494 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.286 2.54 2.794 0.120 0.130 0.140 3.048 3.302 3.556 15 0 0.670 16.00 16.51 17.01 0 eA S 20 0.254 0.590 a 1 5.334 0.210 A A1 A2 B B1 c D E E1 e1 L 0.630 0.650 15 0.090 2.286 Notes: E S 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . parting line. are determined at the mold 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. c A A2 A1 Base Plane Seating Plane L B e1 eA a B1 44-pin PLCC HD D 6 1 44 40 Symbol 7 39 E 17 HE GE 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.185 0.020 4.699 0.508 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 3.81 3.937 0.66 0.711 0.813 0.406 0.457 0.559 3.683 1.27 BSC 0.590 0.610 0.630 14.99 15.49 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.296 2.54 2.794 0.004 0.10 L Notes: A2 A 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. θ e b b1 Seating Plane A1 y GD - 17 - Publication Release Date: February 1999 Revision A3 W78C801 Package Dimensions, continued 44-pin PQFP HD Symbol 34 A A1 A2 b c D E e HD HE L L1 y θ 33 1 E HE 11 12 e Dimension in mm Dimension in inch D 44 b 22 Min. Nom. Max. Min. Nom. Max. --- --- --- --- 0.002 0.01 0.02 0.05 0.25 0.5 0.075 0.081 0.087 1.90 2.05 2.20 0.01 0.014 0.018 0.25 0.35 0.45 0.004 0.006 0.010 0.101 0.152 0.254 0.390 0.394 0.398 9.9 10.00 10.1 0.390 0.394 0.398 9.9 10.00 10.1 0.025 0.031 0.036 0.635 0.80 0.952 0.510 0.520 0.530 12.95 13.2 13.45 13.45 --- --- 0.510 0.520 0.530 12.95 13.2 0.025 0.031 0.037 0.65 0.8 0.95 0.051 0.063 0.075 1.295 1.6 1.905 0.08 0.003 0 7 0 7 Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. c A2 A θ A1 Seating Plane See Detail F L y L1 Detail F Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 18 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798