AKM AK7782VQ

[AK7782]
AK7782
Dual Audio DSP with 24bit 5ch ADC & SRC
GENERAL DESCRIPTION
The AK7782 is an audio digital signal processor with integrated 24bit 5ch ADCs, an 8:2 stereo input
selector and sample rate converters that support 2ch inputs and the frequency up to 96kHz. The ADC
supports wide range of sampling frequency from 7.35kHz to 96kHz. Two integrated audio DSPs have
high performance processing speed of 2560step/fs (at 48kHz sampling), and two 6k-word delay RAMs
allow surround processing, time alignment adjusting and FIR filtering. As the AK7782 is a RAM based
DSP, it is programmable for various user requirements. It is housed in a 100pin LQFP package.
FEATURES
[DSP1/DSP2]
□ Word Length: 28-bits
□ Instruction Cycle Time: 8.1ns (2560fs, fs=48kHz)
□ Processing Step: 2560 steps (max) /fs= 48kHz, 44.1kHz (Normal Speed)
15360 steps (max) /fs= 8kHz, 7.35kHz
1280 steps (max) fs= 96kHz, 88.2kHz (Double Speed)
□ Multiplier: 24 x 16 → 40-bits (double precision available)
□ Divider: 24 ÷ 24 → 24-bits (floating point normalization function)
□ ALU: 44-bit arithmetic operation (with 4-bit overflow margin)
□
24-bit arithmetic and logic operation
Data Shift: Right shift after multiplication 1, 2, 4, 5, 8, 14, 15-bits
Right shift BUS 1, 2, 3, 4, 8, 14, 15-bits
Left shift after multiplication 1, 2, 3, 4, 8, 15-bits
Left shift BUS 1, 2, 3, 4, 6, 8, 15-bits
Indirect shifting function
Program RAM (PRAM): 2048word x 36-bits
□
□ Coefficient RAM (CRAM): 2048word x 16-bits
□ Data RAM (DRAM): 2048word x 28-bits
□ Offset Register (OFREG): 64word x 13-bits
□ Delay RAM (DLRAM): 168kbit (four types)
● 6kword 28-bits
● 4kword 28-bits + 4kword 14-bits
● 3kword 28-bits + 6kword 14-bits
● 3kword 28-bits + 3kword 28-bits (Linear)
□ Register: 44-bits x 4 (ACC) [for ALU]
28-bits x 12 (TMP) [DBUS connection]
28-bits x 6 steps stack (PTMP) [DBUS connection]
MS1337-E-00-PB
2011/11
- 1-
[AK7782]
[Stereo ADC, Common for ADC1 and ADC2]
□ 24-bit 2ch x 2
□ S/(N+D): 90dB (fs=48kHz)
□ D-range: 96dBA (fs=48kHz)
□ S/N: 96dBA (fs=48kHz)
□ 8ch bidirectional analog input selector
□ High-pass filter (HPF) for DC offset cancellation
□ fs=7.35kHz ~ 96kHz
[Mono ADC]
□ 24bit 1ch
□ S/(N+D) 88dB (fs=48kHz)
□ D-range 95dBA (fs=48kHz)
□ S/N 95dBA (fs=48kHz)
□ High-pass filter (HPF) for DC offset cancellation
□ fs=7.35kHz ~ 96kHz
□ Digital volume control
[DSP1/DSP2 In/Output Digital Interface]
□ Serial Data Input: 14ch (including ADC block)
□ Serial Data Output: 16ch (each DSP outputs are 14ch)
□ Microcomputer Interface: 1ch In/Out or I2C-bus
[SRC, Common for SRC1 and SRC2]
□ 2ch x 2
□ fs=7.35kHz ~ 96kHz
[General]
□ PLL
□ 3.3V±0.3V, 1.8V ±0.1V
□ Operational Temperature: -40°C ~ 85°C
□ 100pin LQFP
MS1337-E-00-PB
2011/11
- 2-
[AK7782]
AINL8, AINR8
2
2
2
2
AINM
AINL5, AINR5
2
AINL6 AINR6
2
AINL7, AINR7
2
AINL3, AINR3
4
AINL4, AINR4
AINL+,AINR+
AINL+,AINR+
AINL2, AINR2
■ Block Diagram
pull down
Hi-z
2 VSS2
7 DVDD18
I/O
3 VSS3
8
3
6 DVDD
3 AVDD
ASEL2[2:0]
ADC1
ASEL1[2:0]
ctrl reg sw
ADC2
ADCM
VOL
3 VREFH
VREF
MUX
VCOM
VREFL
3 VSS1
OUTASEL1
0
OUTASEL2
1
2
0
1
3
0
1
2
3
SDIN7/JX2
JX2
SDIN6 / JX1
P1IN6SEL
JX1
SDIN5
P1IN5SEL
P1IN7SEL
P1SDIN7
P1SDOUT7
2 3
MSEL
3
0
1
2
3
0
1
2
3
P1SDIN6
P2SDIN7
0
1
2
3
P2SDOUT7
0
1
2
3
P1SDOUT6
P2IN6SEL
0
1
2
3
0
1
2
3
P1SDIN5
P1SDOUT5
IRPT1
P1SDIN4
P1SDOUT4
GPO11
SDIN3(32bit)
P1SDIN3
P1SDOUT3
GPO10
SDIN2(32bit)
P1SDIN2
P1SDOUT2
P2SDIN6
P2IN5SEL
0
1
2
3
P2SDIN4
0
P2SDIN3
1
P2IN3SEL
RSRC1SMUTE
PSRCSMUTE
P1SDIN1
OUT4SEL
P2SDOUT4
GPO21
JX12E
JX11E
OUT4EN
P2SDOUT3
GPO20
OUT3EN
OUT2EN
RSRC1RSTN
OUT1EN
SDOUT1
P2SDOUT1
JX22E
JX22
P2IN1SEL
JX21E
JX11
JX21
JX20E
JX10
SRC1
SDOUT2(32bit)
OUT1SEL1
JX10E
PSRCRSTN
SDOUT3(32bit)
OUT2SEL
0
1
2
3
0
1
2
3
P2SDIN1
SDOUT4(32bit)
OUT3SEL
0
1
2
3
P1SDOUT1
JX12
SRC1I SRC1O
SRC1LRCKO
SRC1BICKO
SDOUT5
OUT5EN
0
1
2
3
P2SDIN2
0
1
2
3
SDOUT6
OUT5SEL1
P2SDOUT5
IRPT2
P2SDOUT2
0
1
P2IN2SEL
0
1
2
3
OUT6SEL
OUT6EN
0
1
2
3
P2SDIN5
SDOUT7
OUT7EN
P2SDOUT6
0
1
P2IN4SEL
P1IN1SEL
OUTAEN
OUT7SEL
SDIN4(32bit)
SDIN1
SDOUTA
2
0 1
P2IN7SEL
JX20
JX2
JX1
JX0
WDT1EN
SRCLRCK
SRCBICK
DSP1
SRC1LRCKI
SRC1BICKI
WDT1
CRCE
SRC1UNLOCK
DSP2
SRC2LRCK
SRC2BICK
NC
STO
WDT2EN
WDT2
LOCK1E
LOCK2E
0
TESTO
SRC2ISEL
1
2
3
RSRC2SMUTE
SRC2I SRC2O
SRC2LRCKO
SRC2BICKO
CRC
RSRCRST2N
0
1
SRC2
RQN/CAD1
2
0
1
MICIF
SRC2CKO
SRC2LRCKI
0
2
I2CSEL
SO
SDA
2
0
2
SCLK/SCL
1
SRC2CKI
1
SI/CAD0
RDY
SRC2BICKI
SRC2UNLOCK
LRCLKO
BITCLKO
TESTI2
TESTI1
CKM[2:0] 3
XTI
XTO
CONTROLLER
CKRSTN
PCKRSTN
RCKRSTN
(Master="H",Slave="L")
SMODE
DSPRSTN
PDSPRSTN
RDSPRSTN
SRESETN
PADRSTN
RADRSTN
ADRSTN
LFLT
CLKO1
LRCLKI
BITCLKI
INITRSTN
Figure 1. Block Diagram
MS1337-E-00-PB
2011/11
- 3-
[AK7782]
■ DSP Block Diagram (Common for DSP1 and DSP2)
DLP0, DLP1
DP0, DP1
CP0, CP1
DLRAM
6kw x 28bit
DRAM
2048w x 28bit
CRAM
2048w x 16bit
etc
OFREG
64w x 13bit
CBUS(16bit)
DBUS(28bit)
MPX16
Micon I/F
MPX24
X
Control
DEC
Y
Serial I/F
PRAM
2048w x 36bit
Multiply
16bit x 24bit → 40bit
PC
Stack: 5level(max)
28bit
TMP
40bit
PTMP(LIFO) 6 x 28bit
MUL
44bit
A
DBUS
2 x 24/24.4bit
SDIN7
SHIFT
2 x 24/24.4bit
SDIN6
44bit
2 x 24/24.4bit
SDIN5
2 x 24/20/16/32/24.4bit
SDIN4
2 x 24/20/16/32/24.4bit
SDIN3
2 x 24/20/16/32/24.4bit
SDIN2
2 x 24/24.4bit
SDIN1
B
ALU
44bit
Overflow Margin: 4bit
44bit
DR0-3
44bit
Over Flow Data
Generator
Division 24÷24→24
12 x 28bit
2 x 24/24.4bit
SDOUT7
2 x 24/24.4bit
SDOUT6
2 x 24/24.4bit
SDOUT5
2 x 24/16/32/24.4bit
SDOUT4
2 x 24/16/32/24.4bit
SDOUT3
2 x 24/16/32/24.4bit
SDOUT2
2 x 24/24.4bit
SDOUT1
Peak Detector
MS1337-E-00-PB
2011/11
- 4-
[AK7782]
■ Ordering Guide
-40 ∼ +85°C
100pin LQFP (0.5mm pitch)
Evaluation Board for AK7782
AK7782VQ
AKD7782
RDY
STO
SDOUTA1
SDOUT6
SDOUT7
DVDD
DVDD18
VSS3
SDIN6/JX1
SDIN7/JX2
JX0
SDIN1
SRCBICK
SRCLRCK
PSRCRSTN
SDA
DVDD18
VSS3
DVDD
PSRCSMUTE
VSS2
VSS1
AVDD
TESTI2
NC
■ Pin Layout
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC
AINM
76
77
50
49
AINR4
78
48
VSS3
AINL4
79
47
DVDD18
AINR3
80
81
46
45
SCLK/SCL
AINL3
AINR2
82
44
RQN/CAD1
AINL2
43
42
PDSPRSTN
AVDD
83
84
VREFH
85
41
PCKRSTN
VCOM
86
40
INITRSTN
VREFL
39
38
VSS3
VSS1
87
88
AINR-
89
37
LRCLKI
AINR+
36
35
BITCLKI
AINL-
90
91
AINR+
92
34
SDIN4
AINR5
93
94
33
32
SDIN3
AINL5
AINR6
95
31
DVDD18
AINL6
96
30
VSS3
AINR7
97
98
29
28
DVDD
AINL7
AINR8
99
27
SDOUT5
AINL8
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SDOUT4
100 pin LQFP
DVDD
SI/CAD0
PADRSTN
DVDD18
SDIN5
SDIN2
CLKO1
pin
SDOUT3
SDOUT2
SDOUT1
BITCLKO
LRCLKO
VSS3
DVDD
DVDD18
CKM[2]
CKM[0]
DVDD18
CKM[1]
XTO
VSS3
XTI
DVDD
VSS3
VSS2
SRC2BICK
SRC2LRCK
TESTI1
I2CSEL
AVDD
LFLT
VSS1
(TOP VIEW)
SO
Input
Output
I/O
Power
Figure 2. Pin Layout
MS1337-E-00-PB
2011/11
- 5-
[AK7782]
PIN/FUNCTION
No. Pin Name
I/O
Function
Filter Connection Pin for AK7782 Core PLL
When using the PLL function, connect with R (1.5kΩ) and C (47nF) in
series and connected to analog ground (VSS1)
Ground Pin 0V (silicon board potential)
Power Supply Pin for Analog Block 3.3V (typ)
Test Pin (Internal pull-down)
Connect to VSS3
I2C-bus Select Pin
“L”: Normal Microcomputer Interface
“H”: I2C-bus selected mode. SCL and SDA are active.
I2CSEL must be fixed to “L” (VSS3) or “H” (DVDD).
LR Clock Input Pin for SRC2
BIT Clock Input Pin for SRC2
Ground Pin (silicon board potential)
Connect to VSS1
Classification
Analog Output
1
LFLT
O
2
3
VSS1
AVDD
-
4
TESTI1
I
5
I2CSEL
I
6
7
SRC2LRCK
SRC2BICK
I
I
8
VSS2
-
9
DVDD
-
Power Supply Pin for Digital Block 3.3V (typ)
Digital Power
Supply
10
VSS3
-
Ground Pin 0V
Power Supply
11
XTI
I
12
XTO
O
13
14
15
16
17
VSS3
DVDD18
CKM [1]
CKM [0]
CKM [2]
I
I
I
18
DVDD18
-
19
20
VSS3
DVDD
-
Power Supply
Test
I2C Select
SRC2
Power Supply
Crystal Oscillator Input Pin
Connect a crystal oscillator between the XTI pin and XTO pin or input
an external clock into the XTI pin when not using a crystal oscillator.
System Clock
Crystal Oscillator Output Pin
Connect a crystal oscillator between the XTI pin and XTO pin or leave
open when using an external clock source.
Ground Pin 0V
Power Supply
Power Supply Pin for Digital Block 1.8V (typ)
Clock Mode Select Pin
Mode Select
Clock Mode Select Pin
Clock Mode Select Pin
Digital Power
Power Supply Pin for Digital Block 1.8V (typ)
Supply
Ground Pin 0V
Power Supply
Power Supply Pin for Digital Block 3.3V (typ)
MS1337-E-00-PB
2011/11
- 6-
[AK7782]
No. Pin Name
21
LRCLKO
I/O
O
Function
LR Channel Select Pin
Master mode: Outputs 1fs clock.
Slave mode: Outputs LRCLKI clock.
Serial bit Clock Output Pin
Master mode: Outputs 64fs clock.
Slave mode: Outputs BITCLKI clock
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT7 D3, D2.
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT7 D5, D4.
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT7 D7, D6.
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT6 D1, D0.
DSP Serial Data Output Pin
Outputs “L” during initial reset.
The output data is selected by CONT6 D3, D2.
Clock Output Pin 1
Output frequency can be set by control registers.
Outputs “L” during initial reset.
22
BITCLKO
O
23
SDOUT1
O
24
SDOUT2
O
25
SDOUT3
O
26
SDOUT4
O
27
SDOUT5
O
28
CLKO1
O
29
DVDD
-
Power Supply Pin for Digital Block 3.3V (typ)
30
31
VSS3
DVDD18
-
32
SDIN2
I
33
SDIN3
I
34
SDIN4
I
35
SDIN5
I
Ground Pin 0V
Power Supply Pin for Digital Block 1.8V (typ)
DSP Serial Data Input Pin
Supports floating point input F24.4:
MSB 32-bit and 24-bit / LSB 24-bit, 20-bit and 16-bit.
Connect to VSS3 when this pin is not used.
DSP Serial Data Input Pin
Supports floating point input F24.4:
MSB 32-bit and 24-bit / LSB 24-bit, 20-bit and 16-bit.
Connect to VSS3 when this pin is not used.
DSP Serial Data Input Pin
Supports floating point input F24.4:
MSB 32-bit and 24-bit / LSB 24-bit, 20-bit and 16-bit.
Connect to VSS3 when this pin is not used.
DSP Serial Data Input Pin
Supports floating point input F24.4:
MSB 24-bit / LSB 24-bit, 20-bit and 16-bit.
Connect to VSS3 when this pin is not used.
MS1337-E-00-PB
Classification
System Clock
Digital Block
Serial Data Output
Clock Output
Digital Power
Supply
Power Supply
Digital Block
Serial Data Input
Digital Block
Serial Data Input
2011/11
- 7-
[AK7782]
No.
36
37
Pin Name
BITCLKI
LRCLKI
I/O
I
Serial bit Clock input Pin
I
LR channel select Input Pin
Function
38
DVDD18
-
Power Supply Pin for Digital Block 1.8V (typ)
39
VSS3
-
40
INITRSTN
I
41
PCKRSTN
I
System Clock
42
PADRSTN
I
43
PDSPRSTN
I
RQN
I
CAD1
I
SI
I
CAD0
I
SCLK
I
SCL
I
Ground Pin 0V
Initial Reset N Pin (for device initialization)
The AK7782 is initialized by the INITRSTN pin = “L”.
This pin must be “L” upon power-up the AK7782.
CKM[2:0] Pin settings can be change when the INITRSTN pin = “L”.
Clock Reset N Pin
The internal clock is reset by the PCKRSTN pin = “L”.
Setting of CKM[2:0] can be changed by the PCKRSTN pin = “L”,
even if the INITRSTN pin is “H”.
ADC Reset N Pin
ADC1, ADC2 and ADCM are reset by the PADRSTN pin = “L”.
Control register RADRSTN bit= “0” can also reset these blocks.
The AK7782 is in system reset state when PADRSTN and PDSPRSTN
pins = “L”.
DSP Reset N Pin
DSP1 and DSP2 are reset by the PDSPRSTN= “L”. Control Register
RDSRE bit = “0” can also reset these blocks .
The AK7782 is in system reset state when PADRSTN and PDSPRSTN
pins = “L”.
Microcomputer Interface Request N Pin (I2CSEL= “L”)
Set this pin to “H” during initial reset or when not interfacing to a
microcomputer.
I2C-bus Address Pin 1 (I2CSEL= “H”)
Serial Data Input Pin for Microcomputer Interface (I2CSEL= “L”)
Set this pin to “L” when not used.
I2C-bus address Pin 0 (I2CSEL= “H”)
Serial Data Clock Pin for Microcomputer Interface (I2CSEL= “L”)
Set this pin to “H” when there is no clock input.
SCL I2C-bus Interface Pin (I2CSEL= “H”)
47
DVDD18
-
Power Supply Pin for Digital Block 1.8V (typ)
48
VSS3
-
Ground Pin 0V
49
DVDD
-
Power Supply Pin for Digital Block 3.3V (typ)
50
SO
O
Serial Data Output Pin for Microcomputer Interface
Outputs “Hi-z” when the RQN pin = “H”.
Outputs “Hi-z” during initial reset.
44
45
46
Classification
MS1337-E-00-PB
Digital Power
Supply
Power Supply
Reset
Microcomputer
I/F
I2C
Microcomputer
I/F
I2C
Microcomputer
I/F
I2C
Digital Power
Supply
Power Supply
Digital Power
Supply
Microcomputer
I/F
2011/11
- 8-
[AK7782]
No. Pin Name
I/O
51
O
RDY
Function
Data write ready Pin for Microcomputer Interface
Status Output Pin
“H”: Normal operation
“L”: WDT, CRC error or SRCUNLOCK status (Figure 1)
Outputs “H” during initial reset.
Serial Data Output Pin
Supports MSB 24-bit.
Outputs “L” during initial reset.
Serial Data Output Pin
Supports MSB 24-bit.
Outputs “L” during initial reset.
Serial Data Output Pin
Supports MSB 24-bit.
Outputs “L” during initial reset.
52
STO
O
53
SDOUTA1
O
54
SDOUT6
O
55
SDOUT7
O
56
DVDD
-
Power Supply Pin for Digital Block 3.3V (typ)
57
VSS3
-
Ground Pin 0V
58
DVDD18
-
Power Supply Pin for Digital Block 1.8V (typ)
SDIN7
I
JX2
I
SDIN6
I
JX1
I
61
JX0
I
62
SDIN1
I
63
SRCBICK
I
SRCLRCK
I
59
60
64
65
66
67
68
69
70
71
Classification
Microcomputer
I/F
Status
Digital Block
Serial Data Output
Digital Power
Supply
Power Supply
Digital Power
Supply
DSP Serial Data Input Pin
Digital Block
Connect to VSS3 when this pin is not used. This pin supports 24-bit
Serial Data Input
MSB justified, floating point F24.4.
Conditional Jump Pin
Condition
Connect to VSS3 when this pin is not used.
DSP Serial Data Input Pin
Digital Block
Connect to VSS3 when this pin is not used. This pin supports 24-bit
Serial Data Input
MSB justified, floating point F24.4.
Conditional Jump Pin
Connect to VSS3 when this pin is not used.
Condition
Conditional Jump Pin
Connect to VSS3 when this pin is not used.
DSP/SRC Serial Data Input Pin
Digital Block
Connect to VSS3 when this pin is not used. This pin supports 24-bit
Serial Data Input
MSB justified, floating point F24.4.
SRC Serial bit Clock Input Pin
SRC1
SRC LR channel Select Input Pin
I2CSEL Pin = “L”
O
Outputs “L”.
SDA
I2C
I2CSEL Pin= “H”
I/O
SDA I2C-bus Interface
SRC Reset N Pin
SRC1 and SRC2 blocks are reset by the PSRCRSTN pin = “L”. Reset
PSRCRSTN I
Control register RSRCRSTN bit = “0” can also reset these blocks.
Digital Power
DVDD18
- Power Supply Pin for Digital Block 1.8V (typ)
Supply
VSS3
- Ground Pin 0V
Power Supply
Digital Power
DVDD
- Power Supply Pin for Digital Block 3.3V (typ)
Supply
Ground Pin 0V (silicon board potential)
VSS2
Power Supply
Connect to VSS1.
SRC Soft Mute Pin
PSRC
SRC1 and SRC2 blocks are soft muted by the PSRCSMUTE pin =
I
SRC
SMUTE
“H”. Control register RSRCSMUTE bit = “1” can also soft mutes
these blocks.
MS1337-E-00-PB
2011/11
- 9-
[AK7782]
No. Pin Name
I/O
Function
Classification
72
TESTI2
I
Test Pin (Internal pull-down)
Connect to VSS3.
Test
73
AVDD
-
Power Supply Pin for Analog Block 3.3V (typ)
Analog Power
Supply
74
VSS1
-
Ground Pin 0V (silicon board potential)
Power Supply
75
NC
-
76
NC
-
77
78
79
80
81
82
83
AINM
AINR4
AINL4
AINR3
AINL3
AINR2
AINL2
I
I
I
I
I
I
I
NC Pin
Connect to VSS1.
NC Pin
Connect to VSS1.
ADCM Mono Single-ended Input Pin
Rch Single-ended Input Pin for ADC1 or ADC2
Lch Single-ended Input Pin for ADC1 or ADC2
Rch Single-ended Input Pin for ADC1 or ADC2
Lch Single-ended Input Pin for ADC1 or ADC2
Rch Single-ended Input Pin for ADC1 or ADC2
Lch Single-ended Input Pin for ADC1 or ADC2
84
AVDD
-
Power Supply Pin for analog Block 3.3V (typ)
NC
NC
Analog Input
Analog Power
Supply
Reference voltage Input Pin for analog Block
Connect this pin to AVDD, and connect a 0.1μF and 10μF capacitors Analog Input
between this pin and VSS1.
Common voltage Output Pin for analog Block
Analog Output
86
VCOM
O
Connect a 0.1μF and 10μF capacitors between this pin and VSS1.
Do not connect to external circuits.
Reference voltage input Pin for analog Block
87
VREFL
I
Analog Input
Normally, this pin is connected to VSS1.
88
VSS1
- Ground Pin 0V (silicon board potential)
Power Supply
89
AINRI Rch Differential Input Pin for ADC1 or ADC2
90
AINR+
I Rch Differential Input Pin for ADC1 or ADC2
91
AINLI Lch Differential Input Pin for ADC1 or ADC2
92
AINL+
I Lch Differential Input Pin for ADC1 or ADC2
93
AINR5
I Rch Single-ended Input Pin for ADC1 or ADC2
94
AINL5
I Lch Single-ended Input Pin for ADC1 or ADC2
Analog Input
95
AINR6
I Rch Single-ended Input Pin for ADC1 or ADC2
96
AINL6
I Lch Single-ended Input Pin for ADC1 or ADC2
97
AINR7
I Rch Single-ended Input Pin for ADC1 or ADC2
98
AINL7
I Lch Single-ended Input Pin for ADC1 or ADC2
99
AINR8
I Rch Single-ended Input Pin for ADC1 or ADC2
100
AINL8
I Lch Single-ended Input Pin for ADC1 or ADC2
Note 1. All digital input pins must not be allowed to float.
Note 2. If analog input pins (AINR-, AINR+, AINL-, AINL+, AINL2~8, AINR2~8, AINM) are not used, leave them
open.
Note 3. The I2CSEL pin should be fixed to “L” (VSS3) or “H” (DVDD).
85
VREFH
I
MS1337-E-00-PB
2011/11
- 10-
[AK7782]
■ Handling of Unused Pins
Unused I/O pins must be connected appropriately.
Pin Name
AINL+, AINL-, AINR+, AINR-, AINL2, AINR2, AINL3, AINR3, AINL4, AINR4,
Analog
AINL5, AINR5, AINL6, AINR6, AINL7, AINR7, AINL8, AINR8, AINM
XTO, LRCLKO, BITCLKO, SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5,
CLKO1, SO, RDY, STO, SDOTUA1, SDOUT6, SDOUT7, SDA (I2CSEL= “L”)
Digital
TESTI1, SRC2LRCK, SRC2BICK, XTI, SDIN2, SDIN3, SDIN4, SDIN5,
PCKRSTN, PADRSTN, SDIN7/JX2, SDIN6/JX1, JX0, SDIN1, SRCBICK,
SRCLRCK, PSRCRSTN, PSRCSMUTE, TESTI2
Relationship between the I2CSEL pin and the SDA
I2CSEL
Normal Microcomputer
L
Interface
L
I2C-bus
H
H
MS1337-E-00-PB
INITRSTN
L
H
L
H
Setting
Leave Open
Leave Open
Connect to VSS3
SDA
L
L
“Hi-Z” → pull-up
function
2011/11
- 11-
[AK7782]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=0V; Note 4)
Parameter
Symbol
min
Power Supply Voltage
VA
Analog (AVDD)
-0.3
VD
Digital (DVDD)
-0.3
VD18
Digital (DVDD18)
-0.3
ΔGND
|VSS1(VSS2) – VSS3| (Note 5)
-0.3
Input Current (except for power supply pin)
IIN
–
Analog Input Voltage
AINL+, AINL-, AINR+, AINR-,
VINA
-0.3
AINL2~8, AINR2~8, AINM
VREFH, VREFL
Digital Input Voltage
VIND
-0.3
Operational Ambient Temperature
Ta
-40
Storage Temperature
Tstg
-65
Note 4. All voltages with respect to ground.
Note 5. VSS1, VSS2 and VSS3 must be connected to the same ground plane.
max
Unit
4.3
4.3
2.5
+0.3
±10
V
V
V
V
mA
(VA+0.3) ≤ 4.3
V
(VD+0.3) ≤ 4.3
85
150
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATION CONDITION
(VSS1=VSS2=VSS3=0V; Note 4)
Parameter
Symbol
min
typ
max
Unit
Power Supply Voltage
AVDD
VA
3.0
3.3
3.6
V
DVDD
VD
3.0
3.3
3.6
V
DVDD18
VD18
1.7
1.8
1.9
V
AVDD-DVDD
ΔVDD
-0.3
0
+0.3
V
Reference Voltage (VREF)
VREFH
(Note 6)
VRH
VA
V
VREFL
(Note 7)
VRL
0.0
V
Note 4. All voltages with respect to ground.
Note 6. The VREFH pin is normally connected to AVDD.
Note 7. The VREFL pin is normally connected to VSS1.
Note 8. The analog input voltage is proportional to the (VREFH-VREFL) voltage.
Note 9. The power-up sequence between AVDD, DVDD and DVDD18 is not critical. The INITRSTN pin should be held
“L” when power is supplied. The INITRSTN pin is allowed to be “H” after all power supplies are applied and
settled.
Note 10. Do not turn off the power supply of the AK7782 when the power supplies of the surrounding device are turned
on in I2C-bus mode (I2CSEL pin = “H”). Pull-up resistors at SDA and SCL pins must be connected to the DVDD
voltage or less. (A diode exists for DVDD in the SDA and SCL pins.)
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
MS1337-E-00-PB
2011/11
- 12-
[AK7782]
ANALOG CHARACTERISTICS
(1) Analog Characteristics
1-1) ADC
(Ta=25°C; AVDD=DVDD=3.3V; DVDD18=1.8V, VREFH=AVDD, VREFL=VSS1, BITCLK=64fs; Signal frequency
1kHz; Measurement [email protected], [email protected]; ADC full differential input (ADC1,
ADC2); CKM Mode 0 (CKM[2:0]=000), during SRC reset, unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
24
Bits
Stereo
ADC
Dynamic Characteristics
S/(N+D)
fs = 48kHz (-1dBFS) Note 11)
82
90
dB
ADC1
fs = 96kHz (-1dBFS)
87
dB
ADC2
Dynamic Range
fs = 48kHz (A-filter) Note 11, Note 12)
88
96
dB
fs = 96kHz
93
dB
S/N
fs = 48kHz (A-filter) Note 11)
88
96
dB
fs = 96kHz
93
dB
Inter-channel Isolation (f=1kHz) Note 13)
90
115
dB
DC Accuracy
Channel Gain Mismatch
0.0
0.3
dB
Analog Input
Input Voltage (Differential Input)
Note 14)
±1.85
±2.00
±2.15
Vp-p
Input Voltage (Single-ended Input)
Note 15)
1.85
2.00
2.15
Vp-p
Note 16)
22
33
kΩ
Input Impedance
Resolution
24
Bits
Mono
ADC
Dynamic Characteristics
S/(N+D)
fs = 48kHz (-1dBFS)
78
88
dB
ADCM
fs = 96kHz (-1dBFS)
87
dB
Dynamic Range
fs = 48kHz (A-filter) Note 12)
87
95
dB
fs = 96kHz
92
dB
S/N
fs = 48kHz (A-filter)
87
95
dB
fs = 96kHz
92
dB
Analog Input
Input Voltage
Note 17)
1.85
2.00
2.15
Vp-p
Note 18)
22
33
kΩ
Input Impedance
Note 11. Values are not guaranteed with single-ended inputs.
Note 12. S/(N+D) when -60dB signal is applied.
Note 13. Inter-channel isolation between L-channel and R-channel at –1dBFS signal input.
Note 14. AINL+, AINL-, AINR+, and AINR- pins.
The full scale for differential input voltage is (± FS= ± (VREFH-VREFL) x (2.0/3.3)).
Note 15. AINL2~L8, and AINR2~R8 pins.
The full scale of single-ended input voltage (FS=(VREFH-VREFL) x (2.0/3.3)).
Note 16. AINL+, AINL-, AINR+, AINR-, AINL2~L8, and AINR2~R8 pins.
Note 17. AINM pin. The full scale of input voltage is (FS=(VREFH-VREFL) x (2.0/3.3)).
Note 18. AINM pin.
MS1337-E-00-PB
2011/11
- 13-
[AK7782]
1-2) SRC
(Ta=25°C; AVDD = 3.3V; DVDD=3.3V; DVDD18=1.8V; data = 24bit; measurement bandwidth = 20Hz∼ FSO/2, unless
otherwise specified.)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
7.35
96
kHz
Output Sample Rate
FSO
7.35
96
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
-112
dB
FSO/FSI=44.1kHz/96kHz
-112
dB
FSO/FSI=48kHz/44.1kHz
-112
dB
FSO/FSI=48kHz/96kHz
-112
dB
FSO/FSI=48kHz/8kHz
-111
-103
dB
FSO/FSI=8kHz/48kHz
-112
dB
FSO/FSI=8kHz/44.1kHz
-100
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
113
dB
FSO/FSI=44.1kHz/96kHz
113
dB
FSO/FSI=48kHz/44.1kHz
113
dB
FSO/FSI=48kHz/96kHz
113
dB
FSO/FSI=48kHz/8kHz
109
112
dB
FSO/FSI=8kHz/48kHz
113
dB
FSO/FSI=8kHz/44.1kHz
113
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted
FSO/FSI=44.1kHz/48kHz
115
dB
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
6
MS1337-E-00-PB
2011/11
- 14-
[AK7782]
DC CHARACTERISTICS
(Ta=-40°C~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
High Level Input Voltage
Note 19)
VIH
80%DVDD
Low Level Input Voltage
Note 19)
VIL
SCL, SDA High Level Input Voltage
VIH
70%DVDD
SCL, SDA Low Level Input Voltage
VIL
VOH
DVDD-0.5
High Level Output Voltage Iout=-100μA
VOL
Low Level Output Voltage Iout=100μA Note 20)
SDA Low Level Output Voltage Iout=3mA
VOL
Input Leak Current
Note 21)
Iin
Note 22)
Input Leak Current (pull-down pin)
Iid
Input Leak Current (XTI pin)
Iix
typ
max
Unit
V
20%DVDD
V
V
30%DVDD
V
V
0.5
V
0.4
V
±10
μA
22
μA
26
μA
Note 19. Except for the SDA pin and the SCL pin (when I2CSEL= “1”). The SCLK pin is included when I2CSEL = “0”.
Note 20. Except for the SDA pin.
Note 21. Except for the XTI pin and pull-down pins.
Note 22. Pull-down pins (typ. 150kΩ) are the TESTI1 and TESTI2 pins.
POWER CONSUMPTION
(Ta=25°C, AVDD=DVDD=3.0~3.6V(typ=3.3V, max=3.6V), DVDD18=1.7~1.9V(typ=1.8V, max=1.9V))
Parameter
min
typ
max
Unit
Power Supply Current (Note 23)
1) a) AVDD
52
70
mA
b) DVDD
8
15
mA
c) DVDD18
140
210
mA
Note 23. The current of DVDD18 changes depending on the system frequency and contents of the DSP program.
MS1337-E-00-PB
2011/11
- 15-
[AK7782]
DIGITAL FILTER CHARACTERISTICS
1) ADC1, ADC2
(Ta=-40°C~85°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; fs=48kHz (Note 24))
Parameter
Symbol
min
typ
max
Unit
Passband (±0.005dB) (Note 25)
PB
0
21.5
kHz
(-0.02dB)
21.768
kHz
(-6.0dB)
23.99
kHz
Stopband
SB
26.54
kHz
Passband Ripple
(Note 25)
PR
±0.005
dB
Stopband Attenuation
(Note 26, Note 27)
SA
80
dB
Group Delay Distortion
0
ΔGD
μs
Group Delay
(Ts=1/fs)
GD
29
Ts
Digital Delay Filter + Analog Filter
Amplitude Characteristics 20Hz~20.0kHz
±0.01
dB
Note 24. Frequency of each amplitude characteristic is in proportion to fs (sampling rate). The characteristic of the high
pass filter is not included.
Note 25. The passband is from DC to 21.5kHz when fs=48kHz.
Note 26. The stopband is from 26.5kHz to 3.0455MHz when fs = 48kHz.
Note 27. When fs = 48 kHz, the analog modulator samples the analog input at 3.072MHz. There is no attenuation of an
input signal in band of integer times (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3…) of the sampling frequency by
the digital filter.
2) ADCM
(Ta=-40°C ~85°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V fs=48kHz; (Note 24))
Parameter
Symbol
min
typ
max
Unit
Passband (±0.005dB) (Note 25)
PB
0
21.5
kHz
(-0.02dB)
21.768
kHz
(-6.0dB)
23.99
kHz
Stopband
SB
26.54
kHz
Passband Ripple
(Note 25)
PR
±0.005
dB
Stopband Attenuation
(Note 26, Note 27)
SA
80
dB
Group Delay Distortion
0
ΔGD
μs
Group Delay (Ts=1/fs) (Note 28)
GD
29
Ts
Digital Delay Filter + Analog Filter
Amplitude Characteristics 20Hz~20.0kHz
±0.1
dB
Note 24. Frequency of each amplitude characteristic is in proportion to fs (sampling rate). The characteristic of the high
pass filter is not included.
Note 25. The passband is from DC to 21.5kHz when fs=48kHz.
Note 26. The stopband is from 26.5kHz to 3.0455MHz when fs = 48kHz.
Note 27. When fs = 48 kHz, the analog modulator samples the analog input at 3.072MHz. There is no attenuation of an
input signal in band of integer times (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3…) of the sampling frequency by the digital
filter.
Note 28. 1Ts additional delay occurs in VOL + MUX path.
MS1337-E-00-PB
2011/11
- 16-
[AK7782]
3) SRC (Common for SRC1 and SRC2)
(Ta=-40°C ~85°C; AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
typ
max
Passband -0.01dB
0.980≤FSO/FSI≤6.000
PB
0
0.4583FSI
0.900≤FSO/FSI<0.990
PB
0
0.4167FSI
0.533≤FSO/FSI<0.909
PB
0
0.2182FSI
0.490≤FSO/FSI<0.539
PB
0
0.2177FSI
0.450≤FSO/FSI<0.495
PB
0
0.1948FSI
0.225≤FSO/FSI<0.455
PB
0
0.0917FSI
0.167≤FSO/FSI<0.227
PB
0
0.0917FSI
Stopband
0.980≤FSO/FSI≤6.000
SB
0.5417FSI
0.900≤FSO/FSI<0.990
SB
0.5021FSI
0.533≤FSO/FSI<0.909
SB
0.2974FSI
0.490≤FSO/FSI<0.539
SB
0.2812FSI
0.450≤FSO/FSI<0.495
SB
0.2604FSI
0.225≤FSO/FSI<0.455
SB
0.1573FSI
0.167≤FSO/FSI<0.227
SB
0.1354FSI
Passband Ripple
0.225≤FSO/FSI≤6.000
PR
±0.01
0.167≤FSO/FSI<0.227
PR
±0.0612
Stopband Attenuation
0.450≤FSO/FSI≤6.000
SA
95.2
0.167≤FSO/FSI<0.455
SA
92.3
Group Delay (Ts=1/fs) (Note 29)
GD
56
Note 29. SRC delay time is calculated from the rising edge of SRCLRCK just after data input to the rising edge of
LRCLKO just after data output, when there is no phase difference between SRCLRCK and LRCLKO.
MS1337-E-00-PB
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
Ts
2011/11
- 17-
[AK7782]
SWITCHING CHARACTERISTICS
[#h indicates hexadecimal numbers. (#=0, 1, 2 ~ 9, A, B, C, D, E, F)]
1) System Clock
(Ta=-40°C~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
XTI
CKM[2:0] 0h, 1h, 2h, 3h
a) with a Crystal Oscillator
CKM[2:0]=0h, 2h
fXTI
CKM[2:0]=1h, 3h
fXTI
b) with an External Clock
Duty Cycle
CKM[2:0]=0h, 2h
CKM[2:0]=1h, 3h
LRCLKI Frequency
(Note 30)
fXTI
fXTI
fs
40
11.0
16.5
7.35
typ
11.2896
12.288
16.9344
18.432
50
48
BITCLKI Frequency
High Level Width
tBCLKH
64
Low Level Width
tBCLKL
64
fBCLK
64
a) CKM[2:0]=2h, 3h
Duty Cycle
40
50
CKM[2:0]=2h, 3h
0.23
b) CKM[2:0]=4h, 5h
(Note 31)
64
fBCLK
Duty Cycle
40
50
CKM[2:0]=4h
fBCLK
2.75
CKM[2:0]=5h
fBCLK
5.5
Note 30. LRCLK frequency and sampling rate (fs) should be the same.
Note 31. BITCLKI is a source of master clock. It should be 64 times fs correctly.
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
SRCLRCK Frequency
(Note 30) fs
7.35
SRCBICK Frequency
High Level Width
Low Level Width
(Note 32)
Duty Cycle
64
64
32
40
0.23
Note 30. LRCLK frequency and sampling rate (fs) should be the same.
Note 32. The maximum value 128fs is achieved when fs ≤ 48kHz.
typ
48
tBCLKH
tBCLKL
fBCLK
MS1337-E-00-PB
max
50
Unit
MHz
MHz
60
12.4
18.6
96
%
MHz
MHz
kHz
60
3.1
6.2
ns
ns
fs
%
MHz
fs
%
MHz
MHz
max
96
Unit
kHz
128
60
6.2
ns
ns
fs
%
MHz
60
6.2
2011/11
- 18-
[AK7782]
2) Reset
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V)
Parameter
Symbol
min
INITRSTN
(Note 33) tRST
600
PCKRSTN
tRST
600
PADRSTN
tRST
600
PDSPRSTN
tRST
600
PSRCRSTN
tRST
600
Note 33. The INITRSTN pin must be “L” when power-up the AK7782.
typ
max
Unit
ns
ns
ns
ns
ns
3) Audio Interface
3-1) SDIN1~ SDIN7, SDOUT1~ SDOUT7 and SDOUTA1 (supports up to fs=96kHz)
MSB, LSB justified and I2S Compatible Format
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, CL=20pF)
Parameter
Symbol
Slave Mode CKM[2:0]=2h, 3h, 4h, 5h
Delay Time from BITCLKI “↑” to LRCLKI
(Note 34) tBLRD
Delay Time from LRCLKI to BITCLKI “↑”
(Note 34) tLRBD
Delay Time from LRCLKI/O to Serial Data Output
tLRD
Delay Time from BITCLKI/O to Serial Data Output
tBSOD
Serial Data Input Latch Setup Time
tBSIDS
Serial Data Input Latch Hold Time
tBSIDH
Master Mode CKM[2:0]=0h, 1h
BITCLKO Frequency
fBCLK
BITCLKO Duty Cycle
Delay Time from BITCLKI “↓” to LRCLKO
tMBL
Delay Time from LRCLKO to Serial Data Output
tLRD
Delay Time from BITCLKO to Serial Data Output
tBSOD
Serial Data Input Latch Setup Time
tBSIDS
Serial Data Input Latch Hold Time
tBSIDH
Note 34. BITCLKI edge must not occur at the same time as LRCLKI edge.
min
typ
max
Unit
40
40
ns
ns
ns
ns
ns
ns
20
20
40
40
64
50
-20
40
40
40
40
40
fs
%
ns
ns
ns
ns
ns
3-2) SDIN1 and SDIN5 (SRC1I and SRC2I Inputs) (supports up to fs=96kHz)
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
min
Slave Mode
Delay Time from SRCBICK1 “↑” to SRCLRCK1 (Note 35) tBLRD
20
Delay Time from SRCLRCK1 to SRCBICK1 “↑” (Note 35) tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
40
Serial Data Input Latch Hold Time
tBSIDH
40
Note 35. SRCBICK1 edge must not occur at the same time as SRCLRCK1 edge.
MS1337-E-00-PB
typ
max
Unit
ns
ns
ns
ns
2011/11
- 19-
[AK7782]
4) Microprocessor Interface
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V, CL=20pF)
Parameter
Symbol
min
Microprocessor Interface Signal
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL
200
SCLK High Level Width
tSCLKH
200
Microprocessor → AK7782
Time from PDSPRSTN, PADRSTN“↓” to RQN“↓”
tREW
500
Time from RQN“↑” to PDSPRSTN, PADRSTN“↑”
tWRE
500
RQN High Level Width
tWRQH
500
Time from RQN“↓” to SCLK“↓”
tWSC
500
Time from SCLK“↑” to RQN“↑”
tSCW
800
SI Latch Setup Time
tSIS
200
SI Latch Hold Time
tSIH
200
AK7782 ← Microprocessor
Delay Time from SCLK “↓” to SO Output
tSOS
Delay Time from SCLK “↑” to SO Output
tSOH
200
Time from RQN “↓” to SO Hi-Z Release
tRQHR
(Iout=±360μA)
Time from RQN “↑” to SO Hi-Z set (Iout=±360μA)
tRQHS
MS1337-E-00-PB
typ
max
Unit
2.1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
ns
ns
600
ns
600
ns
2011/11
- 20-
[AK7782]
5) I2C-BUS Interface
(Ta=-40°C ~85°C, AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V)
Parameter
Symbol
I2C Timing
SCL clock frequency
fSCL
Bus Free Time Between Transmissions
tBUF
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
Clock Low Time
tLOW
Clock High Time
tHIGH
Setup Time for Repeated Start Condition
tSU:STA
min
max
tHD:DAT
0
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
tSU:DAT
tR
0.1
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
By Input Filter
Capacitive load on bus
tSU:STO
tSP
0.6
0
Unit
400
kHz
μs
μs
μs
μs
μs
0.9
μs
0.3
μs
μs
0.3
μs
50
μs
ns
400
pF
1.3
0.6
1.3
0.6
0.6
SDA Hold Time from SCL Falling
Cb
typ
2
Note 36. I C-bus is a trademark of NXP B.V.
MS1337-E-00-PB
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■ Timing Diagram
1) System Clock
1/fXTI
1/fXTI
tXTI=1/fXTI
VIH
XTI
VIL
1/fs
ts=1/fs
1/fs
VIH
LRCLKI
SRCLRCK
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BITCLKI
SRCBICK
VIL
tBCLKH
tBCLKL
Figure 3. System Clock
2) Reset
INITRSTN
PCKRSTN
tRST
PADRSTN
VIL
PDSPRSTN
PSRCRSTN
Figure 4. Reset
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3) Audio Interface
LRCLKI
50%DVDD
LRCLKO
tBLRD
tMB tMBL
tLRBD
BITCLKI
50%DVDD
BITCLKO
tLRD
tBSOD
SDOUT *
50%DVDD
tBSIDS
tBSIDH
SDIN *
50%DVDD
SDIN * =SDIN1, SDIN2, SDIN3, SDIN4, SDIN5, SDIN6, SDIN7
SDOUT * =SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5, SDOUT6, SDOUT7, SDOUTA1
Figure 5. Standard / I2C Compatible Format
SRCLRCK
SRCLRCK2
50%DVDD
tBLRD
tLRBD
50%DVDD
SRCBICK
SRCBICK2
tBSIDS
SRCI=
SDIN1,SDIN5
tBSIDH
50%DVDD
Figure 6. SRC
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4) Microprocessor Interface
VIH
VIL
RQN
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
Figure 7. Microprocessor Interface Signal
tWRE
tREW
PDSPRSTN
VIL
PADRSTN
RQN
VIH
VIL
tWRQH
tWSC
VIH
SI
VIL
tSIS
tSIH
VIH
VIL
SCLK
tSCW
tWSC
tSCW
Figure 8. Microprocessor → AK7782
VIH
VIL
SCLK
VIH
SO
VIL
tSOS
tSOH
Figure 9. AK7782 → Microprocessor
Note 37. The timing diagram during RUN state is identical except PDSPRSTN and PASRSTN are “H”.
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VIH
VIL
RQN
tRQHS
tRQHR
Hi-Z
SO
Figure 10. SO Output Timing
2
5) I C-bus Interface
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 11. I2C-bus Interface
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PACKAGE
100-pin LQFP
(Unit: mm)
1.60 Max.
16.0
14.0
76
50
100
26
14.0
16.0
0.10±0.05
51
75
25
1
0.5
0.22±0.05
0.09~0.20
0.10
M
1.0
S
0°~10°
0.60±0.15
0.10
S
■ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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MARKING
AK7782VQ
XXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK7782VQ
REVISION HISTORY
Date (YY/MM/DD)
11/11/02
Revision
00
Reason
First Edition
Page
MS1337-E-00-PB
Contents
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[AK7782]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
Thank you for your access to AKM product information.
More detail product information is available, please contact our
sales office or authorized distributors.
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