TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 www.ti.com SLVSAI3 – SEPTEMBER 2010 Cap-Free, NMOS, 400mA Low-Dropout Regulator with Reverse Current Protection Check for Samples: TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 FEATURES 1 • • 2 • • • • • • • • • • Qualified for Automotive Applications Stable with No Output Capacitor or Any Value or Type of Capacitor Input Voltage Range of 1.7V to 5.5V Ultra-Low Dropout Voltage: 75mV typ Excellent Load Transient Response—with or without Optional Output Capacitor New NMOS Topology Delivers Low Reverse Leakage Current Low Noise: 30mVRMS typ (10Hz to 100kHz) 0.5% Initial Accuracy 1% Overall Accuracy Over Line, Load, and Temperature Less Than 1mA max IQ in Shutdown Mode Thermal Shutdown and Specified Min/Max Current Limit Protection Available in Multiple Output Voltage Versions – Fixed Outputs of 1.20V to 3.3V – Adjustable Output from 1.20V to 5.5V Optional VIN DESCRIPTION The TPS736xx family of low-dropout (LDO) linear voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR, and even allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current. The TPS736xx uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is under 1mA and ideal for portable applications. The extremely low output noise (30mVRMS with 0.1mF CNR) is ideal for powering VCOs. These devices are protected by thermal shutdown and foldback current limit. space Optional IN VOUT OUT TPS736xx EN GND NR ON OFF Optional Typical Application Circuit for Fixed-Voltage Versions space 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 SLVSAI3 – SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TA OUTPUT VOLTAGE ORDERABLE PART NUMBER PACKAGE (2) adjustable –40°C to 125°C 2.5 V TPS73601QDBVRQ1 SOT (SOT-23) – DBV Reel of 3000 3.3 V (1) (2) (3) TOP-SIDE MARKING PTWQ (3) PREVIEW TPS73633QDBVRQ1 (3) PREVIEW TPS73625QDBVRQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Product Preview ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) PARAMETER TPS736xx UNIT VIN range –0.3 to 6.0 V VEN range –0.3 to 6.0 V VOUT range –0.3 to 5.5 V VNR, VFB range –0.3 to 6.0 V Peak output current Internally limited Output short-circuit duration Indefinite Continuous total power dissipation See Thermal Information Table Junction temperature range, TJ –40 to +150 °C Storage temperature range –65 to +150 °C (1) 2 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 www.ti.com SLVSAI3 – SEPTEMBER 2010 THERMAL INFORMATION DBV (2) THERMAL METRIC (1) 5 PINS qJA Junction-to-ambient thermal resistance (3) 180 qJCtop Junction-to-case (top) thermal resistance (4) 64 (5) qJB Junction-to-board thermal resistance yJT Junction-to-top characterization parameter (6) yJB Junction-to-board characterization parameter (7) N/A (8) N/A qJCbot (1) (2) (3) (4) (5) (6) (7) (8) Junction-to-case (bottom) thermal resistance 35 N/A UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. Thermal data for the DBV package is derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) DBV: There is no exposed pad with the DBV package. (b) DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 3 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 SLVSAI3 – SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS Over operating temperature range (TA = –40°C to +125°C), VIN = VOUT(nom) + 0.5V (1), IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS VIN Input voltage range (1) (2) VFB Internal reference (TPS73601) Accuracy (1) (4) ΔVOUT%/ΔVIN MAX UNIT 5.5 TJ = +25°C V 1.210 V VFB 5.5 – VDO V +0.5 1.198 Nominal TJ = +25°C –0.5 over VIN, IOUT, and T VOUT + 0.5V ≤ VIN ≤ 5.5V; 10mA ≤ IOUT ≤ 400mA –1.0 Line regulation (1) ΔVOUT%/ΔIOUT Load regulation ±0.5 0.01 1mA ≤ IOUT ≤ 400mA 0.002 10mA ≤ IOUT ≤ 400mA 0.0005 Dropout voltage (5) (VIN = VOUT(nom) – 0.1V) IOUT = 400mA ZO(DO) Output impedance in dropout 1.7V ≤ VIN ≤ VOUT + VDO ICL Output current limit ISC Short-circuit current Reverse leakage current 1.20 VO(nom) + 0.5V ≤ VIN ≤ 5.5V VDO IREV TYP 1.7 Output voltage range (TPS73601) (3) VOUT MIN 75 VOUT = 0.9 × VOUT(nom) 400 3.6V ≤ VIN ≤ 4.2V, 0°C ≤ TJ ≤ +70°C 500 650 IGND GND pin current ISHDN Shutdown current (IGND) IFB FB pin current (TPS73601) (–IIN) % %/V %/mA 200 mV Ω 0.25 VOUT = 0V (6) +1.0 800 mA 800 mA 450 mA VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT 0.1 10 IOUT = 10mA (IQ) 400 550 IOUT = 400mA 800 1000 VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5, –40°C ≤ TJ ≤ +100°C 0.02 1.3 mA 0.1 0.45 mA PSRR Power-supply rejection ratio (ripple rejection) VN Output noise voltage BW = 10Hz – 100KHz COUT = 10mF, No CNR 27 × VOUT COUT = 10mF, CNR = 0.01mF 8.5 × VOUT tSTR Startup time VEN(HI) EN pin high (enabled) 1.7 VIN V VEN(LO) EN pin low (shutdown) 0 0.5 V IEN(HI) EN pin current (enabled) 0.1 mA Thermal shutdown temperature TA Operating ambient temperature 4 37 VOUT = 3V, RL = 30Ω COUT = 1mF, CNR = 0.01mF TSD (3) (4) (5) (6) f = 10KHz, IOUT = 400mA mA f = 100Hz, IOUT = 400mA (1) (2) 58 mA dB mVRMS 600 VEN = 5.5V 0.02 Shutdown, temperature increasing +160 Reset, temperature decreasing +140 –40 ms °C +125 °C Minimum VIN = VOUT + VDO or 1.7V, whichever is greater. For VOUT(nom) < 1.6V, when VIN ≤ 1.6V, the output will lock to VIN and may result in a damaging over-voltage level on the output. To avoid this situation, disable the device before powering down the VIN. TPS73601 is tested at VOUT = 2.5V. Tolerance of external resistors not included in this specification. VDO is not measured for fixed output versions with VOUT(nom) < 1.8V. Fixed-voltage versions only; refer to Applications section for more information. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 www.ti.com SLVSAI3 – SEPTEMBER 2010 FUNCTIONAL BLOCK DIAGRAMS IN 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp Current Limit OUT 8kΩ GND R1 R1 + R2 = 80kΩ R2 NR Figure 1. Fixed Voltage Version IN Table 1. Standard 1% Resistor Values for Common Output Voltages VO 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp GND R2 1.2V Short Open 1.5V 23.2kΩ 95.3kΩ 1.8V 28.0kΩ 56.2kΩ 2.5V 39.2kΩ 36.5kΩ 2.8V 44.2kΩ 33.2kΩ 3.0V 46.4kΩ 30.9kΩ 3.3V 52.3kΩ 30.1kΩ NOTE: VOUT = (R1 + R2)/R2 × 1.204; R1R2 ≅ 19kΩ for best accuracy. OUT Current Limit R1 80kΩ 8kΩ R1 FB R2 Figure 2. Adjustable Voltage Version Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 5 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 SLVSAI3 – SEPTEMBER 2010 www.ti.com PIN CONFIGURATION PIN DESCRIPTIONS 6 NAME SOT23 (DBV) PIN NO. IN 1 Input supply GND 2 Ground EN 3 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to IN if not used. NR 4 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels. FB 4 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 5 Output of the Regulator. There are no output capacitor requirements for stability. DESCRIPTION Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 www.ti.com SLVSAI3 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise noted. LOAD REGULATION LINE REGULATION 0.20 0.5 Referred to IOUT = 10mA −40_C +25_C +125_ C Change in VOUT (%) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 Referred to VIN = VOUT + 0.5V at IOUT = 10mA 0.15 Change in VOUT (%) 0.4 0.10 0 −0.05 −40_ C −0.10 −0.15 −0.4 −0.20 −0.5 0 50 100 150 200 250 300 350 0 400 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN − VOUT (V) IOUT (mA) Figure 3. Figure 4. DROPOUT VOLTAGE vs OUTPUT CURRENT 100 DROPOUT VOLTAGE vs TEMPERATURE 100 TPS73625DBV +125_ C 80 80 60 VDO (mV) VDO (mV) +25_ C +125_C 0.05 +25_ C 40 −40_C 20 50 100 150 200 250 300 60 40 20 0 −50 0 0 TPS73625DBV I OUT = 400mA 350 400 −25 0 25 50 IOUT (mA) Temperature (_ C) Figure 5. Figure 6. OUTPUT VOLTAGE ACCURACY HISTOGRAM 75 100 125 OUTPUT VOLTAGE DRIFT HISTOGRAM 30 18 IOUT = 10mA 16 25 IOUT = 10mA All Voltage Versions Percent of Units (%) Percent of Units (%) 14 20 15 10 12 10 8 6 4 5 2 0 −1.0 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 0 VOUT Error (%) Worst Case dVOUT/dT (ppm/_C) Figure 7. Copyright © 2010, Texas Instruments Incorporated Figure 8. Submit Documentation Feedback Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 7 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 SLVSAI3 – SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise noted. GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE 900 900 800 800 700 700 600 600 I GND (µA) 1000 IGND (µA) 1000 500 400 300 500 400 300 VIN = 5.5V VIN = 4V VIN = 2V 200 100 0 100 200 300 VIN = 5.5V VIN = 3V VIN = 2V 200 100 0 0 −50 400 −25 0 25 50 75 IOUT (mA) Temperature (_C) Figure 9. Figure 10. GROUND PIN CURRENT in SHUTDOWN vs TEMPERATURE CURRENT LIMIT vs VOUT (FOLDBACK) 100 125 800 1 TPS73633 VENABLE = 0.5V VIN = VO + 0.5V 700 Output Current (mA) IGND (µA) IOUT = 400mA 0.1 ICL 600 500 ISC 400 300 200 100 0.01 −50 −25 0 25 50 75 100 0 -0.5 125 0 0.5 Figure 11. 2.0 2.5 3.0 3.5 CURRENT LIMIT vs TEMPERATURE 800 800 750 750 700 700 Current Limit (mA) Current Limit (mA) 1.5 Figure 12. CURRENT LIMIT vs VIN 650 600 550 500 450 650 600 550 500 450 400 1.5 2.0 2.5 3.0 3.5 VIN (V) Figure 13. 8 1.0 Output Voltage (V) Temperature (_C) Submit Documentation Feedback 4.0 4.5 5.0 5.5 400 −50 −25 0 25 50 75 100 125 Temperature (_C) Figure 14. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 www.ti.com SLVSAI3 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise noted. PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN – VOUT 90 40 IOUT = 100mA COUT = Any Ripple Rejection (dB) 70 IOUT = 1mA COUT = 1µF 35 30 IOUT = 1mA COUT = 10µF 60 50 IO = 100mA CO = 1µF IOUT = 1mA C OUT = Any 40 25 PSRR (dB) 80 20 15 30 20 IOUT = Any COUT = 0µF 10 VIN = VOUT + 1V 0 10 100 1k 10k Frequency = 10kHz COUT = 10mF VOUT = 2.5V IOUT = 100mA 10 I OUT = 100mA COUT = 10µF 5 0 100k 1M 0 10M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Frequency (Hz) VIN - VOUT (V) Figure 15. Figure 16. NOISE SPECTRAL DENSITY CNR = 0mF NOISE SPECTRAL DENSITY CNR = 0.01mF 1 1.8 2.0 1 COUT = 0µF 0.1 COUT = 10µF eN (µV/√Hz) eN (µV/√Hz) C OUT = 1µF COUT = 1µF 0.1 COUT = 0µF COUT = 10µF IOUT = 150mA IOUT = 150mA 0.01 0.01 10 100 1k 10k 100k 10 100 1k Frequency (Hz) Frequency (Hz) Figure 17. Figure 18. RMS NOISE VOLTAGE vs COUT 10k 100k RMS NOISE VOLTAGE vs CNR 60 140 50 120 VOUT = 5.0V VOUT = 5.0V 100 30 VN (RMS) VN (RMS) 40 VOUT = 3.3V 80 VOUT = 3.3V 60 20 40 VOUT = 1.5V 10 0 20 CNR = 0.01µF 10Hz < Frequency < 100kHz 0.1 0 1 10 VOUT = 1.5V COUT = 0µF 10Hz < Frequency < 100kHz 1p 10p 100p COUT (µF) CNR (F) Figure 19. Figure 20. Copyright © 2010, Texas Instruments Incorporated 1n 10n Submit Documentation Feedback Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 9 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 SLVSAI3 – SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise noted. TPS73633 LOAD TRANSIENT RESPONSE VIN = 3.8V TPS73633 LINE TRANSIENT RESPONSE COUT = 0µF 100mV/tick IOUT = 400mA VOUT COUT = 0µF 50mV/div COUT = 1µF 50mV/tick COUT = 10µF 20mV/tick VOUT VOUT VOUT COUT = 100µF 50mV/div VOUT dVIN 5.5V 400mA IOUT 50mA/tick 10mA 4.5V 1V/div VIN 10µs/div 10µs/div Figure 21. Figure 22. TPS73633 TURN-ON RESPONSE TPS73633 TURN-OFF RESPONSE RL = 1kΩ CO UT = 0µF R L = 20Ω C OUT = 10µF VOUT RL = 20Ω COUT = 1µF 1V/div R L = 20Ω C OUT = 1µF 1V/div R L = 1kΩ C OUT = 0µF RL = 20Ω COUT = 10µF VOUT 2V 2V VEN 1V/div 1V/div 0V 0V VEN 100µs/div 100µs/div Figure 23. Figure 24. TPS73633 POWER UP / POWER DOWN IENABLE vs TEMPERATURE 10 6 5 4 VIN VOUT IENABLE (nA) 3 Volts = 0.5V/µs dt 2 1 1 0.1 0 −1 −2 50ms/div 0.01 −50 −25 0 25 50 75 100 125 Temperature (_ C) Figure 25. 10 Submit Documentation Feedback Figure 26. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 www.ti.com SLVSAI3 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise noted. TPS73601 IFB vs TEMPERATURE 60 160 55 140 50 120 45 100 IFB (nA) VN (rms) TPS73601 RMS NOISE VOLTAGE vs CFB 40 60 35 30 25 80 VOUT = 2.5V COUT = 0µF R1 = 39.2kΩ 10Hz < Frequency < 100kHz 20 10p 100p 40 20 1n 10n 0 −50 −25 0 25 50 75 100 CFB (F) Temperature (_C) Figure 27. Figure 28. TPS73601 LOAD TRANSIENT, ADJUSTABLE VERSION TPS73601 LINE TRANSIENT, ADJUSTABLE VERSION CFB = 10nF R1 = 39.2kΩ COUT = 0µF 200mV/div VOUT COUT = 0µF COUT = 10µF 200mV/div VOUT = 2.5V CFB = 10nF 100mV/div COUT = 10µF 100mV/div 125 VOUT VOUT VOUT 4.5V 400mA 3.5V VIN 10mA IOUT 25µs/div 5µs/div Figure 29. Figure 30. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 11 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 SLVSAI3 – SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION The TPS736xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS736xx ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit. Figure 31 shows the basic circuit connections for the fixed voltage models. Figure 32 gives the connections for the adjustable output version (TPS73601). Optional input capacitor. May improve source impedance, noise, or PSRR. VIN Optional output capacitor. May improve load transient, noise, or PSRR. IN VOUT OUT TPS736xx EN GND NR ON OFF Optional bypass capacitor to reduce output noise. Figure 31. Typical Application Circuit for Fixed-Voltage Versions Optional input capacitor. May improve source impedance, noise, or PSRR. VIN IN Optional output capacitor. May improve load transient, noise, or PSRR. VOUT OUT TPS73601 EN OFF GND R1 CFB FB ON R2 VOUT = (R1 + R2) R2 x 1.204 Optional capacitor reduces output noise and improves transient response. For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19kΩ. This 19kΩ, in addition to the internal 8kΩ resistor, presents the same impedance to the error amp as the 27kΩ bandgap reference output. This impedance helps compensate for leakages into the error amp terminals. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1mF to 1mF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. The TPS736xx does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement. OUTPUT NOISE A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS736xx and it generates approximately 32mVRMS (10Hz to 100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: (R1 ) R2) + 32mVRMS R2 V N + 32mVRMS Figure 32. Typical Application Circuit for Adjustable-Voltage Version R1 and R2 can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values for common output voltages are shown in Figure 2. 12 Submit Documentation Feedback VOUT VREF (1) Since the value of VREF is 1.2V, this relationship reduces to: ǒmVV Ǔ V N(mVRMS) + 27 RMS V OUT(V) (2) for the case of no CNR. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 www.ti.com SLVSAI3 – SEPTEMBER 2010 An internal 27kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of ~3.2, giving the approximate relationship: ǒmVV Ǔ V N(mVRMS) + 8.5 RMS V OUT(V) (3) for CNR = 10nF. This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section. The TPS73601 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient performance. The TPS736xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates ~250mV of switching noise at ~4MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT. BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. INTERNAL CURRENT LIMIT The TPS736xx internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below 0.5V. See Figure 12 in the Typical Characteristics section. Note from Figure 12 that approximately –0.2V of VOUT results in a current limit of 0mA. Therefore, if OUT is forced below –0.2V before EN goes high, the device may not start up. In applications that work with both a positive and negative voltage supply, the TPS736xx should be enabled first. Copyright © 2010, Texas Instruments Incorporated ENABLE PIN AND SHUTDOWN The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5V (max) turns the regulator off and drops the GND pin current to approximately 10nA. When EN is used to shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT (see Figure 23). When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may overshoot upon power-up. Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section for more information. DROPOUT VOLTAGE The TPS736xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS-ON of the NMOS pass element. For large step changes in load current, the TPS736xx requires a larger voltage drop from VIN to VOUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the dc dropout. Values of VIN – VOUT above this line ensure normal transient response. Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS736xx can take a couple of hundred microseconds to return to the specified regulation accuracy. Submit Documentation Feedback Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 13 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 SLVSAI3 – SEPTEMBER 2010 www.ti.com TRANSIENT RESPONSE The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value 1mF) from the OUT pin to ground will reduce undershoot magnitude but increase its duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin will also improve the transient response. The TPS736xx does not have active pull-down when the output is over-voltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by: (Fixed Voltage Version) dVńdt + C OUT VOUT 80kW ø R LOAD (4) (Adjustable Voltage Version) dVńdt + C OUT V OUT 80kW ø (R 1 ) R 2) ø R LOAD (5) REVERSE CURRENT The NMOS pass element of the TPS736xx provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate. 14 Submit Documentation Feedback After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There will be additional current flowing into the OUT pin due to the 80kΩ internal resistor divider to ground (see Figure 1 and Figure 2). For the TPS73601, reverse current may flow when VFB is more than 1.0V above VIN. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your application. This produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS736xx has been designed to protect against overload conditions. It was not intended to replace proper heat sinking. Continuously running the TPS736xx into thermal shutdown degrades device reliability. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 TPS73601-Q1, TPS73625-Q1, TPS73633-Q1 www.ti.com SLVSAI3 – SEPTEMBER 2010 POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal Information table. Using heavier copper will increase the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers will also improve the heat-sink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT): Copyright © 2010, Texas Instruments Incorporated space P D + (VIN * VOUT) I OUT (6) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. PACKAGE MOUNTING Solder pad footprint recommendations for the TPS736xx are presented in Application Bulletin Solder Pad Recommendations for Surface-Mount Devices (SBFA015), available from the Texas Instruments web site at www.ti.com. Submit Documentation Feedback Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 15 PACKAGE OPTION ADDENDUM www.ti.com 20-Nov-2010 PACKAGING INFORMATION Orderable Device TPS73601QDBVRQ1 Status (1) ACTIVE Package Type Package Drawing SOT-23 DBV Pins Package Qty 5 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF TPS73601-Q1 : • Catalog: TPS73601 • Enhanced Product: TPS73601-EP NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 20-Nov-2010 • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS73601QDBVRQ1 Package Package Pins Type Drawing SPQ SOT-23 3000 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 179.0 8.4 Pack Materials-Page 1 3.2 B0 (mm) K0 (mm) P1 (mm) 3.2 1.4 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73601QDBVRQ1 SOT-23 DBV 5 3000 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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