MDT1030 1. General Description This ROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speed and smaller size with the low power and high noise immunity of CMOS. On chip memory system includes 2.0 K bytes of ROM, and 80 bytes of static RAM. 2. Features The followings are some of the features on the hardware and software : u Fully CMOS static design u 8-bit data bus u On chip ROM size : 2.0 K words u Internal RAM size : 80 bytes (73 general purpose registers, 7 special registers) u 34 single word instructions u 12-bit instructions u 2-level stacks u Operating voltage : 2.3 V ~ 6.3 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u Power-on Reset u Power edge-detector Reset u Sleep Mode for power saving u 4 oscillator start-up time : 150 µs, 20 ms, 40 ms, 80 ms u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by code options : RC－Low cost RC oscillator LFXT－Low frequency crystal oscillator XTAL－Standard crystal oscillator HFXT－High frequency crystal oscillator u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely u Pull up resistors for the following pins : PA0~PA3, PB0~PB7, /MCLR, RTCC u Pull down resistors for the following pins : PA0~PA3, PB0~PB7, RTCC u 12 I/O pins with their own independent direction control 3. Applications The application areas of this MDT1030 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral … etc. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 2005 /6 VER1.4 MDT1030 4. Pin Assignment PA2 PA3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 5. Pin Function Description Pin Name I/O Function Description PA0~PA3 I/O Port A, TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC1 I Oscillator Input OSC2 O Oscillator Output Vdd Power supply Vss Ground This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 2005 /6 VER1.4 MDT1030 6. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07~0F Internal RAM, General Purpose Register 10~1F Internal Memory Select Register 30~3F Internal Memory Select Register 50~5F Internal Memory Select Register 70~7F Internal Memory Select Register (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 JUMP --- from instruction word RTWI, RET --- from STACK A10 A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b6 b5 RTWI, RET --- from STACK Write PC --- from ALU JUMP, CALL --- from instruction word RTWI, RET --- from STACK This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 2005 /6 VER1.4 MDT1030 (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF Time overflow Flag bit page Page select bit : 6—5 00 : 000H --- 1FFH 01 : 200H --- 3FFH 10 : 400H --- 5FFH 11 : 600H --- 7FFH General purpose bit 7 —— (5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 Read only “1” Indirect Addressing Mode (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 2005 /6 VER1.4 b0 MDT1030 (8) TMR (Time Mode Register) Bit Symbol Function Prescaler Value 2—0 PS2—0 3 PSC 4 TCE 5 TCS RTCC rate WDT rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1 : 16 1:8 1 0 0 1 : 32 1 : 16 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin (9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (10) Configuration ROM : Bit 1 Bit 0 Oscillator Type 0 0 RC 0 1 LFXT Oscillator 1 0 XTAL Oscillator 1 1 HFXT Oscillator Bit 3 Bit 2 0 0 150 µs 0 1 20 ms 1 0 40 ms 1 1 80 ms Oscillator Oscillator Start-up Time This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 2005 /6 VER1.4 MDT1030 Bit 4 Watchdog Timer control 0 Watchdog timer disable all the time 1 Watchdog timer enable all the time (B) Program Memory Address Description 000-7FF 7FF Program memory The starting address of the power on, external reset or WDT 7. Reset Condition for all Registers Register Address Power-On Reset /MCLR or WDT Reset CPIO A －－ 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 TMR －－ --11 1111 --11 1111 IAR 00h － － RTCC 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu MSR 04h 111x xxxx 111u uuuu PORT A 05h - - - - xxxx - - - - uuuu PORT B 06h xxxx xxxx uuuu uuuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) u u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2005 /6 VER1.4 MDT1030 8. Instruction Set Instruction Code Mnemonic Operands Function Operating Status 010000 000000 NOP No operation None 010000 000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 000010 SLEEP Sleep mode TF, PF 010000 000011 TMODE Load W to TMODE register 0→WT, stop OSC W→TMODE 010000 000100 RET Return Stack→PC None 010000 000rrr CPIO Control I/O port register W→CPIO 010001 1rrrrr STWR Store W to register W→R 011000 trrrrr LDR R, t Load register R→t Z 1110ii iiiiii LDWI Load immediate to W I→W None 010111 trrrrr SWAPR R, t Swap halves register [R(0~3) ↔ R(4~7)]→t None 011001 trrrrr INCR R, t R + 1→t Z 011010 trrrrr INCRSZ R, t R + 1→t None 011011 trrrrr Increment register, skip if zero ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrr SUBWR R, t Subtract W from register R ﹣W→t (R+/W+1→t) C, HC, Z 011101 trrrrr DECR R, t Decrement register R ﹣1→t Z 011110 trrrrr R ﹣1→t None 010010 trrrrr DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register R ∩ W→t Z 1101ii iiiiii ANDWI AND W and immediate i ∩ W→W Z 010011 trrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 1111 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 1011 iiiiiiii XORWI i i ♁ W→W Z 011111 trrrrr COMR R, t Complement register /R→t Z 010110 trrrrr RRR R, t Rotate right register R(n)→R(n-1), C→R(7), R(0)→C C 010101 trrrrr RLR R, t Rotate left register R(n)→r(n+1), C→R(0), R(7)→C C 010000 1xxxxx CLRW Clear working register 0→W Z 010001 0rrrrr CLRR Clear register 0→R Z R R I i R Increment register Exclu. OR W and immediate None r None This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2005 /6 None VER1.4 MDT1030 Mnemonic Operands Instruction Code Function Operating Status 0000bb brrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 1100 nnnnnnnn CALL Call subroutine n→PC, PC+1→Stack None 1010ii iiiiii RTWI 100n nnnnnnnn Note : W : WT : TMODE : CPIO : TF : PF : PC : OSC : Inclu. : Exclu. : AND : n i JUMP n Return, place immediate to W Stack→PC, i→W None JUMP to address None Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t : : 0 1 R : C : HC : Z : / : x : i : n : n→PC Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address 9. Electrical Characteristics (A) Operating Voltage & Frequency Vdd ﹕2.3 V ~ 6.3 V Frequency﹕0 Hz ~ 20 MHz (B) Input Voltage : @ V dd＝5.0 V, Temperature＝25 ℃ Vil Vih Port Min. Max. PA, PB Vss 1.0 V RTCC, /MCLR Vss 0.8 V PA, PB 2.0 V Vdd 3.4 V Vdd RTCC, /MCLR ＊Threshold Voltage : This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 2005 /6 VER1.4 MDT1030 Port A, Port B V th＝1.56 V RTCC, /MCLR V il ＝1.4 V, V ih ＝2.9 V (Schmitt Trigger) (C) Output Voltage : @ V dd＝5.0 V, Temperature＝25 ℃, the typical value as followings : PA, PB Port Ioh＝－20.0 mA Voh＝3.50 V Iol ＝20.0 mA Vol ＝0.44 V Ioh＝－5.0 mA Voh＝4.70 V Iol ＝5.0 mA Vol ＝0.20 V (D) Leakage Current @ V dd＝5.0 V, Temperature＝25 ℃, the typical value as followings : Iil － 1.0 µA (Max.) Iih ＋ 1.0 µA (Max.) (E) Sleep Current @WDT－Disable, Temperature＝25 ℃ Vdd＝2.3 ~ 6.3 V, dI d＜1.0 µA @WDT－Enable, Temperature＝25 ℃, the typical value as followings : Vdd＝2.3 V Idd＜1.0 µA Vdd＝3.0 V Idd＝2.0 µA Vdd＝4.0 V Idd＝5.0 µA Vdd＝5.0 V Idd＝12.0 µA Vdd＝6.3 V Idd＝20.0 µA (F) Operating Current / Voltage Temperature＝25 ℃, the typical value as followings : This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 2005 /6 VER1.4 MDT1030 (i) OSC Type＝RC ; WDT－Enable; @ V dd＝5.0 V Cext. (F) 3P 20P 100P 300P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 12.4 M 1.9 m 10.0 K 7.0 M 1.1 m 47.0 K 1.7 M 310.0 µ 100.0 K 842.0 K 180.0 µ 300.0 K 282.5 K 90.0 µ 470.0 K 180.0 K 75.0 µ 4.7 K 5.40 M 900.0 µ 10.0 K 2.80 M 500.0 µ 47.0 K 666.6 K 150.0 µ 100.0 K 318.2 K 100.0 µ 300.0 K 106.5 K 70.0 µ 470.0 K 68.8 K 60.0 µ 4.7 K 1.66 M 320.0 µ 10.0 K 851.0 K 180.0 µ 47.0 K 193.5 K 80.0 µ 100.0 K 92.6 K 65.0 µ 300.0 K 29.8 K 60.0 µ 470.0 K 18.7 K 55.0 µ 4.7 K 695.0 K 160.0 µ 10.0 K 350.0 K 105.0 µ 47.0 K 79.1 K 65.0 µ 100.0 K 35.5 K 60.0 µ 300.0 K 11.9 K 55.0 µ 470.0 K 7.5 K 53.0 µ This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 2005 /6 VER1.4 MDT1030 (ii) OSC Type＝LF (C=20 p); WDT－Enable Voltage/Frequency 32 K 455 K 1M Sleep 2.3 V 4.0 µA X X ＜1.0 µA 3.0 V 8.0 µA 50.0 µA 85.0 µA 2.0 µA 4.0 V 17.0 µA 70.0 µA 140.0 µA 4.0 µA 5.0 V 30.0 µA 110.0 µA 200.0 µA 12.0 µA 6.3 V 58.0 µA 160.0 µA 290.0 µA 20.0 µA (iii) OSC Type＝XT (C=10 p); WDT－Enable Voltage/Frequency 1M 4M 10 M Sleep 2.1 V 65.0 µA 220.0 µA 490.00 µA ＜1.0 µA 3.0 V 120.0 µA 365.0 µA 800.00 µA 2.0 µA 4.0 V 210.0 µA 550.0 µA 1.20 mA 4.0 µA 5.0 V 330.0 µA 750.0 µA 1.70 mA 12.0 µA 6.3 V 530.0 µA 1.2 mA 2.40 mA 20.0 µA (iv) OSC Type＝HF (C=10 p); WDT－Enable Voltage/Frequency 4M 10 M 20 M Sleep 2.1 V 220.0 µA 560.00 µA 950.00 µA ＜1.0 µA 3.0 V 400.0 µA 900.00 µA 1.50 mA 2.0 µA 4.0 V 640.0 µA 1.60 mA 2.60 mA 4.0 µA 5.0 V 900.0 µA 2.40 mA 3.70 mA 12.0 µA 6.3 V 1.4 mA 3.60 mA 5.50 mA 20.0 µA (G) Pull Resistance @ Input Mode : V dd＝3.0 V PORT RTCC /MCLR Pull-High Resistance Pull-Low Resistance Pull-High Resistance Pull-Low Resistance Pull-High Resistance Rhi ＝330.0 KOhm Rlo ＝330.0 KOhm Rhi ＝300.0 KOhm Rlo ＝300.0 KOhm Rhi ＝300.0 KOhm This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 2005 /6 VER1.4 MDT1030 @ Input Mode : V dd＝5.0 V PORT RTCC /MCLR Pull-High Resistance Rhi ＝160.0 KOhm Pull-Low Resistance Rlo ＝160.0 KOhm Pull-High Resistance Rhi ＝150.0 KOhm Pull-Low Resistance Rlo ＝150.0 KOhm Pull-High Resistance Rhi ＝150.0 KOhm p.s. : It is only a reference value for the Pull High/Low Resistance, and the accurate value of the Resistance depends on the various parameter of the Process. But the variation of the value will be not more than 20%. (H) Power Edge-detector Reset Voltage, @ V dd＝5.0 V Vpr≦ 1.1~1.3 V Vpr ﹕Vdd (Power Supply) The Power Edge-detector function can be chosen as either “Enable” or “Disable” : (i) “Disable” condition : No Power EDT function. (ii) “Enable” condition : Under operation condition(Not in Sleep Mode), if the operating voltage(V pr) was not dropped down smoothly, then, 1.1 V≦Vpr≦ 2.0 V, the IC will be reset. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 2005 /6 VER1.4 MDT1030 (I) The basic WDT time-out cycle time Temperature＝25 ℃, the typical value as followings : Voltage (V) Basic WDT time-out cycle time (ms) 2.3 28.90 3.0 25.60 4.0 22.30 5.0 20.00 6.3 18.10 10. Port A and Port B Equivalent Circuit Working Register D QB Data I/P I/O Control Latch I/O Control CK MOS Pull-Hi (Long Channel) Information Sheet Pull Hi/Lo Selection Q Port I/O Pin D MOS Pull-Down (Long Channel) Data O/P Latch Write CK Q Data Bus D QB Read Data I/P Latch Input Resistor TTL Input Level CK This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 2005 /6 VER1.4 MDT1030 11. M CLRB and RTCC Input Equivalent Circuit MOS Pull Hi (Long Channel) R≒1K MCLRB Schmitt Trigger Information Sheet Pull Hi/Lo Selection This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 2005 /6 VER1.4 MDT1030 MOS Pull Hi (Long Channel) R≒1K RTCC Schmitt Trigger MOS Pull Low (Long Channel) Information Sheet Pull Hi/Lo Selection This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 15 2005 /6 VER1.4 MDT1030 12. Block Diagram ROM Stack Two Levels RAM 73×8 2048×12 Port PA0~PA3 4 bits Port A 11 bits 11 bits Program Counters 12 bits Instruction Register Special Register D0~D7 OSC1 OSC2 MCLR Port B Oscillator Circuit Instruction Decoder Control Circuit Data 8-bit Power on Reset Power Down Reset Working Register Status Register ALU 8-bit Timer/Counter Prescale WDT/OST Timer RTCC This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 16 2005 /6 VER1.4 Port PB0~PB7 8 bits MDT1030 13. Capacitor Selection For Crystal Oscillator (a) With built-in Oscillation Capacitors ( Default for HF,XT,LF ) @ Vdd＝2.3V~5.5 V , C1=C2=10P~15P This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 17 2005 /6 VER1.4 MDT1030 (b) Without built-in Oscillation Capacitors @ Vdd＝3.0 V~ 5.0 V Osc. Type HF XT LF Resonator Freq. C1 C2 20 MHz 5 pF ~10 pF 10 pF~30 pF 10 MHz 10 pF ~50 pF 20 pF ~100 pF 4 MHz 10 pF ~50 pF 20 pF ~100 pF 10 MHz 10 pF ~30 pF 10 pF ~50 pF 4 MHz 10 pF ~50 pF 20 pF ~100 pF 1 MHz 10 pF ~30 pF 20 pF ~50 pF 1 MHz 3 pF ~5 pF 3 pF ~5 pF 455 K 10 pF ~30 pF 20 pF ~50 pF 32 K 10 pF ~20 pF 15 pF ~30 pF This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 18 2005 /6 VER1.4 MDT1030 To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range are recommended, but the higher capacitance will increase the start-up time. There do not have built-in Oscillation Capacitors for RC type. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 19 2005 /6 VER1.4