深圳市美芯微电子有限公司 麦肯单片机授权一级代理商 电话：０７５５－３６８５７６０９／２７９４５５５１／２９４９１８８２ 地址：深圳市宝安区宝源路名优产品采购中心Ｂ１区７２１室 MDT10P123 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 2K words EPROM and 80 bytes static RAM. Four comparator inputs with external Vref (not for 18 pin package) are also provided. 4 types of power edge-detector reset: 1.8v , 2.1v , always enable 1.8v and Disable 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler 2 oscillator start-up time can be selected by programming option: 150 μs,20ms On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O (for 18 pins package), 14 I/O (for 20 pins package),16 I/O (for 22/24 pins package) pins with their own independent direction control 16 I/O pins own independent weak pull-high and can be enabled by software. WDT can be enabled by software if WDT Disable is selected in user option. 2. Features Fully CMOS static design 8-bit data bus On chip EPROM size : 2 K words Internal RAM size : 80 bytes (72 general purpose registers, 8 special registers) 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3V ~ 5.5 V Internal RC 4MHz frequency Addressing modes include direct, indirect and relative addressing modes Power-on Reset (POR), 4 Channel comparators Sleep Mode for power saving 3. Applications The application areas of this MDT10P123 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral … etc This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.1 2010/06 Ver. 1.0 MDT10P123 4. Pin Assignment MDT10P123P11 MDT10P123S11 PA5 1 20 PA4/VREF PA2/CIC2 2 19 PA1/CIC1 PA3/CIC3 3 18 PA0/CIC0 RTCC 4 17 NC /MCLR 5 16 OSC2 Vss 6 15 Vdd PB0 7 14 PB7 PB1 8 13 PB6 PB2 9 12 PB5 PB3 10 11 PB4 MDT10P123K11 PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 PA6 PA4/VREF PA1/CIC1 PA0/CIC0 NC OSC2 Vdd PB7 PB6 PB5 PB4 MDT10P123S21 NC PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 1 2 3 4 5 6 7 8 9 10 PB2 11 PB3 12 24 23 22 21 20 19 18 17 16 15 NC PA6 PA4/VREF PA1/CIC1 PA0/CIC0 NC OSC2 Vdd PB7 PB6 14 PB5 13 PB4 This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.2 2010/06 Ver. 1.0 MDT10P123 5.Order Information MARK ROM (Words) RAM (Bytes) I/O Comparators Timer (8 bit) Package Mil MDT10P123S21 2.0K 80 16 4 1 24-SOP 300 mil MDT10P123K11 2.0K 80 16 4 1 22-SKINNY 300 mil MDT10P123P11 2.0K 80 14 4 1 20-DIP 300 mil MDT10P123S11 2.0K 80 14 4 1 20-SOP 300 mil This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.3 2010/06 Ver. 1.0 MDT10P123 6. Block Diagram Stack Two Levels RAM 72X8 EPROM 2K x 14 (MDT10P123) Port B 11 bits Program Counters Port PB0~PB7 8 bits (Pull hi) 11 bits 14 bits Instruction Register Special Registers D0~D7 OSC2 MCLR Port PA0~PA7 (22,24 pins) PA0~PA5 (20 pins) PA0~PA3 (18 pins) 8 bits Port A (pull hi) Oscillator Circuit Instruction Decoder Control Circuit CMR0~CMR5 Comparator mode Register Data 8-bit Power on Reset Power Down Reset Working Register Status Register ALU 8-bit Timer/Counter WDT/OST Timer Prescale RTCC This specification are subject to be changed without notice. Any latest information pleasevisit preview http;//www.mx mcu.com.cn Please http;//www.mdtic.com.tw P.4 2010/06 Ver. 1.0 MDT10P123 7. Pin Function Description Pin Name I/O Function Description PA0~PA7 I/O PA0~PA3 : TTL input level or comparator input PA4 : TTL input level or comparator VREF input PA5~PA7 : TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC2 O Clock out Vdd Power supply Vss Ground NC Unused ,do not connect 8. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07 Control register for comparator 08~0F Internal RAM, General Purpose Registers 10~1F Internal RAM, Memory bank 0 30~3F Internal RAM, Memory bank 1 50~5F Internal RAM, Memory bank 2 70~7F Internal RAM, memory bank 3 This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.5 2010/06 Ver. 1.0 MDT10P123 (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK A10 A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b6-b5 LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF Time overflow Flag bit page ROM Page select bit : 5-6 00 : 000H --- 1FFH 01 : 200H --- 3FFH 10 : 400H --- 5FFH 11 : 600H --- 7FFH 7 —— General purpose bit This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.6 2010/06 Ver. 1.0 MDT10P123 (5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only “1” Indirect Addressing Mode (6) PORT A : R5 PA7~PA0, I/O Register for 22, 24 pins PA5~PA0, I/O Register for 20 pins PA3~PA0, I/O Register for 18 pins (7) PORT B : R6 PB7~PB0, I/O Register (8) CMR(Comparator Mode Register) Bit 0 : R7 Function 0: Define PA0 as TTL input 1: Define PA0 as comparator input 1 0: Define PA1 as TTL input 1: Define PA1 as comparator input 2 0: Define PA2 as TTL input 1: Define PA2 as comparator input 3 0: Define PA3 as TTL input 1: Define PA3 as comparator input 5-4 Reference Voltage select 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF (External pin and PA4 must be set to input) 7-6 General purpose bits This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.7 2010/06 Ver. 1.0 MDT10P123 (9) TMR (Time Mode Register) Bit Symbol 2—0 PS2—0 3 PSC 4 TCE 5 TCS 6 PHEN 7 WDTEN Function Prescaler Value RTCC rate WDT rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 1:8 0 1 0 1:4 1 : 16 0 1 1 1:8 1 0 0 1 : 16 1 : 32 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal select : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin Global Pull High Enable bit： 0 — Enable weak internal Pull High 1 — Disable weak internal Pull High Watchdog timer Enable bit : 0 — Enable WDT 1 — Disable WDT (10) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (11) Set Pull high resistors The Pull high register is “write-only” ＝“0”, Disable I/O pin Pull high resistor ＝“1”, Enable I/O pin Pull high resistor Do the CPIO instructions twice within three instructions on the same I/O port,the second CPIO instruction will enable the I/O pins pull-hi when global pull high Enable. Correct instruction sequence to enable pull-high Ex1: LDWI 0FFH CPIO 06H ←First：set PortB I/O LDWI 0FFH ←Second CPIO 06H ←Third：set PortB Pull hi This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.8 2010/06 Ver. 1.0 MDT10P123 Ex2： LDWI 0FFH CPIO 06H CPIO 06H ←First：set PortB I/O ←Second：set PortB Pull hi Incorrect instruction sequence to enable pull-high Ex1: (over three instructions) LDWI 0FFH CPIO 06H ←First：set PortB I/O LDWI 0FFH ←Second NOP ←Third CPIO 06H ←Fourth：set PortB I/O Ex2： LDWI CPIO CPIO (Different port) 0FFH 06H ←First：set PortB I/O 05H ←set PortA I/O (11) EPROM Option by writer programming : OST 150 us 20ms WDT Disable Enable Description Oscillator Start-up Time 150 us Oscillator Start-up Time 20 ms Description Watchdog timer disable all the time (can be enabled by software,if software WDT enable) Watchdog timer enable all the time (always enable) PED Disable Low level Mid level L(all on) PED disable 1.8V 2.1V always Enable 1.8V Description Security Disable Enable Security Disable Security Enable Description This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.9 2010/06 Ver. 1.0 MDT10P123 Software WDT Description Enable WDT can be enabled by software Disable WDT can’t be enabled by software Freq x 2 Enable Disable I/O pull-hi Enable Disable CLKOUT Enable Disable Reset on Err Enable Disable Comparators Enable Disable Description System clock is doubled (8MHz) System clock is 4MHz Description Allow software to enable independent I/O pin pull-high Disable all pull-high resistors Description Allow OSC2 to output CLKOUT signal OSC2 will be floating Description The MCU will be reset if two illegal instructions are executed continuously. Disable the illegal instruction reset function Description Allow software to enable comparators Disable all comparators (B) Program Memory Address 000- 7FF 7FF Description Program memory The starting address of the power on, external reset or WDT This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.10 2010/06 Ver. 1.0 MDT10P123 9. Reset Condition for all Registers Register Address Power-On Reset /MCLR Reset WDT Reset CPIO A －－ 1111 1111 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 1111 1111 TMR －－ 1111 1111 1111 1111 1111 1111 IAR 00h － － － RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu PC 02h 1111 1111 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h 100x xxxx 100u uuuu 1uuu uuuu PORT A 05h xxxx xxxx uuuuuuuu uuuu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu CMR 07h 0000 0000 uuuu uuuu uuuu uuuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) U u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.11 2010/06 Ver. 1.0 MDT10P123 10. Instruction Set Mnemonic Function Operands 010000 00000000 NOP No operation None 010000 00000001 Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode TF, PF 010000 00000011 Load W to TMODE register 0→WT, stop OSC W→TMODE Return Stack→PC Control I/O port register W→CPIO Store W to register W→R Load register R→t Z I→W None [R(0~3)↔R(4~7 )]→t R + 1→t None Instruction Code CLRWT TMODE 010000 00000100 RET R Operating Status None None 010000 00000rrr CPIO 010001 1rrrrrrr STWR 011000 trrrrrrr LDR 111010 iiiiiiii LDWI I Load immediate to W 010111 trrrrrrr SWAPR R, t Swap halves register 011001 trrrrrrr INCR Increment register 011010 trrrrrrr INCRSZ R, t 011011 trrrrrrr ADDWR R, t Increment register, skip if zero Add W and register 011100 trrrrrrr SUBWR R, t Subtract W from register 011101 trrrrrrr DECR Decrement register 011110 trrrrrrr 010010 trrrrrrr DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii 010100 trrrrrrr IORWI i XORWR R, t Inclu. OR W and immediate i ∪ W→W R ♁ W→t Z 110110 iiiiiiii 011111 trrrrrrr XORWI i COMR R, t Z Complement register i ♁ W→W /R→t 010110 trrrrrrr RRR R, t Rotate right register C 010101 trrrrrrr RLR R, t Rotate left register 010000 1xxxxxxx CLRW Clear working register R(n) →R(n-1), C→R(7), (0)→C R(n)→r(n+1), C→R(0), (7)→C 0→W 010001 0rrrrrrr CLRR Clear register 0→R Z 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None R R, t R, t R, t R Exclu. OR W and register Exclu. OR W and immediate r None None R + 1→t Z None W + R→t C, HC, Z R ﹣W→t (R+/W+1→t) R ﹣1→t C, HC, Z R ﹣1→t Z None Z Z C Z This specification are subject to be changed without notice. Any latest information pleasevisit preview http;//www.mx mcu.com.cn Please http;//www.mdtic.com.tw P.12 2010/06 Ver. 1.0 MDT10P123 Instruction Code 0011bb brrrrrrr Mnemonic Operands BTSS R, b Function Operating Bit Test, skip if set 100nnn nnnnnnnn LCALL n Long CALL subroutine 101nnn nnnnnnnn LJUMP n Long JUMP to address 110000 nnnnnnnn CALL n Call subroutine 110001 iiiiiiii i RTWI 11001n nnnnnnnn JUMP n Status Skip if R(b)=1 None n→PC, PC+1→Stack n→PC None n→PC, PC+1→Stack Return,place immediate to W Stack→PC,i→ W JUMP to address n→PC None None None None Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND n : : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ Immediate address b t : : Bit position Target 0 : Working register 1 : General register R : General register address C : Carry flag HC : Half carry Z : Zero flag / : Complement x : Don’t care i : Immediate data ( 8 bits ) This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.13 2010/06 Ver. 1.0 MDT10P123 11. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Vdd Operating voltage Min Typ Max Unit 2.3 5.5 V VIL Input Low Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V -0.6 -0.6 1.0 1.0 V V VIH Input high Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V 2.0 3.3 Vdd Vdd V V IIL Input leakage current Vdd=5V +/-1 µA Output Low Voltage PA, PB Vdd=5V, IOL=20mA 0.5 V Vdd=5V, IOL=5mA 0.2 V Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vdd＝2.3 ~ 6.0 V 3.4 4.5 V V Vdd＝2.3 V Vdd＝3.0 V Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 1 1.5 5.0 7.0 15 VOL VOH Output High Voltage PA, PB Islp Sleep current (WDT disable) Sleep current (WDT enable) Islp Low level Mid level Twdt The basic WDT time-out cycle Vdd＝2.3 V Vdd＝3.0 V time Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V Vpr Power Edge-detector Reset Voltage 0.1 1.6 1.9 1.0 μA μA μA μA μA μA 1.8 2.1 V V 28.5 25.0 21.9 20.3 19.1 mS mS mS mS mS TFLT /MCLR filter Vdd＝5.0 V 600 nS Idd Comparator Supply current (one comparator) Vdd=5.0v 15 μA Vref Input reference voltage Vdd=2.5v ~6.0v Comparator Response time V-=Vdd/4, V+=V- ± 0.2v Vdd=5.0v , V- = Vref V+ = (PA0~PA3) Vdd-0.8v 8 V μS This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.14 2010/06 Ver. 1.0 MDT10P123 Sym Description Condition Min Tcmp V-=Vdd/2, V+=V- ± 0.2v V-=Vdd3/4, V+=V- ± 0.2v V-=VDD-0.8,V+=V± 0.2v Typ Max Unit μS μS μS 8 8 8 12. Operating Current 12.1 Internal RC 4MHz frequency Operating Temperature：-40°C<TA<80°C Freq Tolerance ±1 Type 4.00 MHz ±2.5 4.00 MHz ±1.5 4.00 MHz conditions At VDD 4=V and Temperature=25°C 2.5V < VDD < 5.5V -40°C < TA < 80°C 12.2、OSC Type＝IRC4M；WDT－Enable；PED=Disable；Temperature＝25℃ Vdd Idd 5.5V 700 uA 5.0V 630 uA 4.0V 460 uA 3.0V 320 uA 2.5V 260 uA 2.3V 235 uA 12.3 Power Edge-detector Reset Voltage (Not in Sleep Mode), Vdd＝5.0 V (PED: Enable) Vpr ﹕Vdd (Power Supply) Vpr(Low level)≦1.6~1.8 V Vpr(Mid level)≦1.9~2.1 V PS. If PED_Enable then Internal Power_on_reset will be off This specification are subject to be changed without notice. Any latest information pleasevisit preview http;//www.mx mcu.com.cn Please http;//www.mdtic.com.tw P.15 2010/06 Ver. 1.0 MDT10P123 13. Port A Equivalent Circuit PA0-PA3 C o n tro l P u ll-h ig h P u ll h ig h R e s is to r Q D I/O C o n tro l I/O C o n tro l L a tc h C K Q B P o rt I/O P in D D a ta O /P L a tc h W rite QB G In p u t R e s is to r D a ta Bus 0 R ea d G T T L in p u t le v e l D QB D a ta I/P L a tc h S + 1 VREF c o m p a ra to r le v e l C o m p a rto r C o n tro l PA4 Control Pull-high Pull high Resistor Q D I/O Control C K I/O Control Latch Q B Port I/O Pin D Data O/P Latch W rite G Q B Input Resistor Data Bus Rea d G com parator enable D QB Data I/P Latch TTL Input Level 3 2 Vref 1 S0 S1 CM R_4 CM R_5 0 3/4 VDD 1/2 VDD 1/4 VDD This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.16 2010/06 Ver. 1.0 MDT10P123 PA5-PA7 Control Pull-high Pull high Resistor D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write Q B G Data Bus Rea d Port B D QB G Data I/P Latch TTL Input Level Input Resistor Equivalent Circuit Control Pull-high Pull high Resistor D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G Data Bus Q B D QB Rea d G Data I/P Latch TTL Input Level Input Resistor This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.17 2010/06 Ver. 1.0 MDT10P123 13. MCLRB and RTCC Input Equivalent Circuit R≒1K MCLRB Schmitt Trigger R≒1K RTCC Schmitt Trigger This specification are subject to be changed without notice. Any latest information please preview http;//www.mx mcu.com.cn Please visit http;//www.mdtic.com.tw P.18 2010/06 Ver. 1.0