深圳市美芯微电子有限公司麦肯单片机授权一级代理商 电话：０７５５－３６８５７６０９／２７９４５５５１／２９４９１８８２ 地址：深圳市宝安区宝源路名优产品采购中心Ｂ１区７２１室 1. 12 I/O pins own independent direction control. 12 I/O pins own independent weak pull-high and can be enabled by software. WDT can be enabled by software if WDT Disable is selected in user option. General Description This ROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve high speed, small size, the low power and high noise immunity. On chip memory includes 2K words EPROM and 80 bytes static RAM. 2. Features 3. The followings are some of the features on the hardware and software : Fully CMOS static design 8-bit data bus On chip EPROM size : 2 K words Internal RAM size : 80 bytes (73 general purpose registers, 7 special registers) 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3 V ~ 5.5 V Internal RC 4MHz frequency Addressing modes include direct, indirect and relative addressing modes Power-on Reset (POR) 4 types of power edge-detector reset: 1.8v , 2.1v , always enable 1.8v and Disable Sleep Mode for power saving 2 oscillator start-up time can be selected by programming option： MDT10P158 Applications The application areas of this MDT10P158 range from appliance motor control and high speed automotive to low power remote transmitters /receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral … etc. 150 μs,20ms 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer(WDT) This specification are subject to be changed without notice. Any latest information pleasevisit preview http;//www.mx mcu.com.cn please http;//www.mdtic.com.tw P.1 2011/01 Ver. 1.1 MDT10P158 4. Pin Assignment MDT10P158P11 MDT10P158S11 PA2 1 18 PA1 PA3 RTCC /MCLR VSS PB0 PB1 PB2 PB3 5. 2 3 4 5 6 7 8 9 17 16 15 14 13 12 11 10 MDT10P158SS11 PA2 PA3 RTCC /MCLR VSS VSS PB0 PB1 PB2 PB3 PA0 N/C OSC2 VDD PB7 PB6 PB5 PB4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA1 PA0 N/C OSC2 VDD VDD PB7 PB6 PB5 PB4 Order Information MARK MDT10P158P11 MDT10P158S11 MDT10P158SS11 12 Timer (8 bit) 1 73 12 1 18-SOP 300 mil 73 12 1 20-SSOP 209 mil ROM (Words) 2K RAM (Bytes) 73 2K 2K I/O Package Mil 18-DIP 300 mil This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.2 2011/01 Ver. 1.1 MDT10P158 6. Block Diagram EPROM Stack Two Levels RAM 73 x 8 2048 x 14 11 bits Program Counters Port A (pull hi) 11 bits 14 bits Instruction Register Special Registers D0~D7 OSC2 MCLR Port PB0~PB7 8 bits Port B (pull hi) Oscillator Circuit Instruction Decoder Control Circuit Data 8-bit Power on Reset Power Down Reset Working Register ALU 8-bit Timer/Counter Port PA0~PA3 4 bits Prescale Status Register WDT/OST Timer RTCC This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.2 2011/01 Ver. 1.1 MDT10P158 7. 8. Pin Function Description Pin Name I/O Function Description PA0~PA3 I/O Port A, TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC2 O Clock out Vdd Power supply Vss Ground Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07~1F Internal RAM, Memory bank 0 30~3F Internal RAM, Memory bank 1 50~5F Internal RAM, Memory bank 2 70~7F Internal RAM, memory bank 3 (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.3 2011/01 Ver. 1.1 MDT10P158 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 JUMP, LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK A10 A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b6 b5 RTWI, RET --- from STACK LJUMP, LCALL – from instruction word Write PC --- from ALU JUMP, CALL, LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF WDT Timer overflow Flag bit PAGE ROM page select bit : 6—5 00 : Page 0, 000H --- 1FFH 01 : Page 1, 200H --- 3FFH 10 : Page 2, 400H --- 5FFH 11 : Page 3, 600H --- 7FFH 7 —— General purpose bit This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.4 2011/01 Ver. 1.1 MDT10P158 (5) MSR (Memory Bank Select Register) : R4 Memory Bank Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only, always read as “1” Indirect Addressing Mode (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register (8) TMR (Time Mode Register) Bit Symbol Prescaler Value 2—0 PS2—0 3 PSC 4 TCE 5 TCS 6 PHEN 7 WDTEN Function RTCC rate WDT rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1 : 16 1:8 1 0 0 1 : 32 1 : 16 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin Global Pull High Enable bit : 0 — Enable weak internal Pull High 1 — Disable weak internal Pull High This bit will be ignored if the “I/O pull-hi” is disable in user option. Watchdog timer Enable bit : 0 — Enable WDT 1 — Disable WDT This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.5 2011/01 Ver. 1.1 MDT10P158 (9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (10)Set Pull hi mode The Pull hi register is “write-only” ＝“0”, Disable I/O pin Pull hi ＝“1”, Enable I/O pin Pull hi Do the CPIO instructions twice within three instructions on the same I/O port,the second CPIO instruction will enable the I/O pins pull-hi when global pull high Enable. Correct instruction sequence to enable pull-high Ex1: LDWI 0FFH CPIO 06H ←First：set PortB to input LDWI 0FFH ←Second CPIO 06H ←Third：enable Pull high of PB0~7 Ex2： LDWI 0FFH CPIO 06H CPIO 06H ←First：set PortB to input ←Second：enable Pull high of PB0~7 Incorrect instruction sequence to enable pull-high Ex1: (over three instructions) LDWI 0FFH CPIO 06H ←First：set PortB to input LDWI 0FFH ←Second NOP ←Third CPIO 06H ←Fourth：set PortB to input Ex2： (Different port) LDWI 0FFH CPIO 06H ←First：set PortB to input CPIO 05H ←set PortA to input (11) EPROM Option by writer programming : OST 150 us Description Oscillator Start-up Time 150 us 20ms Oscillator Start-up Time 20 ms WDT Description Watchdog timer disable all the time (can be enabled by software,if software WDT enable) Disable Enable Watchdog timer enable all the time (always enable) This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.6 2011/01 Ver. 1.1 MDT10P158 PED Disable Description PED disable Low level 1.8V Mid level 2.1V L(all on) always Enable 1.8V Security Disable Description Security Disable Enable Security Enable Software WDT Enable Disable Description WDT can be enabled by software WDT can’t be enabled by software Freq x 2 Enable Disable Description System clock is doubled (8MHz) System clock is 4MHz I/O pull-hi Enable Disable CLKOUT Enable Disable Reset on Err Enable Disable Description Allow software to enable independent I/O pin pull-high Disable all pull-high resistors Description Allow OSC2 to output CLKOUT signal OSC2 will be floating Description The MCU will be reset if two illegal instructions are executed continuously. Disable the illegal instruction reset function (12) Program Memory Address 000-7FF 7FF Description Program memory The starting address of power on, external reset or WDT time-out reset. This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.7 2011/01 Ver. 1.1 MDT10P158 9. Reset Condition for all Registers Register Address Power-On Reset /MCLR or WDT Reset CPIO A －－ 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 TMR －－ 1111 1111 1111 1111 IAR 00h － － RTCC 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu MSR 04h 100x xxxx 100u uuuu PORT A 05h - - - - xxxx - - - - uuuu PORT B 06h xxxx xxxx uuuu uuuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) u u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 10. Instruction Set : Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode 0→WT, stop OSC TF, PF 010000 00000011 TMODE Load W to TMODE register W→TMODE None 010000 00000100 RET Return Stack→PC None 010000 00000rrr CPIO R Control I/O port register W→CPIO r None 010001 1rrrrrrr STWR R Store W to register W→R None 011000 trrrrrrr LDR R, t Load register R→t 111010 iiiiiiii LDWI I Load immediate to W 010111 trrrrrrr SWAPR R, t Swap halves register I→W [R(0~3) ↔R(4~7)]→t Z None None This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.8 2011/01 Ver. 1.1 MDT10P158 Instruction Code Mnemonic Operands Function Operating Status 011001 trrrrrrr INCR R, t Increment register R + 1→t Z 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t None 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R ﹣W→t or (R+/W+1→t) R ﹣1→t 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t None 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 110110 iiiiiiii XORWI i Exclu. OR W and immediate i ♁ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR R, t Rotate right register C 010101 trrrrrrr RLR R, t Rotate left register 010000 1xxxxxxx CLRW Clear working register R(n) →R(n-1), C→R(7), R(0)→C R(n)→r(n+1), C→R(0), R(7)→C 0→W 010001 0rrrrrrr CLRR Clear register 0→R Z 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 1000nn nnnnnnnn LCALL n Long CALL subroutine None 1010nn nnnnnnnn LJUMP n Long JUMP to address n→PC, PC+1→Stack n→PC 110000 nnnnnnnn CALL n Call subroutine None 110001 iiiiiiii RTWI i Return, place immediate to W n→PC, PC+1→Stack Stack→PC,i→W None 11001n nnnnnnnn JUMP n JUMP to address n→PC None R Z C Z None Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t : Bit position : Target 0 : Working register 1 : General register R : General register address C : Carry flag HC : Half carry Z : Zero flag / : Complement x : Don’t care i : Immediate data ( 8 bits ) n : Immediate address This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.9 2011/01 Ver. 1.1 MDT10P158 11. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Vdd Operating voltage Min Typ Max Unit 2.3 5.5 V VIL Input Low Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V -0.6 -0.6 1.0 1.0 V V VIH Input high Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V 2.0 3.3 Vdd Vdd V V IIL Vdd=5V +/-1 µA Input leakage current VOL Output Low Voltage PA, PB Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA 0.5 0.2 V V Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vdd＝2.3 ~ 6.0 V 3.4 4.5 V V Islp Sleep current (WDT enable) Vdd＝2.3 V Vdd＝3.0 V Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 1 1.2 3.0 5.0 10 Vpr Power Edge-detector Reset Voltage Low level Mid level VOH Output High Voltage PA, PB Islp Sleep current (WDT disable) 0.1 1.6 1.9 1.0 μA μA μA μA μA μA 1.8 2.1 V V Twdt The basic WDT time-out cycle Vdd＝2.3 V Vdd＝3.0 V time Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 28.5 25.0 21.9 20.3 19.1 mS mS mS mS mS Vdd＝5.0 V 600 nS TFLT /MCLR filter This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.10 2011/01 Ver. 1.1 MDT10P158 Operating Current 12.1 Internal RC 4MHz frequency Operating Temperature：-40°C<TA<80°C Freq Tolerance ±1 Typ 4.00 MHz ±2.5 4.00 MHz ±1.5 4.00 MHz conditions At VDD 4=V and Temperature=25°C 2.5V < VDD < 5.5V -40°C < TA < 80°C 12.2、OSC Type＝IRC4M；WDT－Enable；PED=Disable；Temperature＝25℃ Vdd Idd 5.5V 700 uA 5.0V 630 uA 4.0V 460 uA 3.0V 320 uA 2.5V 260 uA 2.3V 235 uA 12.3、Power Edge-detector Reset Voltage (Not in Sleep Mode), Vdd＝5.0 V (PED:Enable) Vpr(Low level)≦1.6~1.8 V Vpr ﹕Vdd (Power Supply) Vpr(Mid level)≦1.9~2.1 V PS. If PED_Enable then Internal Power_on_reset will be off This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.11 2011/01 Ver. 1.1 MDT10P158 12. Port A and Port B Equivalent Circuit Control Pull-high Pull high Resistor D C K I/O Control I/O Q Contr ol Latch Q B Port I/O Pin D Data O/P Latch Q G B Write Data Bus Rea d Q D B Data I/P G Latch TTL Input Level Input Resistor This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.12 2011/01 Ver. 1.1 MDT10P158 13. MCLRB and RTCC Input Equivalent Circuit MCLRB R≒1K Schmitt Trigger R≒1K RTCC Schmitt Trigger This specification are subject to be changed without notice. Any latest information please visit visit http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.13 2011/01 Ver. 1.1